SCALAR_INT_MODE_P check in bb_ok_for_noce_convert_multiple_sets.
- Allow rewiring of multiple regs.
- Refactor code with noce_multiple_sets_info.
- Remove old code for subregs.
Manolis Tsamis (4):
ifcvt: handle sequences that clobber flags in
noce_convert_multiple_sets
-by: Manolis Tsamis
---
(no changes since v1)
gcc/ifcvt.cc | 49 +++--
1 file changed, 19 insertions(+), 30 deletions(-)
diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index a0af553b9ff..3273aeca125 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -3375,20
On Tue, Jul 18, 2023 at 9:38 PM Richard Sandiford
wrote:
>
> Manolis Tsamis writes:
> > On Tue, Jul 18, 2023 at 1:12 AM Richard Sandiford
> > wrote:
> >>
> >> Manolis Tsamis writes:
> >> > noce_convert_multiple_sets has been int
): Remove old code.
Signed-off-by: Manolis Tsamis
---
(no changes since v1)
gcc/ifcvt.cc | 38 --
1 file changed, 38 deletions(-)
diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index ecc0cbabef9..3b4b873612c 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -3449,44
/ifcvt_multiple_sets_arithm.c: New test.
Signed-off-by: Manolis Tsamis
---
Changes in v3:
- Add SCALAR_INT_MODE_P check in bb_ok_for_noce_convert_multiple_sets.
- Allow rewiring of multiple regs.
- Refactor code with noce_multiple_sets_info.
- Remove old code for subregs.
gcc/ifcvt.cc
(struct noce_multiple_sets_info): Introduce new struct
noce_multiple_sets_info to store info for noce_convert_multiple_sets.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/ifcvt_multiple_sets_rewire.c: New test.
Signed-off-by: Manolis Tsamis
---
(no changes since v1)
gcc/ifcvt.cc
Hi Roger,
I've (accidentally) found a codegen regression that I bisected down to
this patch.
For these two functions:
typedef struct {
float minx, miny;
float maxx, maxy;
} AABB;
int TestOverlap(AABB a, AABB b) {
return a.minx <= b.maxx
&& a.miny <= b.maxy
&& a.maxx >= b.minx
regards,
> Roger
> --
>
> > -Original Message-
> > From: Manolis Tsamis
> > Sent: 01 September 2023 11:45
> > To: Uros Bizjak
> > Cc: Roger Sayle ; gcc-patches@gcc.gnu.org
> > Subject: Re: [x86_64 PATCH] Improve __int128 argument passing (in
&g
On Tue, Sep 12, 2023 at 3:47 AM Jeff Law wrote:
>
>
>
> On 9/9/23 02:46, Manolis Tsamis wrote:
> > This is a new RTL pass that tries to optimize memory offset calculations
> > by moving them from add immediate instructions to the memory loads/stores.
> >
.
* fold-mem-offsets.cc: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fold-mem-offsets-1.c: New test.
* gcc.target/riscv/fold-mem-offsets-2.c: New test.
* gcc.target/riscv/fold-mem-offsets-3.c: New test.
Signed-off-by: Manolis Tsamis
---
Changes in v5
: 97
548: 101
557: 9
AArch64:
500: 71
502: 318
505: 0
520: 23
523: 205
525: 73
531: 7
541: 56
548: 0
557: 2
x86-64:
500: 8
502: 16
505: 0
520: 4
523: 5
525: 2
531: 0
541: 0
548: 0
557: 0
Thanks,
Manolis
On Sat, Sep 9, 2023 at 11:47 AM Manolis Tsamis
.
* fold-mem-offsets.cc: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fold-mem-offsets-1.c: New test.
* gcc.target/riscv/fold-mem-offsets-2.c: New test.
* gcc.target/riscv/fold-mem-offsets-3.c: New test.
Signed-off-by: Manolis Tsamis
---
Changes in v7
On Tue, Oct 10, 2023 at 5:15 PM Jeff Law wrote:
>
>
>
> On 10/10/23 05:59, Manolis Tsamis wrote:
>
> >> It's a code quality issue as long as we don't transform the code into
> >> movl $0, -18874240, at which point it would become a correctness issue.
> >>
This version has been bootstrapped and tested to cause no regressions
in both x86 and Aarch64.
Manolis
On Mon, Oct 16, 2023 at 9:01 PM Manolis Tsamis wrote:
>
> This is a new RTL pass that tries to optimize memory offset calculations
> by moving them from add immediate ins
Hi all,
Pinging once more (
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628820.html).
Manolis
On Mon, Sep 18, 2023 at 11:18 AM Manolis Tsamis wrote:
>
> Kind ping for V3 of these ifcvt changes
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628820.html
>
> Th
Kind ping for V3 of these ifcvt changes
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628820.html
Thanks,
Manolis
On Wed, Aug 30, 2023 at 1:14 PM Manolis Tsamis wrote:
>
>
> noce_convert_multiple_sets has been introduced and extended over time to
> handle
> if conver
.
* fold-mem-offsets.cc: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fold-mem-offsets-1.c: New test.
* gcc.target/riscv/fold-mem-offsets-2.c: New test.
* gcc.target/riscv/fold-mem-offsets-3.c: New test.
Signed-off-by: Manolis Tsamis
---
Changes in v6
On Fri, Sep 29, 2023 at 10:22 PM Jeff Law wrote:
>
>
>
> On 9/12/23 04:13, Manolis Tsamis wrote:
>
> >>> +
> >>> +/* Get the single reaching definition of an instruction inside a BB.
> >>> + The definition is desired for REG used in INSN.
>
On Fri, Oct 6, 2023 at 8:57 PM Jeff Law wrote:
>
>
>
> On 10/6/23 08:17, Manolis Tsamis wrote:
> SNIP
> >> So I was ready to ACK, but realized there weren't any testresults for a
> >> primary platform mentioned. So I ran this on x86.
> >>
> &g
On Thu, Oct 5, 2023 at 5:54 PM Jeff Law wrote:
>
>
>
> On 10/3/23 05:45, Manolis Tsamis wrote:
> > This is a new RTL pass that tries to optimize memory offset calculations
>
> > +
> > +/* If INSN is a root memory instruction then compute a potentially new
&
On Thu, Oct 5, 2023 at 1:05 AM Jeff Law wrote:
>
>
>
> On 10/3/23 05:45, Manolis Tsamis wrote:
> > This is a new RTL pass that tries to optimize memory offset calculations
> > by moving them from add immediate instructions to the memory loads/stores.
> >
:03 AM Jeff Law wrote:
>
>
>
> On 8/30/23 04:14, Manolis Tsamis wrote:
> > This code used to handle register replacement issues with SUBREG before
> > simplify_replace_rtx was introduced. This should not be needed anymore as
> > new_val has the correct mod
Hi Jeff,
Indeed, that sounds like a good idea. I will make this separate and
send it after the required testing.
I'll see what can be done about a testcase.
Best,
Manolis
On Sat, Nov 11, 2023 at 1:20 AM Jeff Law wrote:
>
>
>
> On 8/30/23 04:13, Manolis Tsamis wrote:
>
On Thu, Oct 19, 2023 at 10:46 PM Richard Sandiford
wrote:
>
> Manolis Tsamis writes:
> > Currently the operations allowed for if conversion of a basic block with
> > multiple sets are few, namely REG, SUBREG and CONST_INT (as controlled by
> > bb_ok_for_no
57.xz_r 379572090003 379057409041 514680962 0.14%
> > 557.xz_r 953117469352 952680431430 437037922 0.05%
> > 557.xz_r 536859579650 536456690164 402889486 0.08%
> > 18421773405376
Signed-off-by: Manolis Tsamis
gcc/ChangeLog:
* config/riscv/riscv.cc (struct machine_function): Add array to store
register wrapping information.
(riscv_for_each_saved_reg): Skip registers that are wrapped separetely.
(riscv_get_separate_components): New function
On Tue, Oct 18, 2022 at 8:35 PM Palmer Dabbelt wrote:
>
> On Tue, 18 Oct 2022 08:57:37 PDT (-0700), j...@ventanamicro.com wrote:
> >
> > Just a couple more comments in-line.
> >
> > On 10/18/22 09:18, Manolis Tsamis wrote:
> >>
> >>>> +/
On Wed, Oct 19, 2022 at 8:16 PM Jeff Law via Gcc-patches
wrote:
>
>
> On 10/18/22 11:35, Palmer Dabbelt wrote:
> >
> >> I would have expected things to work fine with libcalls, perhaps with
> >> the exception of the save/restore libcalls. So that needs deeper
> >> investigation.
> >
> > The
On Wed, Oct 19, 2022 at 8:16 PM Jeff Law via Gcc-patches
wrote:
>
>
> On 10/18/22 11:35, Palmer Dabbelt wrote:
> >
> >> I would have expected things to work fine with libcalls, perhaps with
> >> the exception of the save/restore libcalls. So that needs deeper
> >> investigation.
> >
> > The
On Tue, Oct 18, 2022 at 8:35 PM Palmer Dabbelt wrote:
>
> On Tue, 18 Oct 2022 08:57:37 PDT (-0700), j...@ventanamicro.com wrote:
> >
> > Just a couple more comments in-line.
> >
> > On 10/18/22 09:18, Manolis Tsamis wrote:
> >>
> >>>> +/
cmp w2, w1
bhi .L20
The effect is similar for x86-64.
gcc/ChangeLog:
* match.pd: Simplify vector shift + bit_and + multiply in some cases.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/swar_to_vec_cmp.c: New test.
Signed-off-by: Manolis Tsamis
On Tue, Dec 20, 2022 at 2:23 PM Manolis Tsamis wrote:
>
> When using SWAR (SIMD in a register) techniques a comparison operation within
> such a register can be made by using a combination of shifts, bitwise and and
> multiplication. If code using this scheme i
Hi Richard and Tamar,
I just wanted to ping you about this patch. Is there a chance to get
this into GCC13?
Thanks,
Manolis
On Tue, Dec 20, 2022 at 2:31 PM Manolis Tsamis wrote:
>
> On Tue, Dec 20, 2022 at 2:23 PM Manolis Tsamis
> wrote:
> >
> > When using SWA
On Wed, Nov 30, 2022 at 9:44 AM Richard Biener
wrote:
>
> On Tue, Nov 29, 2022 at 11:05 AM Manolis Tsamis
> wrote:
> >
> > When using SWAR (SIMD in a register) techniques a comparison operation
> > within
> > such a register can be made by using
.
(input_edge): Likewise.
* tree-inline.cc (copy_bb): Likewise.
* value-prof.cc (gimple_sc): Add function to create guarded
specializations.
* value-prof.h (gimple_sc): Likewise.
Signed-off-by: Manolis Tsamis
---
Changes in v2:
- Added params ipa-guarded
(ipa_fn_summary_t::duplicate): Likewise.
> > (analyze_function_body): Likewise.
> > (estimate_edge_size_and_time): Likewise.
> > (remap_edge_summaries): Likewise.
> > * ipa-inline-transform.cc (inline_transform): Likewise.
&g
Hi all,
based on everyone's comments I have sent a v2 of this patch that can
be found here
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/607472.html
As per Richard's comments the pattern now uses vec_cond_expr instead and
includes other fixes as requested.
Also based on Tamar's
cmp w2, w1
bhi .L20
The effect is similar for x86-64.
Signed-off-by: Manolis Tsamis
gcc/ChangeLog:
* match.pd: Simplify vector shift + bit_and + multiply in some cases.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/swar_to_vec_cmp.c: New test
On Wed, Nov 30, 2022 at 9:44 AM Richard Biener
wrote:
>
> On Tue, Nov 29, 2022 at 11:05 AM Manolis Tsamis
> wrote:
> >
> > When using SWAR (SIMD in a register) techniques a comparison operation
> > within
> > such a register can be made by using
On Sun, Nov 13, 2022 at 3:33 AM Jeff Law via Gcc-patches
wrote:
>
>
> On 11/7/22 15:07, Palmer Dabbelt wrote:
> > On Thu, 03 Nov 2022 15:23:28 PDT (-0700), j...@ventanamicro.com wrote:
> >>
> >> On 11/2/22 18:26, Palmer Dabbelt wrote:
> >>>
> > I also tried to remove that restriction but it
Signed-off-by: Manolis Tsamis
gcc/ChangeLog:
* config/riscv/riscv.cc (struct machine_function): Add array to store
register wrapping information.
(riscv_for_each_saved_reg): Skip registers that are wrapped separetely.
(riscv_get_separate_components): New function
On Thu, Nov 17, 2022 at 4:09 AM Jeff Law wrote:
>
>
> On 11/16/22 03:26, Manolis Tsamis wrote:
> > On Sun, Nov 13, 2022 at 3:33 AM Jeff Law via Gcc-patches
> > wrote:
> >>
> >> On 11/7/22 15:07, Palmer Dabbelt wrote:
> >>> On Thu, 03 Nov 202
On Fri, Jan 13, 2023 at 7:49 PM Martin Jambor wrote:
>
> Hello,
>
> sorry for getting to this quite late. I have only had a quick glance at
> ipa-cp.cc hunks so far.
>
Hi Martin,
Thanks for taking the time to review these.
> On Fri, Dec 16 2022, Manolis Tsamis wrote
(ipa_fn_summary_t::duplicate): Likewise.
> > (analyze_function_body): Likewise.
> > (estimate_edge_size_and_time): Likewise.
> > (remap_edge_summaries): Likewise.
> > * ipa-inline-transform.cc (inline_transform): Likewise.
&g
.
Signed-off-by: Manolis Tsamis
---
gcc/tree-ssa-forwprop.cc | 41 +++-
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/gcc/tree-ssa-forwprop.cc b/gcc/tree-ssa-forwprop.cc
index e34f0888954..93d5043821b 100644
--- a/gcc/tree-ssa-forwprop.cc
+++ b
On Fri, Mar 17, 2023 at 10:31 AM Richard Biener
wrote:
>
> On Thu, Mar 16, 2023 at 4:27 PM Manolis Tsamis
> wrote:
> >
> > For this C testcase:
> >
> > void g();
> > void f(unsigned int *a)
> > {
> > if (++*a == 1)
> > g();
/ifcvt_multiple_sets_arithm.c: New test.
Signed-off-by: Manolis Tsamis
---
Changes in v2:
- Change "conditional moves" to "conditional instructions"
in bb_ok_for_noce_convert_multiple_sets's comment.
gcc/ifcvt.cc | 60 ++
-by: Manolis Tsamis
---
(no changes since v1)
gcc/ifcvt.cc | 49 +++--
1 file changed, 19 insertions(+), 30 deletions(-)
diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index a0af553b9ff..3273aeca125 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -3375,20
On Wed, Jul 12, 2023 at 5:14 PM Jeff Law wrote:
>
>
>
> On 7/12/23 03:12, Manolis Tsamis wrote:
> > On Mon, Jul 10, 2023 at 12:58 AM Hans-Peter Nilsson
> > wrote:
> >>
> >> On Sun, 9 Jul 2023, Hans-Peter Nilsson wrote:
> >&
"conditional moves" to "conditional instructions"
in bb_ok_for_noce_convert_multiple_sets's comment.
Manolis Tsamis (2):
ifcvt: handle sequences that clobber flags in
noce_convert_multiple_sets
ifcvt: Allow more operations in multiple set if conve
I resent this with just the change in the comment.
OK to merge?
Manolis
On Tue, Jul 4, 2023 at 5:32 PM Manolis Tsamis wrote:
>
> On Mon, Jul 3, 2023 at 12:12 PM Robin Dapp wrote:
> >
> > Hi Manolis,
> >
> > that looks like a nice enhancement of what's already po
.
* fold-mem-offsets.cc: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fold-mem-offsets-1.c: New test.
* gcc.target/riscv/fold-mem-offsets-2.c: New test.
* gcc.target/riscv/fold-mem-offsets-3.c: New test.
Signed-off-by: Manolis Tsamis
---
Changes in v3
functions to test whether the newly synthesized memory
instruction is valid.
Any ideas on how to solve this issue is appreciated.
Manolis
On Thu, Jul 13, 2023 at 5:13 PM Manolis Tsamis wrote:
>
> This is a new RTL pass that tries to optimize memory offset calculations
> by moving them
On Fri, Jul 14, 2023 at 8:35 AM Jeff Law wrote:
>
>
>
> On 7/13/23 09:05, Manolis Tsamis wrote:
> > In this version I have made f-m-o able to also eliminate constant
> > moves in addition to the add constant instructions.
> > This increases the number of simp
Hi Richard,
Thanks for your insightful reply.
On Tue, Jul 18, 2023 at 1:12 AM Richard Sandiford
wrote:
>
> Manolis Tsamis writes:
> > noce_convert_multiple_sets has been introduced and extended over time to
> > handle
> > if conversion for blocks with multiple sets. C
Hi Vineet, Jeff,
On Wed, Jul 19, 2023 at 7:31 AM Jeff Law wrote:
>
>
>
> On 7/18/23 17:42, Vineet Gupta wrote:
> > Hi Manolis,
> >
> > On 7/18/23 11:01, Jeff Law via Gcc-patches wrote:
> >> Vineet @ Rivos has indicated he stumbled across an ICE with the V3
> >> code. Hopefully he'll get a
On Mon, Jul 3, 2023 at 12:12 PM Robin Dapp wrote:
>
> Hi Manolis,
>
> that looks like a nice enhancement of what's already possible. The concern
> I had some years back already was that this function would eventually
> grow and cannibalize on some of what the other functions in ifcvt already
>
On Mon, Jul 10, 2023 at 12:58 AM Hans-Peter Nilsson wrote:
>
> On Sun, 9 Jul 2023, Hans-Peter Nilsson wrote:
>
> > On Thu, 15 Jun 2023, Manolis Tsamis wrote:
> >
> > > This is a new RTL pass that tries to optimize memory offset calculations
> > > by movi
On Mon, Jul 10, 2023 at 12:37 AM Hans-Peter Nilsson wrote:
>
> On Thu, 15 Jun 2023, Manolis Tsamis wrote:
>
> > This is a new RTL pass that tries to optimize memory offset calculations
> > by moving them from add immediate instructions to the memory loads/stores.
> > F
On Thu, May 25, 2023 at 4:38 PM Jeff Law wrote:
>
>
>
> On 5/25/23 06:35, Manolis Tsamis wrote:
> > Propagation of the stack pointer in cprop_hardreg is currenty forbidden
> > in all cases, due to maybe_mode_change returning NULL. Relax this
> > restriction and
On Tue, May 30, 2023 at 2:30 AM Jeff Law wrote:
>
>
>
> On 5/25/23 08:02, Manolis Tsamis wrote:
> > On Thu, May 25, 2023 at 4:53 PM Richard Biener via Gcc-patches
> > wrote:
> >>
> >> On Thu, May 25, 2023 at 3:32 PM Jeff Law via Gcc-patches
> >&g
On Thu, May 25, 2023 at 4:42 PM Jeff Law wrote:
>
>
>
> On 5/25/23 06:35, Manolis Tsamis wrote:
> >
> > This pass tries to optimize memory offset calculations by moving them
> > from add immediate instructions to the memory loads/stores.
> > For example it ca
On Thu, May 25, 2023 at 4:03 PM Richard Biener
wrote:
>
> On Thu, May 25, 2023 at 2:36 PM Manolis Tsamis
> wrote:
> >
> > Implementation of the new RISC-V optimization pass for memory offset
> > calculations, documentation and testcases.
>
> Why do fwprop o
:
* gcc.target/riscv/fold-mem-offsets-1.c: New test.
* gcc.target/riscv/fold-mem-offsets-2.c: New test.
* gcc.target/riscv/fold-mem-offsets-3.c: New test.
Signed-off-by: Manolis Tsamis
---
gcc/config.gcc| 2 +-
gcc/config/riscv/riscv-fold-mem
split
this into two different patches (in which cases some of the testcases
included will fail temporarily).
Manolis Tsamis (2):
Implementation of new RISCV optimizations pass: fold-mem-offsets.
cprop_hardreg: Enable propagation of the stack pointer if possible.
gcc/config.gcc
.
Signed-off-by: Manolis Tsamis
---
gcc/regcprop.cc | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/regcprop.cc b/gcc/regcprop.cc
index f426f4fedcd..6cbfadb181f 100644
--- a/gcc/regcprop.cc
+++ b/gcc/regcprop.cc
@@ -422,7 +422,12 @@ maybe_mode_change (machine_mode
On Thu, May 25, 2023 at 4:53 PM Richard Biener via Gcc-patches
wrote:
>
> On Thu, May 25, 2023 at 3:32 PM Jeff Law via Gcc-patches
> wrote:
> >
> >
> >
> > On 5/25/23 07:01, Richard Biener via Gcc-patches wrote:
> > > On Thu, May 25, 20
Hi Jeff,
Yes that one has changed; I changed the implementation based on your feedback.
Thanks,
Manolis
On Thu, Jun 8, 2023 at 1:18 AM Jeff Law wrote:
>
>
>
> On 5/25/23 06:35, Manolis Tsamis wrote:
> > Propagation of the stack pointer in cprop_hardreg is currenty forbidde
On Fri, Jun 9, 2023 at 3:57 AM Jeff Law wrote:
>
>
>
> On 5/25/23 06:35, Manolis Tsamis wrote:
> > Implementation of the new RISC-V optimization pass for memory offset
> > calculations, documentation and testcases.
> >
> > gcc/ChangeLog:
> >
> >
On Thu, Jun 8, 2023 at 8:37 AM Jeff Law wrote:
>
>
>
> On 5/25/23 06:35, Manolis Tsamis wrote:
> > Implementation of the new RISC-V optimization pass for memory offset
> > calculations, documentation and testcases.
> >
> > gcc/ChangeLog:
> >
> >
On Sat, Jun 10, 2023 at 6:49 PM Jeff Law wrote:
>
>
>
> On 5/25/23 06:35, Manolis Tsamis wrote:
> > Implementation of the new RISC-V optimization pass for memory offset
> > calculations, documentation and testcases.
> >
> > gcc/ChangeLog:
> >
> >
Hi all,
I'm pinging to discuss again if we want to move this forward for GCC14.
I did some testing again and I haven't been able to find obvious
regressions, including testing the code from PR86270 and PR70359 that
Richard mentioned.
I still believe that zero can be considered a special case
Hi all,
It is true that regcprop currently does not propagate sp and hence
leela is not optimized, but from what I see this should be something
we can address.
The reason that the propagation fails is this check that I have added
when I introduced maybe_copy_reg_attrs:
else if (REG_POINTER
Hi Jeff,
Thanks for all the info!
Then I'll prepare/test a patch that removes this regcprop limitation
and send it out.
I have already tested that this change is enough to make fmo optimize
leela as well.
Manolis
On Fri, Aug 4, 2023 at 7:23 PM Jeff Law wrote:
>
>
>
> On 8/4/23 03
.
* fold-mem-offsets.cc: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fold-mem-offsets-1.c: New test.
* gcc.target/riscv/fold-mem-offsets-2.c: New test.
* gcc.target/riscv/fold-mem-offsets-3.c: New test.
Signed-off-by: Manolis Tsamis
---
Changes in v4
I have sent out a new v4 of this
(https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626502.html).
In the new version I both restore the INSN_CODE as mentioned here and
I also call recog when I commit the offset change (because there may
be a change from no offset to some offsets).
I have also
function.
(find_oldest_value_reg): Inline stack_pointer_rtx check.
(copyprop_hardreg_forward_1): Inline stack_pointer_rtx check.
Signed-off-by: Manolis Tsamis
---
gcc/regcprop.cc | 56 -
1 file changed, 23 insertions(+), 33 deletions
r changes the testcase will still fold insn 39).
Please let me know If you have any other feedback on this.
Thanks!
Manolis
On Wed, Aug 9, 2023 at 7:22 PM Jeff Law wrote:
>
>
>
> On 8/7/23 08:33, Manolis Tsamis wrote:
> > This is a new RTL pass that tries to optimize memory
On Mon, Jun 19, 2023 at 7:57 PM Thiago Jung Bauermann
wrote:
>
>
> Hello Manolis,
>
> Philipp Tomsich writes:
>
> > On Thu, 8 Jun 2023 at 00:18, Jeff Law wrote:
> >>
> >> On 5/25/23 06:35, Manolis Tsamis wrote:
> >> > Propagation of th
/ifcvt_multiple_sets_arithm.c: New test.
Signed-off-by: Manolis Tsamis
---
gcc/ifcvt.cc | 60 +++--
.../aarch64/ifcvt_multiple_sets_arithm.c | 67 +++
2 files changed, 108 insertions(+), 19 deletions(-)
create mode 100644
gcc/testsuite/gcc.target
.
Tested on aarch64 and x64; On x64 some tests that use __builtin_rint are
failing with an ICE but I believe that it's not an issue of this change.
force_operand crashes when (and:DF (not:DF (reg:DF 88)) (reg/v:DF 83 [ x ]))
is provided through emit_conditional_move.
Manolis Tsamis (2):
ifcvt
-by: Manolis Tsamis
---
gcc/ifcvt.cc | 49 +++--
1 file changed, 19 insertions(+), 30 deletions(-)
diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index 0b180b4568f..fd1ce8a1049 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -3373,20 +3373,6
On Thu, Jun 15, 2023 at 6:04 PM Jeff Law wrote:
>
>
>
> On 5/25/23 07:42, Jeff Law wrote:
>
> > Thanks Manolis. Do you happen to know if this includes the fixes I
> > passed along to Philipp a few months back? My recollection is one fixed
> > stale DF data which prevented an ICE during
unnecessary verbosity in some comments.
Thanks,
Manolis
On Tue, Jun 13, 2023 at 12:58 AM Jeff Law wrote:
>
>
>
> On 6/12/23 01:32, Manolis Tsamis wrote:
>
> >>
> >>> + for (ref_link = ref_chain; ref_link; ref_link = ref_link->next)
> >>> +
.
* fold-mem-offsets.cc: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fold-mem-offsets-1.c: New test.
* gcc.target/riscv/fold-mem-offsets-2.c: New test.
* gcc.target/riscv/fold-mem-offsets-3.c: New test.
Signed-off-by: Manolis Tsamis
---
Changes in v2
On Tue, Nov 28, 2023 at 12:12 PM Richard Sandiford
wrote:
>
> Manolis Tsamis writes:
> > On Thu, Nov 23, 2023 at 11:01 PM Richard Sandiford
> > wrote:
> >>
> >> Manolis Tsamis writes:
> >> > The existing implementation of need_cmov_or_rewire
Hi Jakub,
Thanks a lot for tracking this down and providing both testcases and a
fix. Some thoughts below.
On Mon, Nov 27, 2023 at 10:52 PM Jakub Jelinek wrote:
>
> On Mon, Oct 16, 2023 at 01:11:01PM -0600, Jeff Law wrote:
> > > gcc/ChangeLog:
> > >
> > > * Makefile.in: Add
On Tue, Nov 28, 2023 at 12:53 PM Jakub Jelinek wrote:
>
> On Tue, Nov 28, 2023 at 11:45:58AM +0200, Manolis Tsamis wrote:
> > > But, while get_single_def_in_bb checks for
> > > if (DF_INSN_LUID (def) > DF_INSN_LUID (insn))
> > > return NULL;
On Thu, Nov 23, 2023 at 11:01 PM Richard Sandiford
wrote:
>
> Manolis Tsamis writes:
> > The existing implementation of need_cmov_or_rewire and
> > noce_convert_multiple_sets_1 assumes that sets are either REG or SUBREG.
> > This commit enchances them so they can han
On Thu, Nov 23, 2023 at 11:01 PM Richard Sandiford
wrote:
>
> Manolis Tsamis writes:
> > The existing implementation of need_cmov_or_rewire and
> > noce_convert_multiple_sets_1 assumes that sets are either REG or SUBREG.
> > This commit enchances them so they can han
(noce_convert_multiple_sets_1): Remove old code.
Signed-off-by: Manolis Tsamis
---
Changes in v2:
- Made standalone patch.
gcc/ifcvt.cc | 38 --
1 file changed, 38 deletions(-)
diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index a0af553b9ff..be42609a848 100644
--- a/gcc
Retested, made independent of the rest of the series and submitted as
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637662.html.
Manolis
On Mon, Nov 13, 2023 at 2:43 PM Manolis Tsamis wrote:
>
> Yes, my finding back then was that this is leftover code from the
> initial imple
(struct noce_multiple_sets_info): Introduce new struct
noce_multiple_sets_info to store info for noce_convert_multiple_sets.
Signed-off-by: Manolis Tsamis
---
Changes in v2:
- Made standalone patch.
- Better comments, some more checks.
gcc/ifcvt.cc | 252
Bootstrapped and tested on x86 and aarch64. This only assumes that the
mode of what simplify_replace_rtx returns is the same with its first
argument.
Thanks,
Manolis
On Tue, Nov 21, 2023 at 8:04 PM Manolis Tsamis wrote:
>
> This code used to handle SUBREG for register replacement when
I have bootstrapped and checked for no testsuite regressions on x86 and aarch64.
Thanks,
Manolis
On Tue, Nov 21, 2023 at 8:00 PM Manolis Tsamis wrote:
>
> The existing implementation of need_cmov_or_rewire and
> noce_convert_multiple_sets_1 assumes that sets are either REG
I have made this independent from the rest of the series, cleaned up
some comments and moved some code to its original position.
Re-submitted as
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637660.html.
Manolis
On Mon, Nov 13, 2023 at 2:40 PM Manolis Tsamis wrote:
>
> H
-by: Manolis Tsamis
---
gcc/match.pd| 30 ++
gcc/testsuite/gcc.dg/pr109393.c | 16
2 files changed, 46 insertions(+)
create mode 100644 gcc/testsuite/gcc.dg/pr109393.c
diff --git a/gcc/match.pd b/gcc/match.pd
index d401e7503e6..13c828ba70d
(struct noce_multiple_sets_info): Introduce new struct
noce_multiple_sets_info to store info for noce_convert_multiple_sets.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/ifcvt_multiple_sets_rewire.c: New test.
Signed-off-by: Manolis Tsamis
---
(no changes since v1)
gcc/ifcvt.cc
): Use modified_in_p instead.
(noce_convert_multiple_sets_1): Don't use seq2 if it clobbers cc_cmp.
Refactor the code that sets read_comparison.
Signed-off-by: Manolis Tsamis
---
(no changes since v1)
gcc/ifcvt.cc | 106 ---
1 file
unnecessary hardcoded list of allowed ops in
bb_ok_for_noce_convert_multiple_sets.
- Set need_cmov based on BB live_out instead of REG_DEAD notes.
- Fix preexisting issues and improve the code that sets read_comparison.
Manolis Tsamis (3):
[RFC] ifcvt: handle sequences
1 - 100 of 130 matches
Mail list logo
