Richard Sandiford rdsandif...@googlemail.com writes:
Sorry for the slow review.
And my slow response :-)
Matthew Fortune matthew.fort...@imgtec.com writes:
The initial support for MIP64r6 is intentionally minimal to make
review
easier. Performance enhancements and use of new MIPS64r6
-Original Message-
From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
Sent: 17 July 2014 21:18
To: gcc-patches@gcc.gnu.org
Cc: Jaydeep Patil; Matthew Fortune
Subject: [committed] Fix MIPS p5600 scheduler
The p5600 scheduler wasn't restricting itself to -mtune=p5600 and so
On Jul 17, 2014, at 11:47 PM, Matthew Fortune matthew.fort...@imgtec.com
wrote:
Thanks for fixing this. I'm afraid I managed to get confused between
failures we had seen sporadically in our development work and thought
they were known regressions on trunk waiting to be fixed when actually
Jürgen Urban juergenur...@gmx.de writes:
Hello Richard,
Jürgen Urban juergenur...@gmx.de writes:
The problem happens with the r5900 hard float configurations, e.g.:
configure --target=mipsel-linux-gnu --with-float=hard --with-fpu=single
--with-arch=r5900
I created the attached
Jürgen Urban juergenur...@gmx.dewrites:
Jürgen Urban juergenur...@gmx.de writes:
Hello Richard,
Jürgen Urban juergenur...@gmx.de writes:
Is this something you
have recently developed outside of the mainline kernel or does it already
exist.
I'm not aware of such logic in the MIPS
Fixes for high level libraries should also be
high level (dmult vs __FLT_MAX_EXP__); i.e. there should be no change in
a
different package which is specific for MIPS. The type double should
stay
double and is handled without a problem when the FPU is 32 bit in ABI
o32.
The
Moore, Catherine catherine_mo...@mentor.com writes:
The patch looks good. Please fix up these couple of nits prior to
committing.
OK, thanks for the second read through. One further amendment below, I'll
aim to commit later today.
Index: gcc/config/mips/mips.c
(for MIPS) https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01481.html,
although I have not been able to test this as there doesn't seem to be
any working MIPS/Loongson hardware in the Compile Farm;
I will post a patch to remove vec_shl and only support vec_shr for
little endian. This is on the
Moore, Catherine catherine_mo...@mentor.com writes:
The patch looks good. Please fix up these couple of nits prior to
committing.
OK, thanks for the second read through. One further amendment below,
I'll aim to commit later today.
Yes, that's better.
Committed as r217446
This patch adds new triplets: mips*-img-linux* and mips*-img-elf*
The purpose of these triplets is essentially to provide a clear separation
between tools which support mips32r5 and below and tools which support
mips32r6 and above.
Thanks,
Matthew
/
* configure.ac: Add mips-img-elf
Eric Botcazou ebotca...@adacore.com writes:
IIRC, fill_eager and its related friends are all speculative in some
way
and aren't those precisely the ones that are causing us problems.
Also
note we have backends working around this stuff in fairly blunt ways:
I'd say that the PA back-end
OK to apply?
2014-11-17 Maciej W. Rozycki ma...@codesourcery.com
gcc/
* gcc/config/mips/mips.md (*jump_absolute): Use a branch when in
range, a jump otherwise.
OK.
I only got my head around this code last week otherwise I wouldn't have
known whether this was
The atomic-compare-exchange-3.c and atomic-op-3.c tests are failing when
using the -mfix-r1 option. This is due to the fact that the delay
slot of the branch instruction that checks if the atomic operation was
not successful can be filled with an operation that returns the output
result.
Maciej W. Rozycki ma...@codesourcery.com writes:
On Mon, 17 Nov 2014, Matthew Fortune wrote:
gcc/
* gcc/config/mips/mips.md (*jump_absolute): Use a branch when in
range, a jump otherwise.
OK.
I only got my head around this code last week otherwise I wouldn't
have known
-Original Message-
From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
Sent: Tuesday, November 18, 2014 12:22 PM
To: Rozycki, Maciej
Cc: gcc-patches@gcc.gnu.org; Moore, Catherine; Eric Christopher
Subject: RE: [PATCH] MIPS/GCC: Unconditional jump generation bug fix
From: Maciej W. Rozycki [mailto:ma...@codesourcery.com]
On Tue, 18 Nov 2014, Andrew Bennett wrote:
Produces (for the atomic operation):
.setnoat
sync
1:
ll $3,0($5)
and $1,$3,$4
bne $1,$7,2f
and
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index
02268f3..368c6f0 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -12997,7 +12997,12 @@ mips_process_sync_loop (rtx_insn *insn, rtx
*operands)
This will sometimes be a delayed branch; see the write
Ok to commit?
gcc/
* config/mips/mips.c (mips_process_sync_loop): Place a nop in the
delay slot of the branch likely instruction.
With an updated ChangeLog to account for the changes in the callers, OK.
Matthew
2014 +0100
Add MIPS .module directive
commit 351cdf24d223290b15fa991e5052ec9e9bd1e284
Author: Matthew Fortune matthew.fort...@imgtec.com
Date: Tue Jul 29 11:27:59 2014 +0100
[MIPS] Implement O32 FPXX, FP64 and FP64A ABI extensions
I have updated the configure check for .module to check
Matthew Fortune matthew.fort...@imgtec.com writes:
(I'm not sure if I need approval from someone else for MIPS specific
top level 'configure' changes. I'm cautiously assuming I do for now.)
FWIW, MIPS maintainership covers all MIPS-specific code and documentation
(except for externally
Andrew Pinski pins...@gmail.com writes:
On Wed, Nov 12, 2014 at 2:56 PM, Matthew Fortune
matthew.fort...@imgtec.com wrote:
Moore, Catherine catherine_mo...@mentor.com writes:
The patch looks good. Please fix up these couple of nits prior to
committing.
OK, thanks
Hi,
I have had to use this patch several times when performing cross testing
but I'm not sure if it is the right fix. The MIPS target testsuite runs
all tests regardless of the current compiler configuration and downgrades
run tests to link tests and then to assembly tests depending on what
Richard Biener richard.guent...@gmail.com writes:
On Sun, Nov 23, 2014 at 10:15 AM, Matthew Fortune
matthew.fort...@imgtec.com wrote:
Hi,
I have had to use this patch several times when performing cross testing
but I'm not sure if it is the right fix. The MIPS target testsuite runs
all
Hi Prachi,
OK with fixes to the changelog entry:
latency not latency. Remember to tab in the changelog entry and split the
line as it will exceed 80 chars. Also two spaces between the date/name and
name/email. E.g.
2014-11-05 Prachi Godbole prachi.godb...@imgtec.com
*
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b577824..7b9b365 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2014-11-25 Matthew Fortune matthew.fort...@imgtec.com
Hi Steve,
You're the lucky recipient of my first review so apologies for being
slow and cautious...
I tried to find a reason why the files were originally separated like this
and I can't see anything obvious. I assume you also found no reason.
Presumably the separation was just to avoid
I talked to Andrew about what files he changed in GCC and created and
tested this new patch. Andrew also mentioned changing some assembly
files in glibc but I don't see any use of '.section .note.GNU-stack' in
any assembly files in glibc (for any platform) so I wasn't planning on
creating a
2014-10-08 Steve Ellcey sell...@mips.com
* config/mips/mti-linux.h (DRIVER_SELF_SPECS): Change
LINUX64_DRIVER_SELF_SPECS to LINUX_DRIVER_SELF_SPECS
OK. I'd agree with obvious here.
Matthew
2014-10-08 Andrew Pinski apin...@cavium.com
* config/mips/mips-cpus.def (octeon3): New cpu.
* config/mips/mips.c (mips_rtx_cost_data): Add octeon3.
(mips_print_operand case 'T', case 't'): Fix a bug as the mode
of the comparison no longer matches mode of the operands.
Hi Catherine/Richard,
I think there may be some impact on register move costs by introducing this
class. Is it worth having mips_canonicalize_move_class return M16_REGS for
M16_STORE_REGS to reduce the effect on costings? Given the extra register is
only $0 then this would seem mostly
Richard Sandiford rdsandif...@googlemail.com writes:
Maciej W. Rozycki ma...@codesourcery.com writes:
On Sat, 12 Apr 2014, Richard Sandiford wrote:
I went ahead and applied the adjusted version of the patch to trunk
as below (because I wanted to add a testcase too).
I believe you
the implementation.
Tested with mips-mti-linux-gnu.
Regards,
Matthew
2014-04-29 Matthew Fortune matthew.fort...@imgtec.com
gcc/
* config/mips/mips-cpus.def: Add PTF_AVOID_ODD_SPREG to generic
mips32, mips32r2, mips64, mips64r2 and loongson3a.
* config/mips/mips.c
Richard Sandiford rdsandif...@googlemail.com writes:
Matthew Fortune matthew.fort...@imgtec.com writes:
Hi Richard,
When MIPSr1 introduced the ability to use odd-numbered
single-precision registers some implementations continued to only
support even-numbered single-precision registers
,
Matthew
2014-04-30 Matthew Fortune matthew.fort...@imgtec.com
gcc/
* config/mips/mips.c: (mips_option_override) Implement -modd-spreg
and defaults.
* config/mips/mips.h: (TARGET_CPU_CPP_BUILTINS) Add _MIPS_SPFPSET
builtin define. (ISA_HAS_ODD_SPREG) Define
]
Sent: 04 May 2014 23:38
To: Matthew Fortune; Richard Sandiford
Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org); Rich Fuhler
Subject: Re: RE: [PATCH, MIPS] Alter default number of single-precision
registers
Hi Matthew：
Test passed on Loongson3a on the case:
void foo (void)
{
register
in a testcase as part of:
http://gcc.gnu.org/ml/gcc-patches/2014-05/msg00401.html
Regards,
Matthew
2014-05-07 Matthew Fortune matthew.fort...@imgtec.com
gcc/
* regcprop.c (copyprop_hardreg_forward_1): Account for
HARD_REGNO_CALL_PART_CLOBBERED.
0001-copyprop-part-clobbered.patch
Richard Sandiford rdsandif...@googlemail.com writes:
Matthew Fortune matthew.fort...@imgtec.com writes:
diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-6.c
b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
new file mode 100644
index 000..2d1b129
--- /dev/null
+++ b/gcc/testsuite
Richard/Vlad,
Richard Sandiford rdsandif...@googlemail.com writes:
Kyrill Tkachov kyrylo.tkac...@arm.com writes:
On 03/05/14 20:21, Richard Sandiford wrote:
...snip...
Hi all,
This caused some testsuite failures on arm:
FAIL: gcc.target/arm/vfp-ldmdbd.c scan-assembler fldmdbd
FAIL:
the order of reviewing and committing the work.
Regards,
Matthew
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On Behalf Of Matthew Fortune
Sent: 07 May 2014 16:22
To: Richard Sandiford
Cc: Joseph Myers (jos...@codesourcery.com); ma
...
Richard Sandiford rdsandif...@googlemail.com writes:
Matthew Fortune matthew.fort...@imgtec.com writes:
*) Dwarf debug for 64-bit values in floating point values for FPXX can't
be strictly correct for both 32-bit and 64-bit registers but opts to
describe one 64-bit register
Richard Sandiford rdsandif...@googlemail.com writes:
Matthew Fortune matthew.fort...@imgtec.com writes:
*) Because GCC can be built to have mfpxx or mfp64 as the default
option
the ASM_SPEC has to handle these specially such that they are not
passed in conjunction with -msingle
Let's step back a bit. Please explain which case you were trying to
handle with the specs patch. Rejecting -msingle-float -mfp64 seems
fine.
Fiddling with the specs to stop that combination reaching the assembler
is what seemed odd.
So, perhaps this is a 'vendor' issue too like some other
You shouldn't need to declare __builtin_* functions anyway. And if a
function can be represented directly with GNU C vector extensions, it's
preferred to implement it that way inline in the header rather than having
built-in functions duplicating existing GNU C functionality. (Look at
what
Mike Stump mikest...@comcast.net writes:
On May 28, 2014, at 7:27 AM, Richard Earnshaw rearn...@arm.com wrote:
Speed of implementation. We're gradually replacing these with proper
builtins, but that takes a lot more work.
As an owner of a port with more builtins that yours, I can offer
Hi Richard,
I've realised that I may need to do 'something' to prevent GCC from loading or
storing DFmode/DImode values to/from FPRs using pairs of SWC1/LWC1 when using
an unaligned address. Initial tests show that when loading from an unaligned
address (4-byte aligned) then GCC loads the two
Richard Sandiford rdsandif...@googlemail.com writes:
Matthew Fortune matthew.fort...@imgtec.com writes:
I've realised that I may need to do 'something' to prevent GCC from
loading or
storing DFmode/DImode values to/from FPRs using pairs of SWC1/LWC1
when using
an unaligned address
Richard Sandiford rdsandif...@googlemail.com writes:
Matthew Fortune matthew.fort...@imgtec.com writes:
MIPSr6 only supports 64-bit registers which naturally leads to needing
-mfp64. MIPSr6 does however also support a single-precision only
variant.
For a single purpose native toolchain
4fc4f1c72e1d226691d4cebf2c5fa6de809fb409 Mon Sep 17 00:00:00 2001
From: Matthew Fortune matthew.fort...@imgtec.com
Date: Sat, 31 May 2014 23:33:21 +0100
Subject: [PATCH] fpxx feature fix
---
gcc/config.gcc |8
gcc/config/mips/mips.c | 34 ++
gcc
This is a small clean-up patch to remove code relating to reloading or moving
mips fcc registers. At some point in the past these registers were allocated
as part of register allocation but they are now statically allocated in the
backend in a round robin fashion. The code for reloading them is
Richard Sandiford rdsandif...@googlemail.com writes:
Matthew Fortune matthew.fort...@imgtec.com writes:
This is a small clean-up patch to remove code relating to reloading or
moving
mips fcc registers. At some point in the past these registers were
allocated
as part of register allocation
On 2014-06-16, 12:12 PM, Robert Suchanek wrote:
Pinging for approval.
This part of the patch will be needed for MIPS16. The second part to
enable
LRA in MIPS has been already approved.
Sorry, Robert. I thought you are waiting for some Richard's comment
(actually he knows the
Alan Lawrence alan.lawre...@arm.com writes:
Patches 7-11 migrate migrate ARM, x86, IA64 (I think), and mostly PowerPC,
to
the new reduc_(plus|[us](min|max))_scal_optab. I have not managed to work
out
how to do the same for MIPS (specifically what I need to add to
mips_expand_vec_reduc), and
gcc/
* config/mips/mips.c (mips_rewrite_small_data_1): Take the context
as a parameter instead of the containing MEM. Iterate over all
subrtxes. Don't return a value.
(mips_rewrite_small_data): Update call accordingly.
OK
gcc/
* config/mips/mips.c: Include rtl-iter.h.
(mips_small_data_pattern_1): Take an rtx rather than an rtx pointer.
Take the context as a parameter instead of the containing MEM.
Iterate over all subrtxes.
(mips_small_data_pattern_p): Update call accordingly.
gcc/
* config/mips/mips.c (mips16_rewrite_pool_refs_info): Delete.
(mips16_rewrite_pool_refs): Take the insn and constant pool as
parameters. Iterate over the instruction's pattern and return void.
(mips16_lay_out_constants): Update accordingly.
OK
gcc/
* config/mips/mips.c (r10k_needs_protection_p_1): Take an rtx
rather than an rtx pointer. Change type of insn from void *
to its real type. Return bool rather than int. Iterate over
all subrtxes here.
(r10k_needs_protection_p_store): Update accordingly.
gcc/
* config/mips/mips.c (mips_kernel_reg_p): Replace with...
(mips_refers_to_kernel_reg_p): ...this new function.
(mips_expand_prologue): Update accordingly.
OK
gcc/
* config/mips/mips.c (mips_sim_insn): Update comment.
(mips_sim_wait_regs_2): Delete.
(mips_sim_wait_regs_1): Use FOR_EACH_SUBRTX_VAR.
OK
gcc/
* config/mips/mips.c (mips_record_lo_sum): Replace with...
(mips_record_lo_sums): ...this new function.
(mips_reorg_process_insns): Update accordingly.
OK
gcc/
* config/mips/mips.c (r10k_needs_protection_p_call): Take a const_rtx
and return a bool. Iterate over all subrtxes here.
(r10k_needs_protection_p): Update accordingly.
OK
gcc/
* config/mips/mips.c (mips_at_reg_p): Delete.
(mips_need_noat_wrapper_p): Use FOR_EACH_SUBRTX.
OK. That should be the last one to cover all changes to use
new rtl iterators for MIPS.
Thanks for splitting this up per change it made it easy to read
through.
Matthew
Zhenqiang Chen zhenqiang.c...@arm.com writes:
For CSiBE, ARM Cortex-m0 result is a little better. A little regression
for
MIPS. Roughly no change for PowerPC.
Do I take it that a little regression for MIPS is so small it can be
considered noise? I haven't had chance to run CSiBE to see the
Do you have an objection to allowing an option to disable these
instructions (despite the reason for wanting to do so)?
Yes this seems like a bad workaround for broken code.
Well, we work around broken hardware all the time. What would you
suggest that Steve do instead?
We work
Moore, Catherine catherine_mo...@mentor.com writes:
Review comments are attached. I will tackle the R6 patch next.
Thanks,
Catherine
Thanks Catherine. Depending on whether the fix to the following
hunk needs discussion I'll make the changes and commit.
static bool
Matthew Fortune matthew.fort...@imgtec.com writes:
Do you have an objection to allowing an option to disable these
instructions (despite the reason for wanting to do so)?
Yes this seems like a bad workaround for broken code.
Well, we work around broken hardware all the time
Hi James,
I think you have a bug in the following hunk where you pass
STORE_MAX_PIECES in place of the optimise for speed flag. I guess you
would need an extra argument to pass a different *_MAX_PIECES value
in.
thanks,
Matthew
@@ -192,8 +184,7 @@ static void write_complex_part (rtx, rtx,
Andrew Pinski pins...@gmail.com writes:
On Thu, Oct 30, 2014 at 11:30 PM, Zhenqiang Chen zhenqiang.c...@arm.com
wrote:
Thank you all for the comments. Patch is updated.
Bootstrap and no make check regression on X86-64.
No make check regression with Cortex-M0 qemu.
No performance
Steve Ellcey sell...@imgtec.com writes:
Here is another MIPS configuration patch, this one allows the mips
configuration to handle the --with-endian, --with-arch, and --with-abi
configure options. Basically instead of having targets set
MIPS_ABI_DEFAULT
and MIPS_ISA_DEFAULT directly in
The patch below fixes the memory cost for P5600.
ChangeLog:
2014-11-05 Prachi Godbole prachi.godb...@imgtec.com
* config/mips/mips.c (mips_rtx_cost_data): Fix memory_letency cost for
p5600.
Please follow these instructions to add yourself to MAINTAINERS in the
write-after-approval
Hi Catherine,
The full patch is attached and the delta from v2 is inline below.
Testing (O32):
MIPS I - FP32, MIPS II - FP32, MIPS II - FPXX
MIPS32 - FP32, MIPS32 - FPXX, MIPS32 - FPXX ODDSPREG,
MIPS32R2 - FP32, MIPS32R2 - FPXX, MIPS32R2 - FPXX ODDSPREG,
MIPS32R2 - FP64, MIPS32R2 - FP64A
One
This patch fixes all failures in the MIPS target tests which were failing
because of
-Wimplicit-int or -Wimplicit-function-declaration.
+2014-11-05 Matthew Fortune matthew.fort...@imgtec.com
+
+ * gcc.target/mips/asm-1.c (bar): Add prototype.
+ * gcc.target/mips/call-1.c (f, h
Sorry to follow myself up. I realised that the new configure options should
be documented in install.texi. The only change from V3 is the
doc/install.texi change.
The MIPS64 tests have completed without regression.
Regards,
Matthew
gcc/
* common/config/mips/mips-common.c
Ping^2
Added Jason as maintainer for dwarf related things.
This hook will be used in the following patch:
https://gcc.gnu.org/ml/gcc-patches/2014-08/msg02172.html
Thanks,
Matthew
Ping.
Thanks,
Matthew
Sent: 07 August 2014 07:21
Please don't add target macros. Add a hook if you
On 09/02/2014 01:59 AM, Matthew Fortune wrote:
gcc/
* target.def (TARGET_DWARF_FRAME_REG_MODE): New target hook.
* targhooks.c (default_dwarf_frame_reg_mode): New function.
* targhooks.h (default_dwarf_frame_reg_mode): New prototype.
* doc/tm.texi.in
Ping!
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On Behalf Of Matthew Fortune
Sent: 18 August 2014 14:25
To: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)
Cc: Richard Sandiford; Eric Christopher (echri...@gmail.com)
Subject
Ping!
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On Behalf Of Matthew Fortune
Sent: 22 August 2014 10:43
To: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org); Eric Christopher
(echri...@gmail.com)
Cc: Moore, Catherine
The patch is ok to commit. I think I made a typo as other analogous
code contains '|='.
Thanks for fixing this, Robert.
The LRA part of this is committed as r215119.
Eric: Is the test OK to commit for MIPS? I suggest removing the
dg-skip-if as the test is for successful compilation, not
Hi Richard,
I'd like to get some more of your thoughts on the ABI implications of MSA.
Generally, any thoughts you have (or anyone else) on the current state of MIPS
ABIs would be welcome. As an example I'm curious whether you see variations of
O32 as being new ABIs or extensions of O32, it
Just wanted to add a couple of MIPS-specific things on top of what Joseph
said:
Matthew Fortune matthew.fort...@imgtec.com writes:
The MSA patch as submitted is another variation of O32 ABI which could
be described as O32+FP64+MSA(+nan2008) and would be link incompatible
with both O32
And as you imply, o32+fp64 is already an established ABI so I think we
have to support the current form alongside any new one. I agree with
Joseph that it'd be better to realign the stack dynamically instead.
This is what x86 does, so it's well tested within gcc.
With glibc, o32+fp64
This patch adds a target macro to allow a backend to override the size
of a dwarf frame register. This is already supported to some extent
by allowing the HARD_REGNO_CALL_PART_CLOBBERED to reduce the size of
a specific register to only that which is saved. However, for the
new MIPS O32 FP64 ABI
Please don't add target macros. Add a hook if you must, but we're
supposed to remove target macros, not add new ones :-)
Thanks Steven, I wasn't sure if there were still things that were
acceptable as macros. There's a lot to get rid of still.
Updated patch using a target hook. I've opted to
Moore, Catherine catherine_mo...@mentor.com writes:
-Original Message-
From: Steve Ellcey [mailto:sell...@mips.com]
Sent: Friday, August 08, 2014 3:42 PM
To: Moore, Catherine; matthew.fort...@imgtec.com; echri...@gmail.com;
2014-08-08 Steve Ellcey sell...@mips.com
*
Matthew Fortune matthew.fort...@imgtec.com writes:
Moore, Catherine catherine_mo...@mentor.com writes:
-Original Message-
From: Steve Ellcey [mailto:sell...@mips.com]
Sent: Friday, August 08, 2014 3:42 PM
To: Moore, Catherine; matthew.fort...@imgtec.com; echri...@gmail.com
Eric Christopher echri...@gmail.com writes:
On Sat, Aug 9, 2014 at 12:00 PM, Matthew Fortune
matthew.fort...@imgtec.com wrote:
Moore, Catherine catherine_mo...@mentor.com writes:
-Original Message-
From: Steve Ellcey [mailto:sell...@mips.com]
Sent: Friday, August 08, 2014 3:42
What is harder to fix about n32 than o32?
-msingle-float with n32 creates 64 bit FPU instructions like dmtc1 and
dmfc1. So I can't compile it for r5900. When I disable it, I get
internal
compiler errors.
That certainly seems like a bug. Can you file a bug report for that with
The secondary_reload_class hook gets called for pseudos which have
not been allocated a hard register. For pseudos with the FP_REGS
class this results in the hook stating that the pseudo must be
reloaded via GR_REGS as it is neither in an FP_REG nor in memory.
This is obviously wasteful as LRA
Ping.
Thanks,
Matthew
Sent: 07 August 2014 07:21
Please don't add target macros. Add a hook if you must, but we're
supposed to remove target macros, not add new ones :-)
Thanks Steven, I wasn't sure if there were still things that were
acceptable as macros. There's a lot to get rid of
/gcc-patches/2014-08/msg01748.html
Do not reload unallocated FP_REGS pseudos via GR_REGS
https://gcc.gnu.org/ml/gcc-patches/2014-08/msg01745.html
Regards,
Matthew
2014-07-31 Matthew Fortune matthew.fort...@imgtec.com
gcc/
* common/config/mips/mips-common.c (mips_handle_option): Ensure
Changelog:
2014-12-03 Prachi Godbole prachi.godb...@imgtec.com
* config/mips/p5600.md (define_automaton, define_cpu_unit): Replace
p5600_agen_pipe and p5600_alu_pipe with p5600_agen_alq_pipe.
(p5600_int_arith_1, p5600_int_arith_2, p5600_int_arith_4): Change
Richard Biener richard.guent...@gmail.com writes:
On Thu, Dec 4, 2014 at 8:59 AM, Benda Xu hero...@gentoo.org wrote:
Hello,
libc could be installed in a directory prefix. This patch provides a
way to specify such a prefix for gcc at configuration time.
I have only tested the patch
Richard Sandiford richard.sandif...@arm.com writes:
Maciej W. Rozycki ma...@codesourcery.com writes:
2014-11-17 Maciej W. Rozycki ma...@codesourcery.com
gcc/
* gcc/config/mips/mips.md (*jump_absolute): Use a branch when in
range, a jump otherwise.
Maciej
location in the
gcc/ChangeLog one?
Thanks,
Matthew
-Original Message-
From: Prachi Godbole
Sent: 26 November 2014 08:40
To: Matthew Fortune; gcc-patches@gcc.gnu.org
Subject: RE: [PATCH][MIPS] Fix P5600 memory cost
Committed with ChangeLog entry fixes.
Prachi
-Original
Moore, Catherine catherine_mo...@mentor.com writes:
Hi Matthew,
-Original Message-
From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
Sent: Friday, November 14, 2014 6:07 PM
Overall, this patch looks really good. It took me a while to get
through it, but I only have
Okay with those changes.
Committed as r218973
Thanks,
Matthew
gcc/
* config.gcc: Support mips*-img-linux* and mips*-img-elf*.
* config/mips/mti-linux.h: Support mips32r6 as being the default
arch.
* config/mips/t-img-elf: New.
* config/mips/t-img-linux: New.
This patch is OK to commit.
Committed as r218975
Thanks,
Matthew
2014-12-24 Steve Ellcey sell...@mips.com
* config/mips/t-mti-linux (MULTILIB_EXCEPTIONS): Add exceptions
for mips32[r1] and mips64[r1] with -mnan=2008.
This is OK, but I think it may be best to fix t-mti-elf at the same
time even though it is probably building but with
2015-01-23 Robert Suchanek robert.sucha...@imgtec.com
* config/mips/mips.c (mips_hard_regno_mode_ok_p): Prohibit
accumulators
for all vector modes.
This seems like a genuine bug and although it can only be triggered by
loongson or paired-single support it probably qualifies
This is a minimal backport of features added to GCC 5 to enable use
of binutils 2.25 with GCC 4.9 for MIPS soft-float builds. Further
details in the PR:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64569
The commits which are being backported are listed below (the last
one is posted but
Andrew Pinski pins...@gmail.com writes:
On Wed, Feb 4, 2015 at 8:46 AM, Matthew Fortune
matthew.fort...@imgtec.com wrote:
Hi Catherine,
I've made a first pass at writing up the MIPS changes for GCC 5.0.
Could you take a read and see what needs some more work?
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