movne r0, r0, lsr #1
orrne r0, r0, #32768
- andsr3, r3, #255
+ subsr2, r2, #1
bne .L3
bx lr
Tested both patches on x86_64-unknown-linux-gnu and
arm-none-linux-gnueabi with no new regressions. Is this OK?
Thanks,
Kugan
Changes the the SUBREG flags to be able to set promoted for sign
(SRP_SIGNED), unsigned (SRP_UNSIGNED), sign and unsigned
(SPR_SIGNED_AND_UNSIGNED) in SUBREG_PROMOTED_VAR_P.
Thanks,
Kugan
gcc/
2014-06-24 Kugan Vivekanandarajah kug...@linaro.org
* gcc/calls.c (precompute_arguments
Sets proper flags on the SUBREG based on value
range info and enables elimination of zext/sext when possible.
Thanks,
Kugan
gcc/
2014-06-24 Kugan Vivekanandarajah kug...@linaro.org
* gcc/calls.c (precompute_arguments: Check is_promoted_for_type
and set the promoted mode
)-volatil == 1))
Am I missing anything here? Please let me know. I am attaching the patch
based on this with your other review comments addressed.
Thanks,
Kugan
gcc/
2014-06-25 Kugan Vivekanandarajah kug...@linaro.org
* calls.c (precompute_arguments): Use new SUBREG_PROMOTED_SET
On 24/06/14 22:21, Jakub Jelinek wrote:
On Tue, Jun 24, 2014 at 09:53:35PM +1000, Kugan wrote:
2014-06-24 Kugan Vivekanandarajah kug...@linaro.org
* gcc/calls.c (precompute_arguments: Check is_promoted_for_type
and set the promoted mode.
(is_promoted_for_type) : New function
On 26/06/14 11:06, Kugan wrote:
On 25/06/14 17:50, Jakub Jelinek wrote:
On Wed, Jun 25, 2014 at 05:21:08PM +1000, Kugan wrote:
The problem with SRP_POINTER 0, SRP_SIGNED 1, SRP_UNSIGNED 2,
SRP_SIGNED_AND_UNSIGNED 3 (as I understand) is that, it will be
incompatible with TYPE_UNSIGNED (tree
On 26/06/14 15:50, Jakub Jelinek wrote:
On Thu, Jun 26, 2014 at 11:06:26AM +1000, Kugan wrote:
Since our aim is to perform single bit checks, why don’t we just use
this representation internally (i.e. _rtx-unchanging = 1 if SRP_SIGNED
and _rtx-volatil = 1 if SRP_UNSIGNED
On 26/06/14 20:12, Jakub Jelinek wrote:
On Thu, Jun 26, 2014 at 07:41:22PM +1000, Kugan wrote:
2014-06-26 Kugan Vivekanandarajah kug...@linaro.org
* calls.c (precompute_arguments): Use new SUBREG_PROMOTED_SET
instead of SUBREG_PROMOTED_UNSIGNED_SET
Missing full stop
On 26/06/14 20:25, Andreas Schwab wrote:
Kugan kugan.vivekanandara...@linaro.org writes:
@@ -5203,24 +5203,25 @@ store_expr (tree exp, rtx target, int call_param_p,
bool nontemporal)
== TYPE_PRECISION (TREE_TYPE (exp)))
{
if (TYPE_UNSIGNED (TREE_TYPE (exp
On 01/07/14 18:21, Kugan wrote:
On 26/06/14 20:12, Jakub Jelinek wrote:
On Thu, Jun 26, 2014 at 07:41:22PM +1000, Kugan wrote:
2014-06-26 Kugan Vivekanandarajah kug...@linaro.org
* calls.c (precompute_arguments): Use new SUBREG_PROMOTED_SET
instead of SUBREG_PROMOTED_UNSIGNED_SET
-linux-gnu, arm-none-linux-gnueabi (using qemu),
aarch64_be-none-elf (Foundation model), aarch64-none-elf
--with-abi=ilp32 (Foundation model) and s390x-ibm-linux (64bit, using
qemu) with no new regression.
Is this OK?
Thanks,
Kugan
gcc/
2014-07-07 Kugan Vivekanandarajah kug...@linaro.org
Thanks foe the review and suggestions.
On 10/07/14 22:15, Richard Biener wrote:
On Mon, Jul 7, 2014 at 8:55 AM, Kugan kugan.vivekanandara...@linaro.org
wrote:
[...]
For -fwrapv, it is due to how PROMOTE_MODE is defined in arm back-end.
In the test-case, a function (which has signed char
tested on qemu for arm-none-linux-gnueabi with no new
regressions.
Please let me know if this is OK?
Thanks,
Kugan
gcc/
2014-057-12 Kugan Vivekanandarajah kug...@linaro.org
* config/arm/arm.c (bdesc_2arg): Fix typo.
(arm_atomic_assign_expand_fenv): Remove The default
On 11/07/14 22:47, Richard Biener wrote:
On Fri, Jul 11, 2014 at 1:52 PM, Kugan
kugan.vivekanandara...@linaro.org wrote:
Thanks foe the review and suggestions.
On 10/07/14 22:15, Richard Biener wrote:
On Mon, Jul 7, 2014 at 8:55 AM, Kugan kugan.vivekanandara...@linaro.org
wrote
On 23/09/14 01:58, Jiong Wang wrote:
On 22/09/14 16:43, Kugan wrote:
AArch64 has the same issue ARM had where the LR register was not used in
leaf functions. This was reported in
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42017. In AArch64, this
test-case need to be added with more live
On 01/10/14 01:00, Jiong Wang wrote:
On 27/09/14 22:20, Kugan wrote:
On 23/09/14 01:58, Jiong Wang wrote:
On 22/09/14 16:43, Kugan wrote:
AArch64 has the same issue ARM had where the LR register was not
used in
leaf functions. This was reported in
https://gcc.gnu.org/bugzilla
one more iteration and converge to the right minimum value.
Attached patch fixes this. Is this OK for stage-1?
Bootstrapped and regression tested on X86_64-unknown-linux-gnu with no
new regressions.
Thanks,
Kugan
gcc/
+2014-04-09 Kugan Vivekanandarajah kug...@linaro.org
+
+ * tree-vrp.c
Ping?
On 10/04/14 06:07, Kugan wrote:
Value range propagation simplifies convergence in vrp_visit_phi_node by
setting minimum to TYPE_MIN when the computed minimum is smaller than
the previous minimum. This can however result in pessimistic value
ranges in some cases.
for example
On 24/04/14 23:05, Richard Biener wrote:
On Wed, Apr 9, 2014 at 10:07 PM, Kugan
kugan.vivekanandara...@linaro.org wrote:
Value range propagation simplifies convergence in vrp_visit_phi_node by
setting minimum to TYPE_MIN when the computed minimum is smaller than
the previous minimum
. Is this OK for trunk?
Thanks,
Kugan
gcc/
+2014-04-27 Kugan Vivekanandarajah kug...@linaro.org
+
+ * config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
+ (arm_builtins) : Add ARM_BUILTIN_LDFPSCR and ARM_BUILTIN_STFPSCR.
+ (bdesc_2arg) : Add description for builtins
. Is this OK for trunk?
Thanks,
Kugan
gcc/
+2014-04-27 Kugan Vivekanandarajah kug...@linaro.org
+
+ * config/aarch64/aarch64.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New
+ define.
+ * config/aarch64/aarch64-builtins.c (arm_builtins) : Add
+ AARCH64_BUILTIN_LDFPSCR
On 28/04/14 21:01, Ramana Radhakrishnan wrote:
On 04/26/14 11:57, Kugan wrote:
Attached patch implements TARGET_ATOMIC_ASSIGN_EXPAND_FENV for AARCH64.
With this, atomic test-case gcc.dg/atomic/c11-atomic-exec-5.c now PASS.
This implementation is based on SPARC and i386 implementations
On 28/04/14 20:29, Ramana Radhakrishnan wrote:
On 04/26/14 11:26, Kugan wrote:
Hi,
Attached patch implements TARGET_ATOMIC_ASSIGN_EXPAND_FENV for ARM. With
this, atomic test-case gcc.dg/atomic/c11-atomic-exec-5.c now PASS.
This implementation is based on SPARC and i386 implementations
+2014-04-29 Kugan Vivekanandarajah kug...@linaro.org
+
+ * config/aarch64/aarch64.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New
+ define.
+ * config/aarch64/aarch64-protos.h (aarch64_atomic_assign_expand_fenv):
+ New function declaration.
+ * config/aarch64/aarch64
On 02/05/14 20:06, Marcus Shawcroft wrote:
On 29 April 2014 03:37, Kugan kugan.vivekanandara...@linaro.org wrote:
On 28/04/14 21:01, Ramana Radhakrishnan wrote:
On 04/26/14 11:57, Kugan wrote:
Attached patch implements TARGET_ATOMIC_ASSIGN_EXPAND_FENV for AARCH64.
With this, atomic test
Ping ?
Thanks,
Kugan
On 02/05/14 22:27, Kugan wrote:
On 02/05/14 20:06, Marcus Shawcroft wrote:
On 29 April 2014 03:37, Kugan kugan.vivekanandara...@linaro.org wrote:
On 28/04/14 21:01, Ramana Radhakrishnan wrote:
On 04/26/14 11:57, Kugan wrote:
Attached patch implements
Ping ?
Thanks,
Kugan
On 02/05/14 19:04, Kugan wrote:
On 02/05/14 10:15, Joseph S. Myers wrote:
It doesn't seem a good idea to me for a host-side GCC file to use the FE_*
names for the target's FE_* values; you'd run into problems if that file
ever ends up including the host's fenv.h
and alternate; this might get confused with this.
Attached RFC patch removes it. regression tested for
aarch64-none-linux-gnu on qemu-aarch64 with now new regression. Is this OK ?
Thanks,
Kugan
gcc/
2014-05-14 Kugan Vivekanandarajah kug...@linaro.org
* config/aarch64/aarch64.c
Hi All,
In AArch64 back-end, BASE_REG_CLASS is defined to be POINTER_REGS.
Shouldn’t this be GENERAL_REGS?
Attached RFC patch makes it GENERAL_REGS. Regression tested for
aarch64-none-linux-gnu on qemu-aarch64 with now new regression. Is this OK ?
Thanks,
Kugan
gcc/
2014-05-15 Kugan
a
lot but others regress). I am looking to see if I can make it perform
better overall. Any suggestions welcome.
Attached experimental patch passes regression but 168.wupwise and
187.facerec miscompares now. I am looking at fixing this as well.
Thanks,
Kugan
gcc/
2014-05-22 Kugan
On 24/05/14 00:06, Christophe Lyon wrote:
Hi,
Since merge from upstream r209283 (210743 in GCC), my build fails on
ARM, because rpc/xdr.h is not found.
Is this expected?
I also have the same issue. I had to build glibc with
--enable-obsolete-rpc to bootstrap now.
Thanks,
Kugan
Ping^2 ?
Thanks,
Kugan
On 12/05/14 09:47, Kugan wrote:
Ping ?
Thanks,
Kugan
On 02/05/14 19:04, Kugan wrote:
On 02/05/14 10:15, Joseph S. Myers wrote:
It doesn't seem a good idea to me for a host-side GCC file to use the FE_*
names for the target's FE_* values; you'd run into problems
On 22/05/14 01:08, Marcus Shawcroft wrote:
On 15 May 2014 01:10, Kugan kugan.vivekanandara...@linaro.org wrote:
Hi All,
AAarch64 back-end defines GENERAL_REGS and CORE_REGS with the same set
of register. Is there any reason why we need this?
Nope an artifact of the early evolution
On 22/05/14 22:18, Richard Earnshaw wrote:
On 22/05/14 00:44, Kugan wrote:
Compiling some applications with -mgeneral-regs-only produces better
code (runs faster) compared to not using it. The difference here is that
when -mgeneral-regs-only is not used, floating point register are also
in thumb1. So these should be conditional on not being
ARM_THUMB1.
Is this OK. Regression tested with no new refression on qemu for
arm-none-linux-gnueabi -march=armv7-a and on arm-none-linux-gnueabi
--with-mode=thumb and -march=armv5t.
Is this OK?
Thanks,
Kugan
gcc/
2014-06-10 Kugan
is, even when -mno-unaligned-access is enabled,
backend will inform vectorizer that it supports misaligned accesses
via TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT.
Attached patch fixes this. Is this OK for trunk?
Thanks,
Kugan
+2014-02-03 Yury Gribov tetra2...@gmail.com
+Kugan
and there is no new
regressions. I am sorry I didn’t mention it when I posted the patch.
Thanks,
Kugan
On 07/02/14 03:54, Christophe Lyon wrote:
On 6 February 2014 10:49, Yury Gribov y.gri...@samsung.com wrote:
Kugan wrote:
Ok if no regressions.
Tested it on qemu for arm-none-linux-gnueabi and there is no new
regressions. I am sorry I didn't mention it when I posted the patch.
Commited
Hi,
Is there any reason why HFmode is not there in arm_preferred_simd_mode?
NEON does support this.
Cross regression tested for arm-none-linux-gnueabi with qemu and no new
regressions.
Attached patch enables this. Is this OK for stage1.
Thanks,
Kugan
gcc/
+2014-02-14 Kugan Vivekanandarajah
On 14/02/14 11:24, Andrew Pinski wrote:
On Thu, Feb 13, 2014 at 4:15 PM, Kugan
kugan.vivekanandara...@linaro.org wrote:
Hi,
Is there any reason why HFmode is not there in arm_preferred_simd_mode?
NEON does support this.
Most likely because there is no support for Half-float
On 14/02/14 14:34, Kugan wrote:
On 14/02/14 11:24, Andrew Pinski wrote:
On Thu, Feb 13, 2014 at 4:15 PM, Kugan
kugan.vivekanandara...@linaro.org wrote:
Hi,
Is there any reason why HFmode is not there in arm_preferred_simd_mode?
NEON does support this.
Most likely because
2014-02-17 Kugan Vivekanandarajah kug...@linaro.org
Index: MAINTAINERS
===
--- MAINTAINERS (revision 207819)
+++ MAINTAINERS (working copy)
@@ -551,6 +551,7 @@
David Ung dav...@mips.com
Neil
. Attached patch fixes
these issues.
Regression tested on qemu-aarch64 for aarch64-none-linux-gnu with no new
regressions.
Is this patch OK?
Thanks,
Kugan
gcc/
+2014-02-21 Kugan Vivekanandarajah kug...@linaro.org
+
+ PR target/60034
+ * aarch64/aarch64.c (aarch64_classify_address): Fix
On 27/02/14 22:32, Marcus Shawcroft wrote:
On 21 February 2014 04:24, Kugan kugan.vivekanandara...@linaro.org wrote:
Compiling inline asm results in ICE (PR60034). Alignment calculation in
aarch64_classify_address for (symbol_ref:DI (*.LANCHOR4) [flags
0x182])) seems wrong here.
Hi Kugan
Ping ?
gcc/
2014-03-03 Kugan Vivekanandarajah kug...@linaro.org
PR target/60034
* aarch64/aarch64.c (aarch64_classify_address): Fix alignment for
section anchor.
gcc/testsuite/
2014-03-03 Kugan Vivekanandarajah kug...@linaro.org
PR target
On 12/03/14 20:07, Marcus Shawcroft wrote:
Hi Kugan
On 3 March 2014 21:56, Kugan kugan.vivekanandara...@linaro.org wrote:
gcc/
2014-03-03 Kugan Vivekanandarajah kug...@linaro.org
PR target/60034
* aarch64/aarch64.c (aarch64_classify_address): Fix alignment
the block alignment irrespective of
SYMBOL_REF_ANCHOR_P().
Thanks for the explanation. Is the attached patch looks OK ?
Thanks,
Kugan
gcc/
2014-03-25 Kugan Vivekanandarajah kug...@linaro.org
PR target/60034
* aarch64/aarch64.c (aarch64_classify_address): Fix alignment
into it based on the
feedback.
Please also note that this pass still doest handle debug instructions
and there are couple regression failures for ARM.
Thanks,
Kugan
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4a51393..1e26172 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13
On 27/08/14 20:01, Uros Bizjak wrote:
Hello!
2014-08-07 Kugan Vivekanandarajah kug...@linaro.org
* calls.c (precompute_arguments): Check
promoted_for_signed_and_unsigned_p and set the promoted mode.
(promoted_for_signed_and_unsigned_p): New function.
(expand_expr_real_1): Check
On 27/08/14 23:02, Kugan wrote:
On 27/08/14 20:01, Uros Bizjak wrote:
Hello!
2014-08-07 Kugan Vivekanandarajah kug...@linaro.org
* calls.c (precompute_arguments): Check
promoted_for_signed_and_unsigned_p and set the promoted mode.
(promoted_for_signed_and_unsigned_p): New function
On 28/08/14 16:44, Marc Glisse wrote:
On Thu, 28 Aug 2014, Kugan wrote:
On 27/08/14 23:02, Kugan wrote:
On 27/08/14 20:01, Uros Bizjak wrote:
Hello!
2014-08-07 Kugan Vivekanandarajah kug...@linaro.org
* calls.c (precompute_arguments): Check
promoted_for_signed_and_unsigned_p and set
On 27/08/14 20:07, Richard Biener wrote:
On Wed, Aug 27, 2014 at 12:01 PM, Uros Bizjak ubiz...@gmail.com wrote:
Hello!
2014-08-07 Kugan Vivekanandarajah kug...@linaro.org
* calls.c (precompute_arguments): Check
promoted_for_signed_and_unsigned_p and set the promoted mode
,
Here is an attempt to do the value range computation in promoted_mode's
type when it is overflowing. Bootstrapped on x86-84.
Based on your feedback, I will do more testing on this.
Thanks for your time,
Kugan
gcc/ChangeLog:
2014-09-04 Kugan Vivekanandarajah kug...@linaro.org
* tree-ssa
can fix this?
Thanks again,
Kugan
and regression tested on x86_64 and arm.
Thanks,
Kugan
gcc/testsuite
2014-09-05 Kugan Vivekanandarajah kug...@linaro.org
PR target/43550
* gcc.target/arm/pr43550.c: New test.
gcc/
2014-09-05 Kugan Vivekanandarajah kug...@linaro.org
PR target/43550
* builtins.c
adding and setting the overflow/wrap around flag to
range_info. We now set static_flag for VR_RANG/VR_ANTI_RANGE. If we go
back to the max + 1, min - 1 for VR_ANTI_RANGE, we can use this
static_flag to encode overflow/wrap around. Will that be something
acceptable?
Thanks again,
Kugan
On 08/09/14 19:48, Richard Biener wrote:
On Sun, Sep 7, 2014 at 11:50 AM, Kugan
kugan.vivekanandara...@linaro.org wrote:
On 05/09/14 19:50, Richard Biener wrote:
Well - the best way would be to expose the target specifics to GIMPLE
at some point in the optimization pipeline. My guess
?
Thanks,
Kugan
gcc/ChangeLog:
2014-09-23 Kugan Vivekanandarajah kug...@linaro.org
* config/aarch64/aarch64.h (EPILOGUE_USES): Return true only after
epilogue_completed is true.
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index db950da..b3e4585 100644
I'd like to ping this patch 1 of 2 that removes redundant zero/sign
extension using value range information.
Bootstrapped and no new regression for x86_64-unknown-linux-gnu and
arm-none-linux-gnueabi.
Thanks you for your time.
Kugan
n 14/08/13 16:49, Kugan wrote:
Hi Richard,
Here
I'd like to ping this patch 2 of 2 that removes redundant zero/sign
extension using value range information.
Bootstrapped and no new regression for x86_64-unknown-linux-gnu and
arm-none-linux-gnueabi.
Thanks you for your time.
Kugan
On 14/08/13 16:59, Kugan wrote:
Hi Eric,
Thanks
Thanks Richard for reviewing.
On 02/09/13 22:15, Richard Biener wrote:
On Wed, Jul 3, 2013 at 2:25 PM, Kugan kugan.vivekanandara...@linaro.org wrote:
On 17/06/13 18:33, Richard Biener wrote:
On Mon, 17 Jun 2013, Kugan wrote:
+/* Extract the value range of assigned exprassion
On 06/09/13 16:16, Richard Biener wrote:
On 9/3/13 2:15 PM, Kugan wrote:
Thanks Richard for reviewing.
On 02/09/13 22:15, Richard Biener wrote:
On Wed, Jul 3, 2013 at 2:25 PM, Kugan
kugan.vivekanandara...@linaro.org wrote:
On 17/06/13 18:33, Richard Biener wrote:
On Mon, 17 Jun 2013
On 09/09/13 19:01, Richard Biener wrote:
On Mon, Sep 9, 2013 at 1:09 AM, Kugan kugan.vivekanandara...@linaro.org wrote:
On 06/09/13 16:16, Richard Biener wrote:
On 9/3/13 2:15 PM, Kugan wrote:
Thanks Richard for reviewing.
On 02/09/13 22:15, Richard Biener wrote:
On Wed, Jul 3, 2013
On 10/09/13 22:47, Richard Biener wrote:
On Tue, 10 Sep 2013, Kugan wrote:
On 09/09/13 19:01, Richard Biener wrote:
On Mon, Sep 9, 2013 at 1:09 AM, Kugan kugan.vivekanandara...@linaro.org
wrote:
On 06/09/13 16:16, Richard Biener wrote:
On 9/3/13 2:15 PM, Kugan wrote:
Thanks Richard
.
Is this Ok,
Thanks,
Kugan
+2013-09-12 Kugan Vivekanandarajah kug...@linaro.org
+
+ * cfgexpand.c (maybe_dump_rtl_for_gimple_stmt) : Add range to dump.
+ * gimple-pretty-print.c (print_double_int) : New function.
+ * gimple-pretty-print.c (dump_gimple_phi) : Dump range info
Hi,
Updated the patch to the latest changes in trunk that splits tree.h. I
also noticed an error in printing double_int and fixed it.
Is this OK?
Thanks,
Kugan
+2013-09-12 Kugan Vivekanandarajah kug...@linaro.org
+
+ * cfgexpand.c (maybe_dump_rtl_for_gimple_stmt) : Add range
Thanks Richard for the review.
On 16/09/13 23:43, Richard Biener wrote:
On Mon, 16 Sep 2013, Kugan wrote:
Hi,
Updated the patch to the latest changes in trunk that splits tree.h. I also
noticed an error in printing double_int and fixed it.
Is this OK?
print_gimple_stmt (dump_file
Thanks Richard for the review.
On 18/09/13 18:55, Richard Biener wrote:
On Wed, 18 Sep 2013, Kugan wrote:
Thanks Richard for the review.
On 16/09/13 23:43, Richard Biener wrote:
On Mon, 16 Sep 2013, Kugan wrote:
[Snip]
+2013-09-17 Kugan Vivekanandarajah kug...@linaro.org
On 24/09/13 19:23, Richard Biener wrote:
On Mon, Sep 23, 2013 at 10:34 PM, Eric Botcazou ebotca...@adacore.com wrote:
I have committed it for you (rev 202831), with a few modifications
(ChangeLog formatting, typos).
Here is what I have committed:
2013-09-23 Kugan Vivekanandarajah kug
Hi,
I am attaching a patch that reverts Split shift di patterns (r197527) as
it introduced PR58578. I am also attaching a patch to add a testcase
based on this failiures.
No regression on qemu for arm-none-eabi and new testcase now passes.
Is this OK?
Thanks,
Kugan
diff --git a/gcc/ChangeLog b
Ping~
Thanks,
Kugan
+2013-09-25 Kugan Vivekanandarajah kug...@linaro.org
+
+ * dojump.c (do_compare_and_jump): Generate rtl without
+ zero/sign extension if redundant.
+ * cfgexpand.c (expand_gimple_stmt_1): Likewise.
+ * gimple.c
Hi Eric,
Can you please help to review this patch?
http://gcc.gnu.org/ml/gcc-patches/2013-10/msg00452.html
Thanks,
Kugan
+2013-09-25 Kugan Vivekanandarajah kug...@linaro.org
+
+ * dojump.c (do_compare_and_jump): Generate rtl without
+ zero/sign extension if redundant
Thanks Richard for the review.
On 15/10/13 23:55, Richard Biener wrote:
On Tue, 15 Oct 2013, Kugan wrote:
Hi Eric,
Can you please help to review this patch?
http://gcc.gnu.org/ml/gcc-patches/2013-10/msg00452.html
I think that gimple_assign_is_zero_sign_ext_redundant and its
description
and
thus clearly you cannot drop the (zext:SI (subreg:QI parts.
The same applies to signed types if you do not want to rely
on signed overflow being undefined of course.
Thanks for the explanation. I now get it and I will rework the patch.
Thanks,
Kugan
,
Kugan
2013-10-23 Kugan Vivekanandarajah kug...@linaro.org
* gcc.target/arm/neon-vcond-ltgt.c: Scan for vbsl or vbit or vbif.
* gcc.target/arm/neon-vcond-unordered.c: Scan for vbsl or vbit or vbif.
diff --git a/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c
b/gcc/testsuite
can also find the logs here in
http://cbuild.validation.linaro.org/build/gcc-linaro-4.8-2013.10/logs/armv7l-precise-cbuild461-calxeda02_21_00_precise_armel-armv5r2/
I changed neon-vcond-gt.c too.
Thanks,
Kugan
2013-10-23 Kugan Vivekanandarajah kug...@linaro.org
* gcc.target/arm/neon
On 25/10/13 19:04, Kyrill Tkachov wrote:
On 24/10/13 20:03, Kugan wrote:
Hi Kyrill,
It happens for armv5te arm-none-linux-gnueabi. --with-mode=arm
--with-arch=armv5te --with-float=soft
Ah ok, I can reproduce it now. So, while I agree that we add a scan for
vbit and vbif
better for processor without hw divide instruction.
On a chromebook, when K is large (close to 64) this performs on an
average ~10% faster. When K is small (8 to 24), it performs about ~100%
faster on an average.
Regression tested on arm-none-linux-gnueabi with no issues.
OK?
Thanks,
Kugan
Hi All,
This RFC patch series implements a simple align divisor shift dividend
method.
Regression tested on arm-none-linux-gnueabi with no issues.
OK?
Thanks,
Kugan
+2013-11-22 Kugan Vivekanandarajah kug...@linaro.org
+
+ * libgcc/libgcc2.c (__udivmoddi4): Define new implementation
Hi All,
This RFC patch enables new divide algorithm for ARMV7-A
Regression tested on arm-none-linux-gnueabi with no issues.
OK?
Thanks,
Kugan
+2013-11-22 Kugan Vivekanandarajah kug...@linaro.org
+
+ * libgcc/config/arm/pbapi-lib.h (HAVE_NO_HW_DIVIDE): Define
On 24/11/13 02:14, Ian Lance Taylor wrote:
Kugan kugan.vivekanandara...@linaro.org writes:
This RFC patch series implements a simple align divisor shift dividend
method.
Regression tested on arm-none-linux-gnueabi with no issues.
OK?
Thanks,
Kugan
+2013-11-22 Kugan Vivekanandarajah
On 27/11/13 02:07, Richard Earnshaw wrote:
On 23/11/13 01:54, Kugan wrote:
[snip]
+2013-11-22 Kugan Vivekanandarajah kug...@linaro.org
+
+* libgcc/config/arm/pbapi-lib.h (HAVE_NO_HW_DIVIDE): Define for
It's bpabi-lib.h
Thanks for the review.
+__ARM_ARCH_7_A__
ping
Thanks,
Kugan
On 27/11/13 15:30, Kugan wrote:
On 27/11/13 02:07, Richard Earnshaw wrote:
On 23/11/13 01:54, Kugan wrote:
[snip]
+2013-11-22 Kugan Vivekanandarajah kug...@linaro.org
+
+ * libgcc/config/arm/pbapi-lib.h (HAVE_NO_HW_DIVIDE): Define for
It's bpabi-lib.h
Thanks
the performance than without the patch.
Is this patch ok for trunk?
Thanks,
Kugan
.
This change improve the geomean of spec2k int benchmark with ref by
about ~3.5% on an arm chromebook.
Tested on X86_64 and ARM.
I would like review comments on this.
Thanks,
Kugan
2013-05-09 Kugan Vivekanandarajah kug...@linaro.org
* gcc/gimple.h (gimple_is_exp_fit_lhs
On 14/05/13 00:24, Chung-Lin Tang wrote:
On 13/5/13 11:15 AM, Kugan wrote:
Hi,
Ping this patch by Chung-Lin.
http://gcc.gnu.org/ml/gcc-patches/2011-05/msg01179.html
This patch allows lr registers to be used in leaf functions for ARM.
There were some concerns about performance regression
On 14/05/13 19:18, Ramana Radhakrishnan wrote:
On 05/13/13 04:15, Kugan wrote:
Hi,
Ping this patch by Chung-Lin.
http://gcc.gnu.org/ml/gcc-patches/2011-05/msg01179.html
This patch allows lr registers to be used in leaf functions for ARM.
There were some concerns about performance regression
On 13/05/13 17:47, Richard Biener wrote:
On Mon, May 13, 2013 at 5:45 AM, Kugan
kugan.vivekanandara...@linaro.org wrote:
Hi,
This patch removes some of the redundant sign/zero
extensions using value ranges informations generated by VRP.
When GIMPLE_ASSIGN stmts with LHS type smaller than word
.html and addresses
the review comments of Richard Biener.
Tested on X86_64 and ARM.
I would like review comments on this.
Thanks,
Kugan
+2013-06-03 Kugan Vivekanandarajah kug...@linaro.org
+
+ * gcc/gcc/tree-flow.h: Declared structure range_info_def and function
+ definition
with expansion improve the geomean of spec2k int
benchmark with ref by about ~3.5% on an arm chromebook.
Tested on X86_64 and ARM.
I would like review comments on this.
Thanks,
Kugan
+2013-06-03 Kugan Vivekanandarajah kug...@linaro.org
+
+ * gcc/dojump.c (do_compare_and_jump): generates
== Progress ==
* VRP based zero/sign extension
- Tested and posted the latest patch
* Better end of loop counter optimisation
- Tree level optimization are optimized in mainline
- Christophe noted a slight change in asm generated from earlier version
- tracked down the patch causing this
Apologies for sending again. Corrected wrong dates in subject now.
On 03/06/13 12:19, Kugan wrote:
== Progress ==
* VRP based zero/sign extension
- Tested and posted the latest patch
* Better end of loop counter optimisation
- Tree level optimization are optimized in mainline
Can you please help to review this patch? Richard reviewed the original
patch and asked it to be split into two parts. Also, he wanted a review
from RTL maintainer for the RTL changes.
Thanks,
Kugan
On 03/06/13 11:43, Kugan wrote:
Hi,
This patch adds value range information to tree SSA_NAME
Can you please help to review this patch? Richard reviewed the original
patch and asked it to be split into two parts. Also, he wanted a review
from RTL maintainers for the RTL changes.
Thanks,
Kugan
On 03/06/13 11:46, Kugan wrote:
Hi,
This patch removes some of the redundant sign/zero
Hi Eric,
Can you please help to review the general idea and this patch for zero
sign extension elimination with VRP?
Thanks,
Kugan
On 17/06/13 11:01, Kugan wrote:
Can you please help to review this patch? Richard reviewed the original
patch and asked it to be split into two parts. Also
On 17/06/13 18:33, Richard Biener wrote:
On Mon, 17 Jun 2013, Kugan wrote:
+/* Extract the value range of assigned exprassion for GIMPLE_ASSIGN stmt.
+ If the extracted value range is valid, return true else return
+ false. */
+static bool
+extract_exp_value_range (gimple stmt
Hi Richard,
Here is an attempt to address your earlier review comments. Bootstrapped
and there is no new regression for X86_64 and arm. Thank you very much
for your time.
Thanks,
Kugan
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,25 @@
+2013-08-14 Kugan Vivekanandarajah kug
and zero_extend; instead we can generate the
following RTl.
(set (reg:SI 110)
(reg:SI 117)))
Same could be done for other assign statements.
The idea looks interesting. Some remarks:
+2013-06-03 Kugan Vivekanandarajah kug...@linaro.org
+
+ * gcc/dojump.c (do_compare_and_jump
and prompts upgradation. Is
this Ok?
Thanks,
Kugan
+2013-12-05 Kugan Vivekanandarajah kug...@linaro.org
+ * configure.ac: Add checks for aarch64 assembler -mabi support.
+ * configure: Regenerate.
+
diff --git a/gcc/configure b/gcc/configure
index fdf0cd0..17b6e85 100755
--- a/gcc
the patch.
I have attempted to implement what Richard suggested. If you think this
is what you want, I will go ahead and implement the missing gimple
binary statements.
Thanks again.
Kugan
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index 98983f4..60ce54b 100644
--- a/gcc/cfgexpand.c
+++ b/gcc
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