This is the second version of the patch - previous discussion at:
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636671.html
This patch adds the testcase from PR110415 and fixes the bug.
The problem is that in a couple of places in trans_class_assignment in
trans-expr.cc, we need to
This patch adds the testcase from PR110415 and fixes the bug.
The problem is that in a couple of places in trans_class_assignment in
trans-expr.cc, we need to get the run-time size of the polymorphic
object from the vtbl, but we are currently getting that vtbl from the
lhs of the assignment
This patch gives GCC to use the accumulator VGPR registers on CDNA1 and
later architectures. The backend does not yet attempt to make use of the
matrix acceleration instructions, but the new registers are still useful
as fast space for register spills. And they can now be used in inline
I have updated this patch to incorporate the feedback from Andrew
Stubbs. Tested on CDNA2 GFX90a.
gcc/ChangeLog:
* config/gcn/gcn-protos.h (gcn_expand_dpp_swap_pairs_insn)
(gcn_expand_dpp_distribute_even_insn)
(gcn_expand_dpp_distribute_odd_insn): Declare.
*
This patch introduces instruction patterns for complex number operations
in the GCN machine description. These patterns are cmul, cmul_conj,
vec_addsub, vec_fmaddsub, vec_fmsubadd, cadd90, cadd270, cmla and cmls
(cmla_conj and cmls_conj were not found to be favorable to implement).
As a side
I have committed this patch to openacc-gcc-8-branch. When invoking gcc
to compile fortran code, fortran.exp is currently adding the options
-lgfortran -foffload=-lgfortran to the gcc command line. libgfortran
statically links to libquadmath and the gfortran driver invokes the
linker with
Sorry for the slow response on this, I was on vacation last week.
On 03/12/2018 21:48, Jakub Jelinek wrote:
I'd give the maintainers the last week to act if they don't want this
to happen and if nothing happens, commit it. PR81084 lists all the reasons
why it should be removed when it is
On 06/02/2018 17:19, Joseph Myers wrote:
On Tue, 6 Feb 2018, Andrew Jenner wrote:
Okay to commit to trunk?
As you're powerpcspe maintainer I'm not sure what you're asking for
approval for. Are you asking rs6000 port maintainers to approve the
removal of the documentation for options
I have committed this patch to suppress some more irrelevant options
from the output of "gcc --target-help" for the powerpcspe backend.
I have tested this by rebuilding GCC and checking the output of "gcc
--target-help".
2018-02-02 Andrew Jenner <and...@codesourcery
On 02/02/2018 21:29, Joseph Myers wrote:
On Fri, 2 Feb 2018, Andrew Jenner wrote:
This patch adds a section to invoke.texi for the new PowerPC SPE backend,
mostly copied from the PowerPC backend but with irrelevant options removed.
I think a lot of the remaining options are also irrelevant
This patch adds a section to invoke.texi for the new PowerPC SPE
backend, mostly copied from the PowerPC backend but with irrelevant
options removed.
The patch also removes documentation of the SPE-specific options -mspe,
-mno-spe and -mfloat-gprs from the PowerPC backend (these options have
the output of "gcc
--target-help". I will be doing some proper testing of the backend soon.
A documentation patch will follow in a separate mail.
2018-02-02 Andrew Jenner <and...@codesourcery.com>
* config/powerpcspe/powerpcspe.opt: Add Undocumented to
Hi Tom,
On 07/11/2017 09:07, Tom de Vries wrote:
On 11/07/2017 09:55 AM, Tom de Vries wrote:
Hi,
this patch removes a semicolon after "do {} while (0)" in
SUBTARGET_OVERRIDE_OPTIONS (no ChangeLog yet).
Can you build & test this patch (or approve as trivial)?
Hi,
Can you build & test
to --enable-e500-double.
GIven this hits the powerpcspe port, I'd like Andrew Jenner to chime in
as the powerpcspe maintainer. I've added him on CC.
This change is fine with me too. Thanks!
Andrew
I needed to apply the attached patch for ia16, so that
__LIBGCC_JCR_SECTION_NAME__ does not get defined unless
TARGET_USE_JCR_SECTION is.
2017-04-01 Andrew Jenner <and...@codesourcery.com>
* c-family/g-cppbuiltin.c (c_cpp_builtins): guard
__LIBGCC_JCR_SECTION_NAME__ defi
In the course of working with the ia16 port, I found a case of subreg
shape (I think it was a 32-bit value in one 16-bit register and two
8-bit registers) which is not currently supported by subreg_get_info but
which easily could be, with the attached change.
2017-04-01 Andrew Jenner
In the course of working with ia16, I found a case where the
sorted_allocnos array in ira-color.c requires more than ira_allocnos_num
entries. The following patch allows this array to expand when this happens.
2017-04-01 Andrew Jenner <and...@codesourcery.com>
* ira-c
2017-04-01 Andrew Jenner <and...@codesourcery.com>
* src/c++11/cow-stdexcept.cc (_ITM_RU2): Declare.
(txnal_read_ptr): Allow 16-bit pointers.
* src/c++11/codecvt.cc (read_utf8_code_point): Handle 16-bit int.
Index: libstdc++-v3/src/c++11/cow-stdexc
2017-04-01 Andrew Jenner <and...@codesourcery.com>
Rask Ingemann Lambertsen <r...@sygehus.dk>
* g++.old-deja/g++.warn/flow1.C: Add support for ia16.
* g++.old-deja/g++.robertl/eb76.C: Likewise.
* g++.old-deja/g++.brendan/enum11.C: Likewise.
*
2017-04-01 Andrew Jenner <and...@codesourcery.com>
* testsuite/25_algorithms/copy/streambuf_iterators/wchar_t/4.cc: Add
support for ia16.
* testsuite/25_algorithms/random_shuffle/moveable.cc: Likewise.
* testsuite/25_algorithms/nth_element/58800.cc: Li
This patch updates the documentation.
2017-04-01 Andrew Jenner <and...@codesourcery.com>
Rask Ingemann Lambertsen <r...@sygehus.dk>
* doc/md.texi: Update for new ia16 back end.
* doc/invoke.texi: Likewise.
* doc/contrib.texi: Likewise.
This part is the back end itself.
libgcc/
2017-04-01 Andrew Jenner <and...@codesourcery.com>
Rask Ingemann Lambertsen <r...@sygehus.dk>
* config.host: Add support for ia16.
* ia16/t-ia16: New.
gcc/
2017-04-01 Andrew Jenner <and...@codesourcery.co
To config-patc...@gnu.org: You'll receive only this part of the patch set.
2017-04-01 Andrew Jenner <and...@codesourcery.com>
Rask Ingemann Lambertsen <r...@sygehus.dk>
* config.sub: Add support for 16-bit Intel x86.
Index
About 10 years ago, Rask Ingemann Lambertsen sent a patch series to add
a 16-bit x86 (i.e. 8088, 8086, 80186 and 80286 CPUs) back end. This work
was never committed. Recently I've been doing some work on this back
end, and today we released a Sourcery CodeBench Lite distribution based
on it
Andrew Jenner <and...@codesourcery.com>
gcc/
* ira-int.h (struct ira_allocno): Add forbidden_regs.
(ALLOCNO_FORBIDDEN_REGS): Define.
* ira-color.c (check_hard_reg_p): Use it.
* ira-build.c (ira_create_allocno): Clear it.
* ira-costs.c (process_asm_operands_sew
===
--- ChangeLog (revision 187630)
+++ ChangeLog (working copy)
@@ -1,3 +1,7 @@
+2012-05-17 Andrew Jenner and...@codesourcery.com
+
+ * cse.c (find_comparison_args): Check for cycles of any length.
+
2012-05-17 Manuel López-Ibáñez m...@gcc.gnu.org
* opts.c
Hi Paolo,
On 5/21/2012 10:12 AM, Paolo Bonzini wrote:
That's pretty heavy-weight. Perhaps you can try the usual algorithm of
looking at x-next and x-next-next?
That would only detect cycles of length 1 and 2 though. While that would
cover all the testcases we currently know about, I wanted
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