Re: [PATCH][AArch64][2/2] (Re)Implement vcopy_lane intrinsics

On 7 June 2016 at 17:56, Kyrill Tkachov wrote: > Ok for trunk? > > Thanks, > Kyrill > > 2016-06-07 Kyrylo Tkachov > James Greenhalgh > > * config/aarch64/arm_neon.h (vcopyq_lane_f32,

Re: [Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequence

On 17 May 2016 at 12:02, James Greenhalgh <james.greenha...@arm.com> wrote: > On Tue, May 17, 2016 at 11:32:36AM +0100, Marcus Shawcroft wrote: >> On 17 May 2016 at 10:06, James Greenhalgh <james.greenha...@arm.com> wrote: >> > >> > Hi, >> > >&

Re: [Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequence

On 17 May 2016 at 10:06, James Greenhalgh wrote: > > Hi, > > This is just a simplification, it probably makes life easier for register > allocation in some corner cases and seems the right thing to do. We don't > use the internal version elsewhere, so we're safe to

Re: [Patch AArch64] Delete ASM_OUTPUT_DEF and fallback to default .set directive

On 17 May 2016 at 10:13, James Greenhalgh wrote: > > Hi, > > As in the ARM port [1] , the AArch64 port wants to put out "b = a" to set > an alias. This doesn't cause us any trouble yet, as the AArch64 port doesn't > warn for this construct - but at the same time there is

Re: [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning

On 11 January 2016 at 12:04, James Greenhalgh wrote: > 2015-12-11 James Greenhalgh > > * config/aarch64/aarch64.c (cortexa57_tunings): Remove > AARCH64_EXTRA_TUNE_RECIP_SQRT. > OK /Marcus

Re: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS

On 26 January 2016 at 16:04, James Greenhalgh wrote: > 2016-01-25 James Greenhalgh > > * config/aarch64/aarch64.md > (arch64_sqrdmlh_lane): Fix register > constraints for operand 3. > (aarch64_sqrdmlh_laneq):

Re: [Patch AArch64] GCC 6 regression in vector performance. - Fix vector initialization to happen with lane load instructions.

On 20 January 2016 at 15:22, James Greenhalgh wrote: > gcc/ > > 2016-01-20 James Greenhalgh > Ramana Radhakrishnan > > * config/aarch64/aarch64.c (aarch64_expand_vector_init): Refactor, >

Re: [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-sqrt

On 11 January 2016 at 11:53, James Greenhalgh wrote: > > --- > 2015-12-10 James Greenhalgh > > * config/aarch64/aarch64.c (use_rsqrt_p): Always use software > reciprocal sqrt for -mlow-precision-recip-sqrt. > OK /Marcus

Re: Backport: [Patch AArch64] Reinstate CANNOT_CHANGE_MODE_CLASS to fix pr67609

On 18 December 2015 at 12:13, James Greenhalgh wrote: > Looking back at the patch just before I hit commit, the 4.9 backport was > a little different (as we still have a CANNOT_CHANGE_MODE_CLASS there). > We can drop the aarch64-protos.h and aarch64.h changes, and we

Re: [AARCH64][ACLE] Implement __ARM_FP_FENV_ROUNDING in aarch64 backend.

On 11 January 2016 at 08:12, Bilyan Borisov wrote: > 2015-XX-XX Bilyan Borisov > > * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): New > macro > definition. > > gcc/testsuite/ > > 2015-XX-XX Bilyan Borisov

Re: [AARCH64][ACLE] Implement __ARM_FP_FENV_ROUNDING in aarch64 backend.

On 11 January 2016 at 10:46, Alan Lawrence wrote: > However, the test doesn't really look at whether we're using glibc vs > musl/bionic/uclibc, only at whether we are targeting -linux-gnu or > -none-elf. Fair point, the test case is not aligned with the

Re: [AArch64] Simplify TLS pattern by hardcoding relocation modifiers into pattern

On 10 September 2015 at 12:28, Jiong Wang wrote: > > TLS instruction sequences are always with fixed format, there is no need > to use operand modifier, we can hardcode the relocation modifiers into > instruction pattern, all those redundant checks in aarch64_print_operand >

Re: [Patch AArch64] Reinstate CANNOT_CHANGE_MODE_CLASS to fix pr67609

On 14 December 2015 at 11:01, James Greenhalgh <james.greenha...@arm.com> wrote: > On Wed, Dec 09, 2015 at 01:13:20PM +0000, Marcus Shawcroft wrote: >> On 27 November 2015 at 13:01, James Greenhalgh <james.greenha...@arm.com> >> wrote: >> >> > 20

Re: [Patch AArch64] Reinstate CANNOT_CHANGE_MODE_CLASS to fix pr67609

On 27 November 2015 at 13:01, James Greenhalgh wrote: > 2015-11-27 James Greenhalgh > > * config/aarch64/aarch64-protos.h > (aarch64_cannot_change_mode_class): Bring back. > * config/aarch64/aarch64.c >

Re: [AArch64] Emit square root using the Newton series

On 8 December 2015 at 21:35, Evandro Menezes wrote: >Emit square root using the Newton series > >2015-12-03 Evandro Menezes > >gcc/ > * config/aarch64/aarch64-protos.h (aarch64_emit_swsqrt): >Declare new >

Re: [ARM] Fix PR middle-end/65958

On 3 December 2015 at 12:17, Eric Botcazou wrote: >> I can understand this restriction, but... >> >> > + /* See the same assertion on PROBE_INTERVAL above. */ >> > + gcc_assert ((first % 4096) == 0); >> >> ... why isn't this a test that FIRST is aligned to

Re: [PATCH AArch64]Use aarch64_sync_memory_operand in atomic_store pattern

On 4 December 2015 at 03:34, Bin Cheng wrote: > 2015-12-01 Bin Cheng > > * config/aarch64/atomics.md (atomic_store): Use predicate > aarch64_sync_memory_operand. > OK /Marcus

Re: [PATCH][AArch64] Don't allow -mgeneral-regs-only to change the .arch assembler directives

On 04/12/15 14:40, Kyrill Tkachov wrote: Ping. This almost fell through the cracks. https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00055.html Thanks, Kyrill On 01/10/15 14:00, Kyrill Tkachov wrote: Hi all, As part of the SWITCHABLE_TARGET work I inadvertently changed the behaviour of

Re: [AArch64] Add register constraints to add3_pluslong

On 4 December 2015 at 19:42, James Greenhalgh wrote: > > Hi, > > This patch fixes a bug I spotted in the add3_pluslong insn_and_split > pattern. We need to give register constraints, otherwise the register > allocator can do whatever it likes. This manifests as an ICE on

Re: [PATCH 1/5] [AARCH64]: Move #undef into .def files.

On 17 November 2015 at 22:10, Andrew Pinski wrote: > > This moves the #undef from the header files to the .def files like was done > for builtins.def (https://gcc.gnu.org/ml/gcc-patches/2015-11/msg00662.html). > > OK? Bootstrapped and tested on aarch64-linux-gnu with no

Re: [Patch AArch64] Add support for Cortex-A35

On 16 November 2015 at 14:36, James Greenhalgh wrote: > 2015-11-16 James Greenhalgh > > * config/aarch64/aarch64-cores.def (cortex-a35): New. > * config/aarch64/aarch64.c (cortexa35_tunings): New. > *

Re: [PATCH][AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INT

On 9 November 2015 at 11:32, Kyrill Tkachov wrote: > 2015-11-09 Kyrylo Tkachov > > PR target/68129 > * config/aarch64/aarch64.h (TARGET_SUPPORTS_WIDE_INT): Define to 1. > * config/aarch64/aarch64.c (aarch64_print_operand,

Re: [PATCH][AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INT

On 9 November 2015 at 15:45, Kyrill Tkachov <kyrylo.tkac...@arm.com> wrote: > > On 09/11/15 15:34, Marcus Shawcroft wrote: >> >> On 9 November 2015 at 11:32, Kyrill Tkachov <kyrylo.tkac...@arm.com> >> wrote: >> >>> 2015-11-09 Kyrylo Tkachov &l

Re: [PATCH][AArch64][cleanup] Remove uses of CONST_DOUBLE_HIGH, CONST_DOUBLE_LOW

On 9 November 2015 at 11:34, Kyrill Tkachov wrote: > * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): > Remove integer CONST_DOUBLE handling. It should never occur. OK /Marcus

Re: [PATCH][AArch64] Fix insn types

On 20 October 2015 at 17:14, Evandro Menezes wrote: > Kyrill, > > Indeed, the correct log would be: > > The type assigned to some insn definitions was not correct. > > gcc/ > * config/aarch64/aarch64.md > (*movhf_aarch64): Change the type of "mov

Re: [PATCH][AArch64] Replace insn to zero up DF register

On 20 October 2015 at 00:40, Evandro Menezes wrote: > In the existing targets, it seems that it's always faster to zero up a DF > register with "movi %d0, #0" instead of "fmov %d0, xzr". > > This patch modifies the respective pattern. Hi Evandro, This patch changes the

Re: [PATCH][ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check

On 28 October 2015 at 10:07, Kyrill Tkachov wrote: > Hi all, > > This RTL checking error occurs on aarch64 in aarch_accumulator_forwarding > when processing an msubsi insn > with subregs: > (insn 15 14 16 3 (set (reg/v:SI 78 [ i ]) > (minus:SI (subreg:SI (reg/v:DI

Re: [PATCH][ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check

On 29 October 2015 at 13:50, Kyrill Tkachov wrote: >>> Ok for trunk? >> >> rtl.h exposes reg_or_subregno() already doesn't that do what we need here? > > > reg_or_subregno assumes that what it's passed is REG or a SUBREG. > It will ICE on any other rtx. Here I want to

Re: Fwd: PING^3: [PATCH]: New configure options that make the compiler use -fPIE and -pie as default option

On 23 October 2015 at 13:34, H.J. Lu <hjl.to...@gmail.com> wrote: > On Fri, Oct 23, 2015 at 4:54 AM, Marcus Shawcroft > <marcus.shawcr...@gmail.com> wrote: >> Hi, >> >> This patch breaks the distinction between build and host. For example >&

Re: Fwd: PING^3: [PATCH]: New configure options that make the compiler use -fPIE and -pie as default option

Hi, This patch breaks the distinction between build and host. For example consider a configure along these lines: ./configure --host=aarch64-none-linux-gnu --target=aarch64-none-linux-gnu --build=x86_64-pc-linux-gnu Will result in: CXX_FOR_BUILD='g++' CXX='aarch64-none-linux-gnu-g++' the

Re: Fwd: PING^3: [PATCH]: New configure options that make the compiler use -fPIE and -pie as default option

On 23 October 2015 at 13:34, H.J. Lu <hjl.to...@gmail.com> wrote: > On Fri, Oct 23, 2015 at 4:54 AM, Marcus Shawcroft > <marcus.shawcr...@gmail.com> wrote: >> Hi, >> >> This patch breaks the distinction between build and host. For example >&

Re: [PATCH] [AArch64] support -mfentry feature for arm64

On 22 October 2015 at 14:21, Li Bin wrote: > From: Jiangjiji > > * gcc/config/aarch64/aarch64.opt: Add a new option. > * gcc/config/aarch64/aarch64.c: Add some new functions and Macros. > * gcc/config/aarch64/aarch64.h: Modify PROFILE_HOOK and

Re: [Patch AArch64 63304] Fix issue with global state.

On 16 October 2015 at 12:05, Ramana Radhakrishnan wrote: > 2015-10-15 Ramana Radhakrishnan > > PR target/63304 > * config/aarch64/aarch64.c (aarch64_nopcrelative_literal_loads): New. >

Re: [PATCH][AArch64] Enable fusion of AES instructions

On 14 October 2015 at 13:30, Wilco Dijkstra wrote: > Enable instruction fusion of dependent AESE; AESMC and AESD; AESIMC pairs. > This can give up to 2x > speedup on many AArch64 implementations. Also model the crypto instructions > on Cortex-A57 according > to the

Re: [PATCH][AArch64][1/2] Add fmul-by-power-of-2+fcvt optimisation

On 19 October 2015 at 14:57, Kyrill Tkachov wrote: > 2015-10-19 Kyrylo Tkachov > > * config/aarch64/aarch64.md > (*aarch64_fcvt2_mult): New pattern. > * config/aarch64/aarch64-simd.md > (*aarch64_fcvt2_mult): Likewise. > *

Re: [PATCH][AArch64] Add support for 64-bit vector-mode ldp/stp

On 20 October 2015 at 17:26, Kyrill Tkachov <kyrylo.tkac...@arm.com> wrote: > Hi Marcus, > > On 20/10/15 17:05, Marcus Shawcroft wrote: >> >> On 16 October 2015 at 13:58, Kyrill Tkachov <kyrylo.tkac...@arm.com> >> wrote: >>> >>> Hi a

Re: [PATCH][Testsuite] Turn on 64-bit-vector tests for AArch64

On 16 October 2015 at 12:26, Alan Lawrence wrote: > This enables tests bb-slp-11.c and bb-slp-26.c for AArch64. Both of these are > currently passing on little- and big-endian. > > (Tested on aarch64-none-linux-gnu and aarch64_be-none-elf). > > OK for trunk? > >

Re: [PATCH][AArch64] Add support for 64-bit vector-mode ldp/stp

On 16 October 2015 at 13:58, Kyrill Tkachov wrote: > Hi all, > > We already support load/store-pair operations on the D-registers when they > contain an FP value, but the peepholes/sched-fusion machinery that > do all the hard work currently ignore 64-bit vector modes. > >

Re: [PATCH][AArch64][1/2] Add fmul-by-power-of-2+fcvt optimisation

On 20 October 2015 at 17:31, Kyrill Tkachov <kyrylo.tkac...@arm.com> wrote: > > On 20/10/15 17:28, Ramana Radhakrishnan wrote: >> >> On Tue, Oct 20, 2015 at 4:26 PM, Marcus Shawcroft >> <marcus.shawcr...@gmail.com> wrote: >>> >>> On 19 October

Re: [PATCH][AArch64][1/2] Add fmul-by-power-of-2+fcvt optimisation

On 20 October 2015 at 16:47, Kyrill Tkachov wrote: > Here's the patch updated as per your feedback. > > How's this? > > Thanks, > Kyrill > > 2015-10-20 Kyrylo Tkachov > > * config/aarch64/aarch64.md > (*aarch64_fcvt2_mult): New pattern. >

Re: [PATCH][AArch64 Testsuite][Trivial?] Remove divisions-to-produce-NaN from vdiv_f.c

On 20 October 2015 at 13:40, Alan Lawrence wrote: > The test vdiv_f.c #define's NAN to (0.0 / 0.0). This produces extra scalar > fdiv's, which complicate the scan-assembler testing. We can remove these by > using __builtin_nan instead. > > Tested on AArch64 Linux. > >

Re: [PATCH] 2015-10-19 Benedikt Huber <benedikt.hu...@theobroma-systems.com> Philipp Tomsich <philipp.toms...@theobroma-systems.com>

On 4 January 1970 at 00:02, Benedikt Huber wrote: > * config/aarch64/aarch64-builtins.c: Builtins for rsqrt and rsqrtf. > * config/aarch64/aarch64-protos.h: Declare. > * config/aarch64/aarch64-simd.md: Matching expressions for frsqrte

Re: [PATCH] 2015-10-15 Benedikt Huber <benedikt.hu...@theobroma-systems.com> Philipp Tomsich <philipp.toms...@theobroma-systems.com>

Hi, A few more style nits: > + builtin_decls_data bdda[] = { New line before { > +{double_type_node, "__builtin_aarch64_rsqrt_df", > AARCH64_BUILTIN_RSQRT_DF}, Space after { Space before } > +void aarch64_emit_swrsqrt (rtx, rtx); > + > +tree aarch64_builtin_rsqrt (unsigned int fn,

Re: [PATCH] 2015-10-15 Benedikt Huber <benedikt.hu...@theobroma-systems.com> Philipp Tomsich <philipp.toms...@theobroma-systems.com>

On 16 October 2015 at 15:31, Benedikt Huber wrote: > I introduced this in revision 7 due to a request from James Greenhalgh. > https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00963.html > >> Given that this is all so mechanical, I'd have a preference towards >>

Re: [PATCH] 2015-10-15 Benedikt Huber <benedikt.hu...@theobroma-systems.com> Philipp Tomsich <philipp.toms...@theobroma-systems.com>

On 16 October 2015 at 14:59, Benedikt Huber wrote: > + typedef struct > + { > +tree type_node; > +const char *builtin_name; > +int function_code; > + } builtin_decls_data; Please address Oleg's comment. Cheers /Marcus

Re: [RFC VTV] Fix VTV for targets that have section anchors.

On 09/10/15 10:17, Ramana Radhakrishnan wrote: This started as a Friday afternoon project ... It turned out enabling VTV for AArch64 and ARM was a matter of fixing PR67868 which essentially comes from building libvtv with section anchors turned on. The problem was that the flow of control

Re: [PATCH, aarch64]: Remove AARCH64_ROUND_UP and AARCH64_ROUND_DOWN defines

On 12 October 2015 at 12:28, Uros Bizjak wrote: > Remove private definitions and use equivalent global macros instead. > > 2015-10-12 Uros Bizjak > > * config/aarch/aarch64.h (AARCH64_ROUND_UP): Remove. > (AARCH64_ROUND_DOWN): Ditto. > *

Re: C PATCH for c/65345 (file-scope _Atomic expansion with floats)

On 6 October 2015 at 12:29, Ramana Radhakrishnan wrote: > Thanks for the explanation Eric, by that explanation I do not see the need to > adjust for TARGET_EXPR or mark_addressable in the backends. > > Here are the patches that I'm testing - I will apply the

Re: [AArch64] [TLSIE][2/2] Implement TLS IE for tiny model

On 5 October 2015 at 14:19, Jiong Wang wrote: > 2015-10-05 James Greenhalgh >Jiong Wang > > gcc/ > * config/aarch64/aarch64.md (tlsie_tiny_sidi): Replace "" with "w". > How about a test case? /Marcus

Re: [AArch64][TLSGD][2/2] Implement TLS GD traditional for tiny code model

On 27 August 2015 at 10:54, Jiong Wang wrote: > > As described this is the main implementaion patch. > > 2015-08-26 Jiong Wang > > gcc/ > * configure.ac: Add check for binutils global dynamic tiny code model > relocation support. > * configure:

Re: [AArch64][TLSGD][1/2] Remove unncessary define_expand for TLS GD traditional

On 27 August 2015 at 10:52, Jiong Wang wrote: > 2015-08-27 Jiong Wang > > gcc/ > * config/aarch64/aarch64.md (tlsgd_small): Delete this define_expand. > (*tlsgd_small): Rename this define_insn to "tlsgd_small"; OK /Marcus

Re: [Patch AArch64] Use default_elf_asm_named_section instead of special cased hook

On 2 October 2015 at 11:08, Ramana Radhakrishnan wrote: > * config/aarch64/aarch64-elf.h (TARGET_ASM_NAMED_SECTION): Use > default_elf_asm_named_section. > * config/aarch64/aarch64.c (aarch64_elf_asm_named_section): Delete. > --- >

Re: [AArch64/testsuite] Add more TLS local executable testcases

On 22 September 2015 at 17:49, Jiong Wang wrote: > 2015-09-22 Jiong Wang > > gcc/testsuite/ >* gcc.target/aarch64/tlsle12_tiny_1.c: New testcase for tiny model. >* gcc.target/aarch64/tlsle24_tiny_1.c: Likewise. >*

Re: [Patch AArch64] Use default_elf_asm_named_section instead of special cased hook

On 2 October 2015 at 14:01, Ramana Radhakrishnan wrote: >>> #undef TARGET_ASM_NAMED_SECTION >>> -#define TARGET_ASM_NAMED_SECTION aarch64_elf_asm_named_section >>> +#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section >> >> Isn't it sufficient to

Re: [Patch AArch64] Improve SIMD concatenation with zeroes

On 02/10/15 09:12, James Greenhalgh wrote: 2015-10-01 James Greenhalgh * config/aarch64/aarch64-simd.md (*aarch64_combinez): Add alternatives for reads from memory and moves from general-purpose registers. (*aarch64_combinez_be):

Re: [Patch 2/2 ARM/AArch64] Add a new Cortex-A53 scheduling model

On 25/09/15 08:59, James Greenhalgh wrote: Hi, This patch introduces a new scheduling model for Cortex-A53. Bootstrapped and tested on arm-none-linux-gnueabi and aarch64-none-linux-gnu and checked with a variety of popular benchmarking and microbenchmarking suites to show a benefit. OK?

Re: [PATCH][AArch64] Add separate insn sched class for vector LDP & STP

On 29/09/15 00:52, Evandro Menezes wrote: In some micro-architectures the insns to load or store pairs of vector registers are implemented rather differently from those affecting lanes in vector registers. Then, it's important that such insns be described likewise differently in the scheduling

Re: [AArch64] Fix Prefetch ICE

On 28 September 2015 at 06:27, Hurugalawadi, Naveen wrote: > Hi Marcus, > > Thanks for the review and comments. > >>> OK and can you back port to 5 ? > > Please find attached the backported patch on gcc-5-branch. > > Regression tested on AArch64 without any

Re: [AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt

On 28 July 2015 at 14:12, Jiong Wang wrote: > > The instruction sequences for preparing argument for TLS descriptor > runtime resolver and the later function call to resolver can actually be > hoisted out of the loop. > > Currently we can't because we have exposed the hard

Re: [Patch 1/2 AArch64/ARM] Give AArch64 ROR (Immediate) a new type attribute

On 25 September 2015 at 14:19, James Greenhalgh wrote: > 2015-09-25 James Greenhalgh > > * config/arm/types.md (type): Add rotate_imm. > * config/aarch64/aarch64.md (*ror3_insn): Split out the > ROR immediate case. >

Re: [AArch64] Fix Prefetch ICE

On 24 September 2015 at 07:47, Hurugalawadi, Naveen wrote: > Hi, > > Please find attached the patch that fixes an ICE for prefetch. > > The predicate is too lose for the constraints. Hence, the patch tightens > up the predicate to be exactly as constraint

Re: [AArch64] Fix vcvt_high_f64_f32 and vcvt_figh_f32_f64 intrinsics.

On 21 September 2015 at 15:38, James Greenhalgh wrote: > --- > gcc/ > > 2015-09-21 James Greenhalgh > > * config/aarch64/aarch64-simd.md > > (aarch64_float_truncate_hi_v4sf): Rewrite as an expand. >

Re: [AArch64/testsuite] Add more TLS local executable testcases

On 26 August 2015 at 14:58, Jiong Wang wrote: > > This patch cover tlsle tiny model tests, tls size truncation for tiny & > small model included also. > > All testcases pass native test. > > OK for trunk? > > 2015-08-26 Jiong Wang > > gcc/testsuite/ >

Re: [PATCH 14/15][ARM/AArch64 Testsuite]Add test of vcvt{,_high}_i{f32_f16,f16_f32}

On 25 August 2015 at 14:57, Alan Lawrence wrote: > Sorry - wrong version posted. The hunk for add_options_for_arm_neon_fp16 has > moved to the previous patch! This version also fixes some whitespace issues. > > gcc/testsuite/ChangeLog: > > *

Re: [AArch64] Handle const address in aarch64_print_operand

On 8 September 2015 at 16:03, Jiong Wang wrote: > 2015-09-08 Jiong Wang > > gcc/ > * config/aarch64/aarch64.c (aarch64_print_operand): Add "CONST" > support. OK /Marcus

Re: [Aarch64][target/PR 67143][5.2] Backport correct constraints for atomic operations.

On 9 September 2015 at 12:43, Matthew Wahab wrote: > gcc/ > 2015-09-09 Matthew Wahab > > Backport from mainline > 2015-08-14 Matthew Wahab > > PR target/67143 > *

Re: [AArch64] Delete aarch64_symbol_context which is not used

On 8 September 2015 at 16:00, Jiong Wang wrote: > > The concept of aarch64_symbol_context is not used in AArch64, this patch > remove it and all relevant code. > > ok for trunk? > > 2015-09-08 Jiong. Wang > > gcc/ > * config/aarch64/aarch64-protos.h

Re: [PATCH] 2015-09-03 Benedikt Huber <benedikt.hu...@theobroma-systems.com> Philipp Tomsich <philipp.toms...@theobroma-systems.com>

Hi, Thanks for your work on this. There are a bunch of predominantly style nits in line below. My none nit comments on this patch are: This should be left turned off for all cores where we have not seen benchmark numbers to indicate that this optimization is a benefit, we can take patches for

Re: [AArch64] Implement copysign[ds]f3

On 16 September 2015 at 08:40, James Greenhalgh wrote: > > Hi, > > This patch adds expanders for copysigndf3 and copysignsf3 to the AArch64 > backend. These use the BSL/BIT/BIF insn to save us from the default > expansion pattern. > > Bootstrapped on

Re: [RFC AArch64][PR 63304] Handle literal pools for functions 1 MiB in size.

On 27 July 2015 at 15:33, Ramana Radhakrishnan ramana.radhakrish...@foss.arm.com wrote: DATE Ramana Radhakrishnan ramana.radhakrish...@arm.com PR target/63304 * config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Handle nopcrelative_literal_loads.

Re: [PATCH][AARCH64]Fix for branch offsets over 1 MiB

On 25 August 2015 at 14:12, Andre Vieira andre.simoesdiasvie...@arm.com wrote: gcc/ChangeLog: 2015-08-07 Ramana Radhakrishnan ramana.radhakrish...@arm.com Andre Vieira andre.simoesdiasvie...@arm.com * config/aarch64/aarch64.md (*condjump): Handle functions 1 Mib.

Re: [AArch64][TLSLE][1/3] Add the option -mtls-size for AArch64

On 25 August 2015 at 15:15, Jiong Wang jiong.w...@arm.com wrote: 2015-08-25 Jiong Wang jiong.w...@arm.com gcc/ * config/aarch64/aarch64.opt (mtls-size): New entry. * config/aarch64/aarch64.c (initialize_aarch64_tls_size): New function. (aarch64_override_options_internal): Call

Re: [AArch64] [TLSIE][1/2] Rename test source file for reuse

On 19 June 2015 at 10:15, Jiong Wang jiong.w...@arm.com wrote: Rename test source from tlsle.c into tls.c for reuse purpose. tls.c will be used as test source file for all TLS test, we just need to specify different tls options in different testcases. 2015-06-19 Jiong Wang

Re: [AArch64] [TLSIE][2/2] Implement TLS IE for tiny model

optimization. 2015-06-19 Marcus Shawcroft marcus.shawcr...@arm.com Jiong Wang jiong.w...@arm.com gcc/ * config/aarch64/aarch64.md (UNSPEC_GOTTINYTLS): New UNSPEC. (tlsie_tiny_mode): New define_insn. (tlsie_tiny_sidi): Ditto. * config/aarch64/aarch64-protos.h

Re: [AArch64][TLSLE][1/3] Add the option -mtls-size for AArch64

On 19 August 2015 at 15:26, Jiong Wang jiong.w...@arm.com wrote: 2015-08-19 Jiong Wang jiong.w...@arm.com gcc/ * config/aarch64/aarch64.opt (mtls-size): New entry. * config/aarch64/aarch64.c (initialize_aarch64_tls_size): New function. (aarch64_override_options_internal): Call

Re: [AArch64][TLSLE][2/3] Add the option -mtls-size for AArch64

2015-08-19 Jiong Wang jiong.w...@arm.com gcc/ * config/aarch64/aarch64-protos.h (aarch64_symbol_type): Rename SYMBOL_TLSLE to SYMBOL_TLSLE24. * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Likewise (aarch64_expand_mov_immediate): Likewise

Re: [AArch64][TLSLE][3/3] Implement local executable mode for all memory model

2015-08-19 Marcus Shawcroft marcus.shawcr...@arm.com Jiong Wang jiong.w...@arm.com gcc/ * config/aarch64/aarch64.c (initialize_aarch64_tls_size): Set default tls size for tiny, small, large memory model. (aarch64_load_symref_appropriately): Support new symbol types

Re: [AArch64] Break -mcpu tie between the compiler and assembler

On 20 August 2015 at 09:15, James Greenhalgh james.greenha...@arm.com wrote: 2015-08-19 James Greenhalgh james.greenha...@arm.com * common/config/aarch64/aarch64-common.c (AARCH64_CPU_NAME_LENGTH): Delete. (aarch64_option_extension): New. (all_extensions):

Re: [Patch] Add to the libgfortran/newlib bodge to detect ftruncate support in ARM/AArch64/SH

On 20 August 2015 at 09:31, James Greenhalgh james.greenha...@arm.com wrote: Hi, Steve's patch in 2013 [1] to fix the MIPS newlib/libgfortran build causes subtle issues for an ARM/AArch64 newlib/libgfortran build. The problem is that ARM/AArch64 (and SH) define a stub function for

Re: ira.c update_equiv_regs patch causes gcc/testsuite/gcc.target/arm/pr43920-2.c regression

On 18 August 2015 at 10:25, Alex Velenko alex.vele...@arm.com wrote: On 31/07/15 12:04, Alex Velenko wrote: On 29/07/15 23:14, Jeff Law wrote: On 07/28/2015 12:18 PM, Alex Velenko wrote: On 21/04/15 06:27, Jeff Law wrote: On 04/20/2015 01:09 AM, Shiva Chen wrote: Hi, Jeff Thanks for

Re: [Aarch64] Adjust tests to take LSE extension into account.

On 18 August 2015 at 09:51, Matthew Wahab matthew.wa...@foss.arm.com wrote: gcc/testsuite 2015-08-18 Matthew Wahab matthew.wa...@arm.com * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Adjust dg-options to disable LSE extensions. *

Re: [PATCH][AARCH64]Add backend combine_bfi pattern.

On 5 August 2015 at 17:46, Renlin Li renlin...@arm.com wrote: Hi Kyrill, On 30/07/15 17:08, Kyrill Tkachov wrote: Hi Renlin, On 30/07/15 16:50, Renlin Li wrote: Hi all, This insn should match the following similar rtx pattern and remove the redundant zero_extend operation if the width

Re: [PATCH][AARCH64] Make arm_align_max_stack_pwr.c and arm_align_max_pwr.c compile testcase, instead of execution.

On 28 July 2015 at 16:51, Renlin Li renlin...@arm.com wrote: 2015-07-28 Renlin Li renlin...@arm.com * gcc.target/aarch64/arm_align_max_pwr.c: Make it a compile test case, check the assembly. * gcc.target/aarch64/arm_align_max_stack_pwr.c: Likewise. Hi, #include stdio.h

Re: [PATCH][AArch64][8/14] Implement TARGET_OPTION_VALID_ATTRIBUTE_P

On 21 July 2015 at 16:37, James Greenhalgh james.greenha...@arm.com wrote: On Thu, Jul 16, 2015 at 04:20:59PM +0100, Kyrill Tkachov wrote: +static bool +aarch64_process_one_target_attr (char *arg_str, const char* pragma_or_attr) +{ + bool ret; + bool invert = false; + + int len =

Re: [PATCH][AArch64] Fix LINUX_TARGET_LINK_SPEC to be consistent with ARM

On 22 July 2015 at 18:13, Szabolcs Nagy szabolcs.n...@arm.com wrote: Same as https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01387.html but for AArch64. -dynamic-linker is only passed to the linker if !static !shared. -rdynamic handling is changed too to be consistent with arm: only pass

Re: [PATCH][AArch64] elf toolchain does not pass -shared linker option

On 22 July 2015 at 18:22, Szabolcs Nagy szabolcs.n...@arm.com wrote: 2015-07-22 Szabolcs Nagy szabolcs.n...@arm.com * config/aarch64/aarch64-elf-raw.h (LINK_SPEC): Handle -h, -static, -shared, -symbolic, -rdynamic. OK, this should be back ported to 5 and 4.9 aswell. Thanks

Re: [AArch64][1/2] Mark GOT related MEM rtx as const to help RTL loop IV

On 7 July 2015 at 13:33, Jiong Wang jiong.w...@arm.com wrote: 2015-07-06 Jiong Wang jiong.w...@arm.com gcc/ * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Mark mem as READONLY and NOTRAP for PIC symbol. gcc/testsuite/ * gcc.target/aarch64/got_mem_hoist.c: New

Re: [PATCH][AArch64] PR target/66731 Fix fnmul insn with -frounding-math

On 6 July 2015 at 09:20, Szabolcs Nagy szabolcs.n...@arm.com wrote: 2015-07-06 Szabolcs Nagy szabolcs.n...@arm.com * gcc.target/aarch64/fnmul-1.c: New. * gcc.target/aarch64/fnmul-2.c: New. * gcc.target/aarch64/fnmul-3.c: New. * gcc.target/aarch64/fnmul-4.c:

Re: [Patch ARM-AArch64/testsuite Neon intrinsics: vget_lane

On 2 July 2015 at 14:44, Christophe Lyon christophe.l...@linaro.org wrote: Hi, Here is the missing test for ARM/AArch64 AdvSIMD intrinsic: vget_lane. Tested on arm, armeb, aarch64 and aarch64_be targets (using QEMU). The tests all pass, expect on armeb where vgetq_lane_s64 and

Re: [AArch64][TLSLE][2/N] Rename tlsle_small to tlsle

On 20 May 2015 at 12:19, Jiong Wang jiong.w...@arm.com wrote: Similar to the rename from SYMBOL_SMALL_TPREL to SYMBOL_TLSLE, this patch rename the rtl pattern name. ok for trunk? 2015-05-19 Jiong Wang jiong.w...@arm.com gcc/ * config/aarch64/aarch64.md (tlsle_small): Rename to tlsle.

Re: [AArch64][TLSLE][3/N] Add UNSPEC_TLSLE

On 20 May 2015 at 12:21, Jiong Wang jiong.w...@arm.com wrote: Add new unspec name UNSPEC_TLSLE, use it for all tlsle pattern. ok for trunk? 2015-05-19 Jiong Wang jiong.w...@arm.com gcc/ * config/aarch64/aarch64.md (UNSPEC_TLSLE): New enumeration. (tlsle): Use new unspec name.

Re: [Aarch64] Expand +rdma documentation, small changes to march and mcpu text.

On 22 June 2015 at 17:17, Matthew Wahab matthew.wa...@arm.com wrote: Hello, The documentation for the ARMv8.1 +rdma option doesn't mention that enabling it also implies enabling Adv.SIMD. This patch fixes that. The documentation for the -march and -mcpu options are also a little messy,

Re: [AArch64][TLSLE][N/N] Implement local executable mode for all memory model

On 21 May 2015 at 17:49, Jiong Wang jiong.w...@arm.com wrote: 2015-05-14 Jiong Wang jiong.w...@arm.com gcc/ * config/aarch64/aarch64.c (aarch64_print_operand): Support tls_size. * config/aarch64/aarch64.md (tlsle): Choose proper instruction sequences. (tlsle_mode): New

Re: [AArch64][TLSLE][1/N] Rename SYMBOL_SMALL_TPREL to SYMBOL_TLSLE

On 20 May 2015 at 11:56, Jiong Wang jiong.w...@arm.com wrote: 2015-05-19 Marcus Shawcroft marcus.shawcr...@arm.com Jiong Wang jiong.w...@arm.com gcc/ * config/aarch64/aarch64-protos.h (arch64_symbol_type): Rename SYMBOL_SMALL_TPREL to SYMBOL_TLSLE

Re: [AArch64][TLSLE][5/N] Recognize -mtls-size

On 21 May 2015 at 17:44, Jiong Wang jiong.w...@arm.com wrote: This patch add -mtls-size option for AArch64. This option let user to do finer control on code generation for various TLS model on AArch64. For example, for TLS LE, user can specify smaller tls-size, for example 4K which is quite

Re: [Patch AArch64 3/4] De-const-ify struct tune_params

On 23 June 2015 at 09:49, James Greenhalgh james.greenha...@arm.com wrote: Hi, If we want to overwrite parts of this structure, we're going to need it to be more malleable than it is presently. Run through and remove const from each of the members, create a non-const tuning structure we

Re: [AArch64][1/2] Rename SYMBOL_SMALL_GOT to SYMBOL_SMALL_GOT_4G

On 26 June 2015 at 10:23, Jiong Wang jiong.w...@arm.com wrote: OK. Reworked this patch. Removed those redundant memory model check by adding new symbol classification. Patch splitted into two: * [1/2] Rename SYMBOL_SMALL_GOT to SYMBOL_SMALL_GOT_4G * [2/2] Implement -fpic for

Re: [AArch64][2/2] Implement -fpic for -mcmodel=small

On 26 June 2015 at 10:32, Jiong Wang jiong.w...@arm.com wrote: This patch respin https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01804.html. A new symbol classification SYMBOL_SMALL_GOT_28K added to represent symbol which needs go through GOT table and it's under -fpic/-mcmodel-small. the

Re: [Patch AArch64 4/4] Add -moverride tuning command, and wire it up for control of fusion and fma-steering

On 23 June 2015 at 09:49, James Greenhalgh james.greenha...@arm.com wrote: Hi, This final patch adds support for the new command line option -moverride. The purpose of this command line is to allow expert-level users of the compiler, and those comfortable with experimenting with the

Re: [Patch AArch64 1/4] Define candidates for instruction fusion in a .def file

On 23 June 2015 at 09:49, James Greenhalgh james.greenha...@arm.com wrote: Hi, This patch moves the instruction fusion pairs from a set of #defines to an enum which we can generate from a .def file. We'll use that .def file again, and the friendly names it introduces shortly. OK?

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