and a big endian
power9 system using the latest binutils which includes support for power11.
There were no regressions, and the 3 power11 tests added ran on both systems.
Can I check this patch into GCC 15 when it opens up for general patches?
2024-03-18 Michael Meissner
gcc/testsuite
tion.
I have tested this patch with a bootstrap build on a little endian power10
system and a bootstrap build on a big endian power9 system. There were no
regressions. Can I apply this patch when GCC 15 opens up for general patches?
2024-03-18 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*
This patch makes -mtune=power11 use the same tuning decisions as
-mtune=power10.
I have tested this patch on a little endian power10 system and a big endian
power9 system. There were no regressions. Can I check this into GCC 15 when
it is open for general patches?
2024-03-18 Michael Meissner
power9 system. When the GCC 15 tree opens up for general
patches, can I apply this patch?
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Tue, Feb 20, 2024 at 06:35:34PM +0800, Kewen.Lin wrote:
> Hi Mike,
>
> Sorry for late reply (just back from vacation).
>
> on 2024/2/8 03:58, Michael Meissner wrote:
> > On Wed, Feb 07, 2024 at 05:21:10PM +0800, Kewen.Lin wrote:
> >> on 2024/2/6 14:01, Mich
.
Previously the -mblock-ops-vector-pair switch was not set in POWERPC_MASKS.
This means the option was not reset if the cpu was changed via target
attributes or targt pragmas. I added this mask to POWERPC_MASKS since the
option is set via -mcpu=future.
2024-02-14 Michael Meissner
gcc
This patch uses the .machine directive to tell the assembler to use any
possible future instructions.
2024-02-14 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Output .machine
future if -mcpu=future.
---
gcc/config/rs6000/rs6000.cc | 2 ++
1
Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Make
-mtune=future become -mtune=power10.
---
gcc/config/rs6000/rs6000.cc | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc
This patch passes -mfuture to the assembler if the user used -mcpu=future.
2024-02-14 Michael Meissner
gcc/
* config/rs6000/rs6000.h (ASM_CPU_SPEC): If -mcpu=future, pass -mfuture
to the assembler.
---
gcc/config/rs6000/rs6000.h | 1 +
1 file changed, 1 insertion(+)
diff
This patch defines _ARCH_PWR_FUTURE if -mcpu=future was used.
2024-02-14 Michael Meissner
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
---
gcc/config/rs6000/rs6000-c.cc | 2 ++
1 file changed, 2 insertions(+)
diff
This patch prints that -mcpu=future was selected if you use the debugging
switch -mdebug=reg.
2024-02-14 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_opt_masks): Add entry to print out
-mfuture in the isa flags.
---
gcc/config/rs6000/rs6000.cc | 1 +
1 file
-02-14 Michael Meissner
gcc/
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New option
bits for -mcpu=future.
(POWERPC_MASKS): Add -mfuture mask.
(future cpu): Add -mcpu=future.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): New processor
, and
there were no regressions. Even though these patches have been posted for 1.5
years now, I assume they have to wait for GCC 15. But I will immediately want
to back port these to GCC 14.1 after they go into GCC 15.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss
On Mon, Feb 05, 2024 at 11:58:31AM +0800, Kewen.Lin wrote:
> Hi Mike,
I will comment on about 1/2 of the things, and come back with the other
comments.
> on 2024/1/6 07:42, Michael Meissner wrote:
> > This patch is a prelimianry patch to add the full 1,024 bit dense math
> &g
w reg+reg addresses for TDOmode.
> >>> #ifdef TARGET_REGNAMES
> >>> @@ -1250,6 +1255,8 @@ static const char alt_reg_names[][8] =
> >>>"%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", &
uot;
> + "@
> + pmdm %A0,%x1,%x2,%3,%4,%5
> + pm %A0,%x1,%x2,%3,%4,%5
> + pm %A0,%x1,%x2,%3,%4,%5"
>
> and
>
> - define_insn "mma_"
> + define_insn "mma_pm"
>
> (or updating its use in corresponding bif expander field)
Yes I can do that.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Wed, Feb 07, 2024 at 05:21:10PM +0800, Kewen.Lin wrote:
> on 2024/2/6 14:01, Michael Meissner wrote:
> Sorry for the possible confusion here, the "tune_proc" that I referred to is
> the variable in the above else branch:
>
>enum processor_type tune
operand:XO 0 "dmr_operand" "=wD")
> > + (unspec:XO [(const_int 0)]
> > + UNSPECV_MMA_XXSETACCZ))]
> > + "TARGET_DENSE_MATH"
> > + "dmsetdmrz %0"
> > + [(set_attr "type" "mma")])
> > +
> > (define_insn "mma_"
> > - [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
> > - (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
> > - (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
> > + [(set (match_operand:XO 0 "accumulator_operand" "=wD,,")
> > + (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
> > + (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
> > MMA_VV))]
> >"TARGET_MMA"
> >" %A0,%x1,%x2"
> > - [(set_attr "type" "mma")])
> > + [(set_attr "type" "mma")
> > + (set_attr "isa" "dm,not_dm,not_dm")])
>
> Like what's suggested in previous patches, s/not_dm/nodm/
Ok.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Thu, Jan 25, 2024 at 05:28:49PM +0800, Kewen.Lin wrote:
> Hi Mike,
>
> on 2024/1/6 07:38, Michael Meissner wrote:
> > The MMA subsystem added the notion of accumulator registers as an optional
> > feature of ISA 3.1 (power10). In ISA 3.1, these ac
t;float128-hardware", OPTION_MASK_FLOAT128_HW,false, true },
> >{ "fprnd", OPTION_MASK_FPRND, false,
> > true },
> >{ "power10", OPTION_MASK_POWER10,false,
> > true },
526.blender_r4 more stack spills, but 149 LXVPs
One benchmark actually generated fewer stack spills as well as generating
LXVPs.
538.imagick_r 11 fewer stack spills, and 26 LXVPs
Note, these are changes to the static instructions generated. It does not
evaluate
Ping
| Date: Thu, 11 Jan 2024 12:29:23 -0500
| From: Michael Meissner
| Subject: [PATCH, V2] PR target/112886, Add %S to print_operand for vector
pair support.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642727.html
--
Michael Meissner, IBM
PO Box 98, Ayer
Ping
| Date: Fri, 5 Jan 2024 18:42:02 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 6/6] PowerPC: Add support for 1,024 bit DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641966.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA
Ping
| Date: Fri, 5 Jan 2024 18:40:58 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 5/6] PowerPC: Switch to dense math names for all MMA
operations.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641965.html
--
Michael Meissner, IBM
PO Box 98, Ayer
Ping
| Date: Fri, 5 Jan 2024 18:39:55 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 4/6] PowerPC: Make MMA insns support DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641964.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA
Ping
| Date: Fri, 5 Jan 2024 18:38:23 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 3/6] PowerPC: Add support for accumulators in DMR
registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641963.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts
Ping
| Date: Fri, 5 Jan 2024 18:37:17 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 2/6] PowerPC: Make -mcpu=future enable
-mblock-ops-vector-pair.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641962.html
--
Michael Meissner, IBM
PO Box 98, Ayer
Ping
| Date: Fri, 5 Jan 2024 18:35:37 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 1/6] Add -mcpu=future
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641961.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss
ze*number added to a memory address if it is a MEM.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
n\txvadddp %S0,%S1,%S2"
> : "=wa" (p)
> : "wa" (q), "wa" (r));
> ptr[2] = p;
> }
>
> /* { dg-final { scan-assembler-times {\mxvadddp 10,42,44\M} 1 } } */
> /* { dg-final { scan-assembler-times {\mxvadddp 11,43,45\M} 1 } } */
>
adds %S that acts like %x, except that it adds 1 to the
register number.
I have tested this on power10 and power9 little endian systems and on a power9
big endian system. There were no regressions in the patch. Can I apply it to
the trunk?
It would be nice if I could apply it to the open branches.
On Tue, Jan 09, 2024 at 04:35:22PM -0600, Peter Bergner wrote:
> On 1/5/24 4:18 PM, Michael Meissner wrote:
> > @@ -14504,13 +14504,17 @@ print_operand (FILE *file, rtx x, int code)
> > print_operand (file, x, 0);
> >return;
> >
> > +case 'S':
&
it into the master branch?
2024-01-05 Michael Meissner
gcc/
* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise
on both little and big endian systems. Can I check
it into the master branch?
2024-01-05 Michael Meissner
gcc/
* config/rs6000/mma.md (vvi4i4i8_dm): New int attribute.
(avvi4i4i8_dm): Likewise.
(vvi4i4i2_dm): Likewise.
(avvi4i4i2_dm): Likewise.
(vvi4i4_dm
endian systems. Can I check
it into the master branch?
2024-01-05 Michael Meissner
gcc/
* config/rs6000/mma.md (mma_): New define_expand to handle
mma_ for dense math and non dense math.
(mma_ insn): Restrict to non dense math.
(mma_xxsetaccz): Convert
.
It is possible that the mangling for DMRs and the GDB register numbers may
change in the future.
2024-01-05 Michael Meissner
gcc/
* config/rs6000/constraints.md (wD constraint): New constraint.
* config/rs6000/mma.md (UNSPEC_DM_ASSEMBLE_ACC): New unspec.
(movxo
and store vector pair instructions for memory options by default. This patch
re-enables generating these instructions if -mcpu=future is used.
The patches have been tested on both little and big endian systems. Can I check
it into the master branch?
2024-01-05 Michael Meissner
gcc
ill be set for power10.
The patches have been tested on both little and big endian systems. Can I check
it into the master branch?
2024-01-05 Michael Meissner
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
__ARCH_PWR_FUTURE__ if -mcpu=future.
, these are preliminary patches for a potential future machine. Things
will likely change in terms of implementation and usage over time.
Originally these patches were submitted in November 2022:
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605581.html
--
Michael Meissner, IBM
PO Box 98, Ayer
is on power10 and power9 little endian systems and on a power9
big endian system. There were no regressions in the patch. Can I apply it to
the trunk?
It would be nice if I could apply it to the open branches. Can I backport it
after a burn-in period?
2024-01-04 Michael Meissner
gcc/
P
:OO [
(subreg:V16QI (reg:V2DF 117 [ _6 ]) 0)
(subreg:V16QI (reg:V2DF 118 [ _8 ]) 0)
] UNSPEC_VSX_ASSEMBLE)) 2183 {*vsx_assemble_pair}
(expr_list:REG_DEAD (reg:V2DF 118 [ _8 ])
(expr_list:REG_DEAD (reg:V2DF 117 [ _6 ])
(nil))))
Now
On Tue, Nov 28, 2023 at 05:44:43PM +0800, Kewen.Lin wrote:
> on 2023/11/28 15:05, Michael Meissner wrote:
> > I tried using this patch to compare with the vector size attribute patch I
> > posted. I could not build it as a cross compiler on my x86_64 because the
> > assemble
that this optimization will match less often.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Fri, Nov 24, 2023 at 05:31:20PM +0800, Kewen.Lin wrote:
> Hi Ajit,
>
> Don't forget to CC David (CC-ed) :), some comments are inlined below.
>
> on 2023/10/8 03:04, Ajit Agarwal wrote:
> > Hello All:
> >
> > This patch add new pass to replace contiguous addresses vector load lxv
> > with
On Fri, Nov 24, 2023 at 05:41:02PM +0800, Kewen.Lin wrote:
> on 2023/11/20 16:56, Michael Meissner wrote:
> > On Mon, Nov 20, 2023 at 08:24:35AM +0100, Richard Biener wrote:
> >> I wouldn't expose the "fake" larger modes to the vectorizer but rather
> >> adjust
ns as part of another change (rewriting built-ins maybe)
But prefixed and pc-rel cannot be added willy-nilly with -mcpu=power10 due to
conforming with other parts of the system (assembler, linker, ABIs, etc.).
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
r on actual code.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
px?\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltib\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
--
2.41.0
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
nd:VPAIR_INT 0 "vsx_register_operand" "=wa")
+ (not:VPAIR_INT
+(and:VPAIR_INT
+ (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")
+ (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"]
+ "TARGET_MMA &am
" "=wa,wa")
+ (minus:VPAIR_FP
+(mult:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
+(match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32
+ && flag_fp_contract_mode == FP_CONTRACT_FAST"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (fma:VPAIR_FP (match_dup 1)
+ (match_dup 2)
+ (neg:VPAIR_FP
+ (match_dup 3]
+{
+}
+ [(set_attr "length" "8")
+ (set_attr "type" "vecfloat")])
+
+;; Optimize vector pair -((a * b) + c) into -fma (a, b, c)
+(define_insn_and_split "*nfma_fpcontract_4"
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (neg:VPAIR_FP
+(plus:VPAIR_FP
+ (mult:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32
+ && flag_fp_contract_mode == FP_CONTRACT_FAST"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (neg:VPAIR_FP
+(fma:VPAIR_FP (match_dup 1)
+ (match_dup 2)
+ (match_dup 3]
+{
+}
+ [(set_attr "length" "8")])
+
+;; Optimize vector pair -((a * b) - c) into -fma (a, b, -c)
+(define_insn_and_split "*nfms_fpcontract_4"
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (neg:VPAIR_FP
+(minus:VPAIR_FP
+ (mult:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32
+ && flag_fp_contract_mode == FP_CONTRACT_FAST"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (neg:VPAIR_FP
+(fma:VPAIR_FP (match_dup 1)
+ (match_dup 2)
+ (neg:VPAIR_FP
+ (match_dup 3)]
+{
+}
+ [(set_attr "length" "8")
+ (set_attr "type" "vecfloat")])
+
--
2.41.0
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
on both little endian power9 and big
endian power9 systems, and there are no regressions. Can I check these
patches into the master branch?
2023-11-19 Michael Meissner
gcc/
* config/rs6000/constraint.md (eV): New constraint.
* config/rs6000/predicates.md (cons_0_to_31_operand
power9 and big
endian power9 systems, and there are no regressions. Can I check these
patches into the master branch?
2023-11-19 Michael Meissner
gcc/
* config/rs6000/constraint.md (eV): New constraint.
* config/rs6000/predicates.md (cons_0_to_31_operand): New predicate
the floating point arithmetic operations.
The third patch implements the integer operations.
The fourth patch provides new tests to test these features.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
* A big endian power9 server using --with-cpu=power9.
Can I check this patch into the master branch after the preceeding patch is
checked in?
2023-11-09 Michael Meissner
gcc/
* config/rs6000/rs6000-builtins.def (__builtin_vpair_i8*): Add built-in
functions for integer
power10 server using --with-cpu=power10
* A little endian power9 server using --with-cpu=power9
* A big endian power9 server using --with-cpu=power9.
Can I check this patch into the master branch after the preceeding patches have
been checked in?
2023-11-08 Michael Meissner
gcc
the preceeding patches have
been checked in?
2023-11-09 Michael Meissner
gcc/
* config/rs6000/predicates.md (mma_assemble_input_operand): Allow any
16-byte vector, not just V16QImode.
* config/rs6000/rs6000-builtins.def (__builtin_vpair_zero): New vector
pair
--with-cpu=power9
* A big endian power9 server using --with-cpu=power9.
Can I check this patch into the master branch?
2023-11-09 Michael Meissner
gcc/
* config/rs6000/rs6000-builtins.def (__builtin_vpair_f32_*): Add vector
pair built-in functions for float
be done.
I have built and tested these patches on:
* A little endian power10 server using --with-cpu=power10
* A little endian power9 server using --with-cpu=power9
* A big endian power9 server using --with-cpu=power9.
Can I check these patches into the master branch?
--
Michael
-11-09 Michael Meissner
gcc/
* config/rs6000/mma.md (movoo): Add support for -mno-load-vector-pair
and
-mno-store-vector-pair.
* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add support for
-mload-vector-pair and -mstore-vector-pair
I discovered a short coming in the patch I proposed to add
-mno-load-vector-pair and -mno-store-vector-pair tuning options. I will submit
a new patch shortly.
| Date: Fri, 13 Oct 2023 19:41:13 -0400
| From: Michael Meissner
| Subject: [PATCH] Power10: Add options to disable load and store
Ping #2
| Date: Wed, 18 Oct 2023 20:06:20 -0400
| From: Michael Meissner
| Subject: [PATCH 6/6] PowerPC: Add support for 1,024 bit DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633516.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA
Ping #2
| Date: Wed, 18 Oct 2023 20:04:44 -0400
| From: Michael Meissner
| Subject: [PATCH 5/6] PowerPC: Switch to dense math names for all MMA
operations.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633515.html
--
Michael Meissner, IBM
PO Box 98, Ayer
Ping #2
| Date: Wed, 18 Oct 2023 20:01:54 -0400
| From: Michael Meissner
| Subject: [PATCH 3/6] PowerPC: Add support for accumulators in DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633514.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts
Ping #2
| Date: Wed, 18 Oct 2023 20:00:18 -0400
| From: Michael Meissner
| Subject: [PATCH 2/6] PowerPC: Make -mcpu=future enable
-mblock-ops-vector-pair.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633512.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts
Ping #2
| Date: Wed, 18 Oct 2023 19:58:56 -0400
| From: Michael Meissner
| Subject: Re: [PATCH 1/6] PowerPC: Add -mcpu=future option
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633511.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email
Ping #2
| Date: Fri, 13 Oct 2023 19:41:13 -0400
| From: Michael Meissner
| Subject: [PATCH] Power10: Add options to disable load and store vector pair.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632987.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts
Ping patch.
| Date: Wed, 18 Oct 2023 20:06:20 -0400
| From: Michael Meissner
| Subject: [PATCH 6/6] PowerPC: Add support for 1,024 bit DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633516.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA
Ping patch.
| Date: Wed, 18 Oct 2023 20:04:44 -0400
| From: Michael Meissner
| Subject: [PATCH 5/6] PowerPC: Switch to dense math names for all MMA
operations.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633515.html
--
Michael Meissner, IBM
PO Box 98, Ayer
Ping patch.
| Date: Wed, 18 Oct 2023 20:03:02 -0400
| From: Michael Meissner
| Subject: [PATCH 4/6] PowerPC: Make MMA insns support DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633514.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA
Ping patch:
| ate: Wed, 18 Oct 2023 20:01:54 -0400
| From: Michael Meissner
| Subject: [PATCH 3/6] PowerPC: Add support for accumulators in DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633513.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts
Ping patch.
| Date: Wed, 18 Oct 2023 20:00:18 -0400
| From: Michael Meissner
| Subject: [PATCH 2/6] PowerPC: Make -mcpu=future enable
-mblock-ops-vector-pair.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633512.html
--
Michael Meissner, IBM
PO Box 98, Ayer
Ping patch.
| Date: Wed, 18 Oct 2023 19:58:56 -0400
| From: Michael Meissner
| Subject: Re: [PATCH 1/6] PowerPC: Add -mcpu=future option
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633511.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email
Ping patch:
| Date: Fri, 13 Oct 2023 19:41:13 -0400
| From: Michael Meissner
| Subject: [PATCH] Power10: Add options to disable load and store vector pair.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632987.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts
it into the master branch?
2023-10-18 Michael Meissner
gcc/
* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise
on both little and big endian systems. Can I check
it into the master branch?
2023-10-18 Michael Meissner
gcc/
* config/rs6000/mma.md (vvi4i4i8_dm): New int attribute.
(avvi4i4i8_dm): Likewise.
(vvi4i4i2_dm): Likewise.
(avvi4i4i2_dm): Likewise.
(vvi4i4_dm
endian systems. Can I check
it into the master branch?
2023-10-18 Michael Meissner
gcc/
* config/rs6000/mma.md (mma_): New define_expand to handle
mma_ for dense math and non dense math.
(mma_ insn): Restrict to non dense math.
(mma_xxsetaccz): Convert
.
It is possible that the mangling for DMRs and the GDB register numbers may
change in the future.
The patches have been tested on both little and big endian systems. Can I check
it into the master branch?
2023-10-18 Michael Meissner
gcc/
* config/rs6000/constraints.md (wD
and store vector pair instructions for memory options by default. This patch
re-enables generating these instructions if -mcpu=future is used.
The patches have been tested on both little and big endian systems. Can I check
it into the master branch?
2023-10-18 Michael Meissner
gcc
ill be set for power10.
The patches have been tested on both little and big endian systems. Can I check
it into the master branch?
2023-10-18 Michael Meissner
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
__ARCH_PWR_FUTURE__ if -mcpu=future.
:
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605581.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
systems and big endian power9
systems doing the normal bootstrap and test. There were no regressions in any
of the tests, and the new tests passed. Can I check this patch into the master
branch?
2023-10-13 Michael Meissner
gcc/
* config/rs6000/mma.md (movoo): Add support for -mload
r and on a native PowerPC system.
Can I check this into the master branch to fix the problem?
2023-10-12 Michael Meissner
gcc/
PR target/111778
* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Protect
code from shifts that are undefined.
(can_be
PowerPC server systems,
and there were no regressions. Can I check this into the master branch? Since
it is just a clean-up, I don't see the need to back port it, but it is simple
to do the back port if desired.
2023-09-29 Michael Meissner
gcc/
* config/rs6000/rs6000.md (UNSPEC_COPYSIGN
On Thu, Aug 24, 2023 at 09:19:51PM -0500, Peter Bergner wrote:
> On 8/24/23 12:35 PM, Michael Meissner wrote:
> > On Thu, Jul 20, 2023 at 10:05:28AM +0530, jeevitha wrote:
> >> gcc/
> >>PR target/110411
> >>* config/rs6000/rs6000.h (enum rs
gative, but those are a lot of the issues that might come up
as people use it.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Wed, Jul 26, 2023 at 01:54:01PM +0800, Kewen.Lin wrote:
> Hi Mike,
>
> on 2023/7/11 03:59, Michael Meissner wrote:
> > In doing other work, I noticed that there was an insn:
> >
> > vsx_extract_v4sf__load
> >
> > Which did not have an iterator. I
Ping clean-up patch.
| Date: Mon, 10 Jul 2023 15:59:44 -0400
| From: Michael Meissner
| Subject: [PATCH] Fix typo in insn name.
| Message-ID:
As I said in the reply, the only thing this patch does is to rename
vsx_extract_v4sf__load to vsx_extract_v4sf_load since the insn does not
use a mode
Ping patch.
| Date: Mon, 10 Jul 2023 15:51:56 -0400
| From: Michael Meissner
| Subject: [PATCH] Improve 64->128 bit zero extension on PowerPC (PR
target/108958)
| Message-ID:
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
Ping patch:
| Date: Mon, 10 Jul 2023 15:50:47 -0400
| From: Michael Meissner
| Subject: [PATCH] Optimize vec_splats of vec_extract for V2DI/V2DF (PR
target/99293)
| Message-ID:
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
On Mon, Jul 10, 2023 at 03:10:21PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Mon, Jul 10, 2023 at 03:59:44PM -0400, Michael Meissner wrote:
> > In doing other work, I noticed that there was an insn:
> >
> > vsx_extract_v4sf__load
> >
> > Whi
=power9, IEEE 128-bit long double
* Power9, LE, --with-cpu=power9, 64-bit default long double
* Power9, BE, --with-cpu=power9, IBM 128-bit long double
* Power8, BE, --with-cpu=power8, IBM 128-bit long double
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
=power9, IEEE 128-bit long double
* Power9, LE, --with-cpu=power9, 64-bit default long double
* Power9, BE, --with-cpu=power9, IBM 128-bit long double
* Power8, BE, --with-cpu=power8, IBM 128-bit long double
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
* Power8, BE, --with-cpu=power8, IBM 128-bit long double
2023-07-10 Michael Meissner
gcc/
* config/rs6000/vsx.md (vsx_extract_v4sf_load): Rename from
vsx_extract_v4sf__load.
---
gcc/config/rs6000/vsx.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc
which optimizes moving a GPR to a
vector register using the mtvsrdd instruction with RA=0, and using lxvrdx to
load a 64-bit value into the bottom 64-bits of the vector register.
2023-07-10 Michael Meissner
gcc/
PR target/108958
* gcc/config/rs6000.md (zero_extendditi2): New
__builtin_vec_splats (__builtin_vec_extract (v, 0));
}
would generate:
mfvsrld 9,34
mtvsrdd 34,9,9
blr
With this patch, GCC generates:
xxpermdi 34,34,34,3
blr
2023-07-10 Michael Meissner
gcc/
PR target/99293
* gcc/config/rs6000
-p10sfopt.cc:505:30:
warning: zero-length gcc_dump_printf format string [-Wformat-zero-length]
505 | dump_printf (MSG_NOTE, "");
| ^~
I just commented out the dump_printf call.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
em
all this patch in
previous GCC compilers?
2023-06-12 Michael Meissner
gcc/
* config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that
allowed prefixed lwa to be generated.
* config/rs6000/fusion.md: Regenerate.
* config/rs6000/predicates.md (ds_
gen_ld_cmpi_p10 function.
| Message-ID:
Patch #2, implement the fix for PR target/105325:
| Date: Wed, 10 May 2023 11:40:00 -0400
| Subject: [PATCH V5, 2/2] PR target/105325: Fix memory constraints for power10
fusion.
| Message-ID:
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
and 64-bit code generation.
Can I check this into the master branch? Assuming I can check this in, I will
also commit to the active GCC branches after a burn-in period.
2023-05-10 Michael Meissner
gcc/
PR target/105325
* config/rs6000/genfusion.pl (print_ld_cmpi_p10): Use &qu
branch? Assuming I can check this in, I will
also commit to the active GCC branches after a burn-in period.
2023-05-10 Michael Meissner
gcc/
PR target/105325
* config/rs6000/genfusion.pl (mode_to_ldst_char): Delete.
(print_ld_cmpi_p10): New function, split off from
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