RE: [PATCH] MIPS: Add support for -mcrc and -mginv options

Hi, > Since CRC and GINV ASEs have now been committed to binutils, please go > ahead with this change. This is now committed as r261635. Robert

RE: [PATCH] MIPS: Add support for P6600

Hi Matthew, > With one more change to add another comment as below, this is OK to > commit. > > > @@ -18957,7 +19039,10 @@ mips_reorg_process_insns (void) > > sequence and replace it with the delay slot instruction > > then the jump to clear the forbidden slot

RE: [PATCH] MIPS: Add support for P6600

Hi Matthew, As already discussed, the link to the P6600 doesn't appear to be referenced on mips.com but reachable when searching for 'p6600': https://www.mips.com/downloads/p6600-multiprocessing-programmers-guide/ I'm resubmitting the whole patch again with updated ChangeLog. > > > > +/*

RE: [PATCH] MIPS: Update I6400 scheduler

Hi, > > There does seem to be a temporal issue in submission for this as the > > i6400_fpu_minmax reservation refers to fminmax and fclass types that > > do not exist in trunk. Can you drop that reservation please? > > > > Otherwise, OK to commit. > > Reservation dropped. > > Committed as

RE: [PATCH] MIPS: Add i6500 processor as an alias for i6400

Hi, > Looks good, OK to commit. Committed as r261490. Regards, Robert

RE: [PATCH] MIPS: Update I6400 scheduler

Hi Matthew, > There does seem to be a temporal issue in submission for this as the > i6400_fpu_minmax reservation refers to fminmax and fclass types that > do not exist in trunk. Can you drop that reservation please? > > Otherwise, OK to commit. Reservation dropped. Committed as r261489.

[PATCH] MIPS: Add support for P6600

Hi, The below adds support for -march=p6600. It includes a new scheduler plus performance tweaks. gcc/ChangeLog: 2018-06-01 Matthew Fortune Prachi Godbole * config/mips/mips-cpus.def: Define P6600. * config/mips/mips-tables.opt: Regenerate. *

[PATCH] MIPS: Update I6400 scheduler

Hi, Update to i6400 scheduler. Regards, Robert gcc/ChangeLog: 2018-06-01 Prachi Godbole * config/mips/i6400.md (i6400_gpmuldiv): Remove cpu_unit. (i6400_gpmul): Add cpu_unit. (i6400_gpdiv): Likewise. (i6400_msa_add_d): Update reservations.

[PATCH] MIPS: Add i6500 processor as an alias for i6400

Hi, This patch adds i6500 CPU as an alias for i6400. Regards, Robert gcc/ChangeLog: 2018-06-01 Matthew Fortune * config/mips/mips-cpus.def: New MIPS_CPU for i6500. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Mark i6500 as

[PATCH] MIPS: Add support for -mcrc and -mginv options

Hi, This patch adds -mcrc and -mginv options to pass through them to the assembler. Regards, Robert gcc/ChangeLog: 2018-06-01 Matthew Fortune * config/mips/mips.h (ASM_SPEC): Pass through -mcrc, -mno-crc, -mginv and -mno-ginv to the assembler. * config/mips/mips.opt

RE: [PATCH] MIPS MSA: Fix ICE when using out-of-range values to intrinsics

Hi, Committed as r243301. Regards, Robert > > Robert Suchanek <robert.sucha...@imgtec.com> writes: > > The revised patch attached below. > > > > Regards, > > Robert > > > > gcc/ > > * config/mips/mips.c (mips_expand_builtin_insn): Ch

RE: [PATCH] MIPS MSA: Fix ICE when using out-of-range values to intrinsics

Hi, > Robert Suchanek <robert.sucha...@imgtec.com> writes: > > The patch primarily fixes an ICE with out-of-range values to the > > __builtin_msa_insve* intrinsics. > > > > The compiler segfaults in mips_legitimize_const_move () as it tries to > > split

[PATCH] MIPS MSA: Fix ICE when using out-of-range values to intrinsics

Hi, The patch primarily fixes an ICE with out-of-range values to the __builtin_msa_insve* intrinsics. The compiler segfaults in mips_legitimize_const_move () as it tries to split symbol that has NULL_RTX value and gets here because the patterns reject the operand and a new move for the constant

RE: [PATCH 4/4] [MIPS] Add tests for MSA

Hi, > -Original Message- > From: Matthew Fortune > Sent: 19 September 2016 15:46 > To: Robert Suchanek; catherine_mo...@mentor.com > Cc: gcc-patches@gcc.gnu.org > Subject: RE: [PATCH 4/4] [MIPS] Add tests for MSA > > Hi Robert, > > Sorry for the long delay.

RE: [PATCH] Disable -mbranch-likely for -Os when targetting generic architecture

Hi, > > I'm happy to include this. Ok to commit with this change? > > This looks like it got lost at some point. I think this is a reasonable > change for safety. > > Go ahead and commit. > > Thanks, > Matthew Committed as r240965. Regards, Robert

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

Hi Jeff, > > The following patch reverts to the old behaviour. I also removed misleading > > comments and related logic that checks for the cached result. There might > > be > > other procedures with similar inconsistency but here I only modified the > offending ones. > Thanks. Given how much

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

> On 08/23/2016 04:15 PM, Trevor Saunders wrote: > > > > I've certainly been tempted to take a stab at at least replacing the > > expect stuff with something else, it drives me kind of crazy to see how > > much testsuite time is spent running expect. Even if we can't do all of > > it, the vast

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

Hi, > unfortunately this broke make check-c > RUNTESTFLAGS='vect.exp=*no-vfa-vect-dv-2.c > --target_board=unix\{-m32,-m64\}', causing the check if > vect_aligned_arrays to be cached between the -m64 and -m32 variants > which is incorrect at least on my machine if you actually run that test > for

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

Hi, > On May 5, 2016, at 8:14 AM, Robert Suchanek <robert.sucha...@imgtec.com> > wrote: > > > > I'm resending this patch as it has been rebased and updated. I reverted a > change > > to check_effective_target_vect_call_lrint procedure because it does n

RE: [PATCH][MIPS] P5600 scheduler fix

Hi, > > gcc/ > > * config/mips/p5600.md (p5600_fpu_fadd): Remove checking for > > `fabs' and `fneg' type attributes. > > (p5600_fpu_fabs): Add `fmove' to the comment. > > OK. > > Thanks, > Matthew Committed as r237173. Regards, Robert

RE: [PATCH][MIPS] Add -minline-intermix to ignore compression flags when inlining

Hi Sandra, > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > > index 73f1cb6..2f6195e 100644 > > --- a/gcc/doc/invoke.texi > > +++ b/gcc/doc/invoke.texi > > @@ -837,6 +837,7 @@ Objective-C and Objective-C++ Dialects}. > > -mips16 -mno-mips16 -mflip-mips16 @gol > >

RE: [PATCH][MIPS] Add support for code_readable function attribute

Hi Sandra, > > +@item code_readable > > +@cindex @code{code_readable} function attribute, MIPS > > +For MIPS targets that support PC-relative addressing modes, this attribute > > +can be used to control how an object is addressed. The attribute takes > > +a single optional argument: > > The

[PATCH][MIPS] P5600 scheduler fix

Hi, The below is a fix for the P5600 scheduler. Ok to commit? Regards, Robert 2016-05-24 Simon Dardis Prachi Godbole gcc/ * config/mips/p5600.md (p5600_fpu_fadd): Remove checking for `fabs' and `fneg' type

[PATCH][MIPS] Remove "new" MIPS TLS access patterns

Hi, The below finishes the revert of r137670 that was already partially reverted in r137734 as part of PR target/35802. It would appear that the revert was not completed because of a spill failure at the time. As LRA can handle the 'v' constraint just fine and MIPS is going to drop the support

[PATCH][MIPS] Don't split shifts by default for MIPS16.

Hi, The following changes the default behaviour of shift splitting for MIPS16 e.g. the shifts will be split only when used with undocumented -mno-debugd option that is now switched on by default. This appears to enable better optimization in certain cases, and hence, giving slightly better

[PATCH][MIPS] Add support for code_readable function attribute

Hi, The patch adds support for __attribute__ ((code_readable)) with optional argument that accepts `no', `yes' or `pcrel' just like the -mcode-readable= command line switch. If the argument is not specified then the default `yes' is applied. This of course has only effect on targets supporting

[PATCH][MIPS] Add -minline-intermix to ignore compression flags when inlining

Hi, The below allows us to inline functions that have different compression flags for better tuning of performance/code size balance. Ok to commit? Regards, Robert 2016-05-24 Matthew Fortune gcc/ * config/mips/mips.c (mips_can_inline_p): Allow inlining

RE: [PATCH] Disable -mbranch-likely for -Os when targetting generic architecture

Hi Catherine, Apologies for the (very) late reply. It appears that I never replied to the last message. > > gcc/ > > * config/mips/mips-cpus.def: Replace PTF_AVOID_BRANCHLIKELY > > with > > PTF_AVOID_BRANCHLIKELY_ALWAYS for generic architecture and > > with > >

[PATCH][MIPS] Disable madd/msub when -mno-imadd is used with -mdsp

Hi, If -mdsp option is used then adding -mno-imadd has no effect on the code generation. This appears to be slightly inconsistent to the -m[no-]imadd option we have. Any potential problems/comments? Ok to commit? Regards, Robert gcc/ * config/mips/mips.c (mips_option_override): Move

[PATCH][MIPS] Add -mgrow-frame-downwards option

Hi, The patch changes the default behaviour of the direction in which the local frame grows for MIPS16. The code size reduces by about 0.5% in average case for -Os, hence, it is good to turn the option on by default. Ok to apply? Regards, Robert gcc/ 2016-05-20 Matthew Fortune

[PATCH][MIPS] Fix ICE for constant pool data in GP area for MIPS16

nction. (mips_output_move): Copy GP instead of splitting HIGH when accessing constant pool data. gcc/testsuite/ 2016-05-20 Robert Suchanek <robert.sucha...@imgtec.com> * gcc.target/mips/mips16-gp-bug-1.c: New test. --- gcc/config/mips/mips.c

[PATCH][MIPS] Add support for P6600

Hi, The below patch adds support for MIPS P6600 CPU. This patch will go in after the approval of the Binutils patch. Tested with mips-img-linux-gnu. Regards, Robert 2016-05-20 Matthew Fortune Prachi Godbole *

RE: [PATCH][MIPS] Enable LSA/DLSA for MSA

Hi Matthew, > > Ok to commit? > > OK. Done as r236289. > There is a corresponding testsuite change needed for this > as some code quality tests change if LSA is available. This > is the HAS_LSA 'ghost' option in mips.exp. I'm happy to leave > this to be dealt with as part of the overall MSA

RE: [PATCH][MIPS] Correct latency of loads in M5100

> > Ok to commit? > > > * config/mips/m5100.md (m51_int_load): Update the latency to 2. > > OK. Committed - r236288 Robert

[PATCH][MIPS] Correct latency of loads in M5100

Hi, A small patch to correct the latency for M5100. Ok to commit? Regards, Robert 2016-05-13 Matthew Fortune * config/mips/m5100.md (m51_int_load): Update the latency to 2. --- gcc/config/mips/m5100.md | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH][MIPS] Enable LSA/DLSA for MSA

Hi, The below enables LSA/DLSA instructions for -mmsa. Ok to commit? Regards, Robert * config/mips/mips.h (ISA_HAS_LSA): Enable for -mmsa. (ISA_HAS_DLSA): Ditto. --- gcc/config/mips/mips.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

RE: [PATCH 2/4] [MIPS] Add pipeline description for MSA

Hi Matthew, > > gcc/ChangeLog: > > > > * config/mips/i6400.md (i6400_fpu_intadd, i6400_fpu_logic) > > (i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float, i6400_fpu_store) > > (i6400_fpu_long_pipe, i6400_fpu_logic_l, i6400_fpu_float_l) > > (i6400_fpu_mult): New cpu units. > >

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

stsuite updates: > > Robert Suchanek > Sameera Deshpande > Matthew Fortune > Graham Stott > Chao-ying Fu Of course. All patches have or will have the correct contributors in ChangeLog. > > Otherwise, OK to commit! I removed __builtin_msa_[d]lsa from extend.texi as part of the pr

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Matthew, Revised patch attached. Tested with mips-img-linux-gnu and bootstrapped x86_64-unknown-linux-gnu. > > mips_gen_const_int_vector > This should use gen_int_for_mode instead of GEN_INT to avoid the issues that > msa_ldi is > trying to handle. gen_int_mode cannot be used to generate a

RE: [PATCH][MIPS] Reorder function types

Hi Catherine, > > > > Robert Suchanek <robert.sucha...@imgtec.com> writes: > > > gcc/ > > > * config/mips/mips-ftypes.def: Sort to lexicographical order. > > > > The patch is fine. I don't know what we can/should commit at this stage. >

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi, Here is the updated patch for MSA. The patch requires updated MSA tests and preparatory patch that reorders function types. Tested on mips-img-linux-gnu and mips-mti-linux-gnu. Regards, Robert gcc/ChangeLog: * config.gcc: Add MSA header file for mips*-*-* target. *

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

Ping. > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Robert Suchanek > Sent: 10 August 2015 13:15 > To: catherine_mo...@mentor.com; Matthew Fortune > Cc: gcc-patches@gcc.gnu.org > Subject: [PATCH 3/

[PATCH][MIPS] Reorder function types

Hi, The following patch reorders some of the function types to follow lexicographical order. This patch should go in before the MSA patch. Regards, Robert gcc/ * config/mips/mips-ftypes.def: Sort to lexicographical order. --- gcc/config/mips/mips-ftypes.def | 12 ++-- 1 file

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi, Comments inlined. > >diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md > >index 7d1a8ba..cde0196 100644 > >--- a/gcc/config/mips/constraints.md > >+++ b/gcc/config/mips/constraints.md > >@@ -308,6 +308,53 @@ (define_constraint "Yx" > >"@internal" > >

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi, Comments inlined. The updated patch will be sent in another email as this message is already long. > Hi Robert, > > Next batch of comments. This set covers the rest of mips-msa.md. > > >+++ b/gcc/config/mips/mips-msa.md > >+(define_expand "vec_perm" > >+ [(match_operand:MSA 0

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi, Comments inlined. > >+;; The attribute gives half modes for vector modes. > >+(define_mode_attr VHMODE > >+ [(V8HI "V16QI") > >+ (V4SI "V8HI") > >+ (V2DI "V4SI") > >+ (V2DF "V4SF")]) > >+ > >+;; The attribute gives double modes for vector modes. > >+(define_mode_attr VDMODE > >+

RE: [RFC][PATCH] Preferred rename register in regrename pass

Hi Christophe, > > > Hi, > I confirm that this fixes the build errors I was seeing. > Thanks. > Thanks for checking this. I'm still seeing a number of ICEs on the gcc-testresults mailing list across various ports but these are likely to be caused another patch. They are already reported as

RE: [RFC][PATCH] Preferred rename register in regrename pass

Hi, > I guess this is ok to stop the failures for now, but you may want to > move the check to the point where we set terminated_this_insn. Also, as > I pointed out earlier, clearing terminated_this_insn should probably > happen earlier. Here is the updated patch that I'm about to commit once

RE: [RFC][PATCH] Preferred rename register in regrename pass

Hi all, > > Now that 'make check' has had enough time to run, I can see several > > regressions in the configurations where GCC still builds. > > For more details: > > http://people.linaro.org/~christophe.lyon/cross-validation/gcc/trunk/230087/report-build-info.html > > > > This also causes

RE: [RFC][PATCH] Preferred rename register in regrename pass

Hi, > > Bernd, do you think that this check would be sufficient and safe? > > I'm not sure what would be better: check the mode, nregs plus perhaps > > consider tying only if nregs == 1. > > Hmm, but shouldn't the regno still be the same? Or is this a case where > we have a multi-word chain like

RE: [RFC][PATCH] Preferred rename register in regrename pass

Hi Christophe, > Hi, > > Since you committed this (r230087 if I'm correct), I can see that GCC > fails to build > ligfortran for target arm-none-linuxgnueabi --with-cpu=cortex-a9. ... > > Can you have a look? Sorry for the breakage. I see that my assertion is being triggered. I'll investigate

RE: [RFC][PATCH] Preferred rename register in regrename pass

Hi Bernd, Sorry for late reply. The updated patch was bootstrapped on x86_64-unknown-linux-gnu and cross tested on mips-img-linux-gnu using r229786. The results below were generated for CSiBE benchmark and the numbers in columns express bytes in format 'net (gain/loss)' to show the difference

RE: [RFC][PATCH] Preferred rename register in regrename pass

Hi, > On 11/09/2015 02:32 PM, Robert Suchanek wrote: > > The results below were generated for CSiBE benchmark and the numbers in > > columns express bytes in format 'net (gain/loss)' to show the difference > > with and without the patch when -frename-registers swi

RE: [RFC][PATCH] Preferred rename register in regrename pass

Hi Bernd, Thanks for the comments, much appreciated. Comments inlined and a reworked patch attached. > On 09/17/2015 04:38 PM, Robert Suchanek wrote: > > We came across a situation for MIPS64 where moves for sign-extension were > > not converted into a nop because of I

RE: [RFC][PATCH] Preferred rename register in regrename pass

Hi Bernd, > Hi Robert, > > gcc/ > > * regrename.c (create_new_chain): Initialize terminated_dead, > > renamed and tied_chain. > > (find_best_rename_reg): Pick and check register from the tied chain. > > (regrename_do_replace): Mark head as renamed. > > (scan_rtx_reg): Tie

[RFC][PATCH] Preferred rename register in regrename pass

Hi, We came across a situation for MIPS64 where moves for sign-extension were not converted into a nop because of IRA spilled some of the allocnos and assigned different hard register for the output operand in the move. LRA is not fixing this up as most likely the move was not introduced by the

RE: [PATCH] Disable -mbranch-likely for -Os when targetting generic architecture

Hi, > Richard Sandiford <rdsandif...@googlemail.com> writes: > > Robert Suchanek <robert.sucha...@imgtec.com> writes: > > > The patch below disables generation of the branch likely instructions for > > > - > Os > > > but only for generic

[PATCH] [MIPS] Fix wrong instruction in the delay slot

Hi, The attached test case that uses __builtin_unreachable in the default case in a switch statement triggers a situation where a wrong instruction is placed in the delay slot by the eager delay slot filler. The issue should be reproducible with ToT compiler with -mips32r2 -G0 -mno-abicalls

RE: [PATCH][MIPS] Fix register renaming in the interrupt handlers

Hi, gcc/ * config/mips/mips-protos.h (mips_hard_regno_rename_ok): New prototype. * config/mips/mips.c (mips_hard_regno_rename_ok): New function. (mips_hard_regno_scratch_ok): Likewise. (TARGET_HARD_REGNO_SCRATCH_OK): Define macro. * config/mips/mips.h

[PATCH] Disable -mbranch-likely for -Os when targetting generic architecture

Hi, The patch below disables generation of the branch likely instructions for -Os but only for generic architecture. The branch likely may result in some code size reduction but the cost of running the code on R6 core is significant. Disabling this for generic architecture would therefore be

RE: [PATCH][MIPS] Fix register renaming in the interrupt handlers

Hi, You also need to do the same thing for TARGET_HARD_REGNO_SCRATCH_OK, to stop peephole2 from using unsaved registers as scratch registers. I should dig out my patches to clean up this interface. It's just too brittle to have two macros that say what registers can be used after

RE: [PATCH, MIPS] Enable load/store bonding for I6400

Ping. -Original Message- From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On Behalf Of Robert Suchanek Sent: 05 August 2015 09:31 To: catherine_mo...@mentor.com; Matthew Fortune; gcc-patches@gcc.gnu.org Subject: [PATCH, MIPS] Enable load/store bonding

RE: [PATCH, MIPS] Remove W32 and W64 pseudo-processors

Hi, gcc/ * config/mips/mips.c (mips_rtx_cost_data): Remove costs for W32 and W64 pseudo-processors. * config/mips/mips.md (processor): Remove w32 and w64. OK, thanks. Matthew Committed as r226851. Regards, Robert

RE: [PATCH, MIPS] Enable load/store bonding for I6400

Hi, gcc/ * config/mips/mips.h (ENABLE_LD_ST_PAIRS): Enable load/store pairs for I6400. Sorry, I missed this one. OK to commit. Thanks, Matthew Committed as r226860. Regards, Robert

[PATCH][MIPS] Fix register renaming in the interrupt handlers

Hi, It was discovered that with the attached test case compiled with -O2 -funroll-loops, the regrename pass renamed one of the registers ($2) to $8 that was not saved by the prologue. The attached patch fixes it by defining macro HARD_REGNO_RENAME_OK that returns zero iff the current function

RE: [PATCH][MIPS] Scheduler fix for the 74k 24k.

Hi, Simon gcc/ * config/mips/mips.c (mips_store_data_bypass_p): Bring code into line with comments. * config/mips/sb1.md: Update usage of mips_store_data_bypass_p. This patch is OK. Committed on Simon's behalf as r226805. Regards, Robert

[PATCH 2/4] [MIPS] Add pipeline description for MSA

Hi, The patch adds a pipeline description for MSA to I6400 and P5600 schedulers. Regards, Robert gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_intadd, i6400_fpu_logic) (i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float, i6400_fpu_store) (i6400_fpu_long_pipe,

[PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi, This series of patches adds the support for MIPS SIMD Architecture (MSA) and underwent a few updates since the last review to address the comments: https://gcc.gnu.org/ml/gcc-patches/2014-05/msg01777.html The series is split into four parts: 0001 [MIPS] Add support for MIPS SIMD

[PATCH, MIPS] Enable load/store bonding for I6400

Hi, Following up https://gcc.gnu.org/ml/gcc-patches/2015-07/msg01730.html The patch below enables the load-load/store-store bonding for MIPS32/MIPS64 R6. Ok to apply? Regards, Robert gcc/ * config/mips/mips.h (ENABLE_LD_ST_PAIRS): Enable load/store pairs for I6400. ---

[PATCH, MIPS] Remove W32 and W64 pseudo-processors

Hi, Since the I6400 scheduler is committed, W32/W64 pseudo-processors are not needed anymore and can be removed. Ok to commit? Regards, Robert gcc/ * config/mips/mips.c (mips_rtx_cost_data): Remove costs for W32 and W64 pseudo-processors. * config/mips/mips.md

RE: [PATCH, MIPS] I6400 scheduling

Hi, PTF_AVOID_BRANCHLIKELY replaced with 0 in all 3 cases. AFAICS, there is no need to update the option handling code. The branch likely will not be enabled as it is additionally guarded by ISA_HAS_BRANCHLIKELY. OK with those changes. I'll commit the updated patch once the build

RE: [PATCH, MIPS] Add -march=interaptiv

Hi Catherine, gcc/ * config/mips/mips-cpus.def (interaptiv): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map - march=interaptiv to -mips32r2. (BASE_DRIVER_SELF_SPECS): Likewise but map to -mdsp. *

RE: [PATCH, MIPS] Scheduling for M51xx core family

Hi Matthew, gcc/ * config/mips/m5100.md: New file. * config/mips/mips-cpus.def (m5100, m5101): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add costs for m5100. * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map

RE: [PATCH, MIPS] I6400 scheduling

Hi, diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md new file mode 100644 index 000..101a20c --- /dev/null +++ b/gcc/config/mips/i6400.md @@ -0,0 +1,142 @@ +;; DFA-based pipeline description for I6400. +;; +;; Copyright (C) 2007-2015 Free Software Foundation,

[PATCH, MIPS] I6400 scheduling

Hi, This patch adds a pipeline description for the I6400 processor with -mips32r6 and -mips64r6 defaulted to this description. Regtested with mips-img-linux-gnu. mips-tables.opt will be regenerated before committing depending on which patch from the series goes in first. Ok to apply? Regards,

[PATCH, MIPS] Add -march=interaptiv

Hi, As in the title, the attached patch adds -march=interaptiv defined to 24kf2_1, mapped to -mips32r2 and -mdsp. OK to apply? Regards, Robert gcc/ * config/mips/mips-cpus.def (interaptiv): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.h

[PATCH, MIPS] Scheduling for M51xx core family

Hi, Another patch with a pipeline description but for M51xx cores with two new options introduced: -march={m5100,m5101}. The M5101 is essentially the same as M5100 but mapped to -msoft-float. Ok to apply? Regards, Robert 2015-07-16 Prachi Godbole prachi.godb...@imgtec.com gcc/ *

RE: [PATCH, MIPS] Support new interrupt handler options

Hi Catherine, This is now OK to commit. Catherine Committed as r225819. Robert

RE: [PATCH, MIPS] Support interrupt handlers with hard-float

Hi, Hi Matthew/Catherine, The attached patch removes the restriction to compile a TU with an ISR with - mhard-float. Instead of forcing -msoft-float, the coprocessor 1 is disabled in an ISR for -mhard-float. Ok to apply? Yes, this one is OK. Committed as r225818. Regards,

RE: [PATCH, MIPS] Fix restoration of hi/lo in MIPS64R2 interrupt handlers

Hi, OK. I'll change it to interrupt_handler-5.c, add a comment and commit after approval for the new interrupt handler options. I believe this change is independent of the new attributes so feel free to commit it before. I was to going to commit it before but by the time I did that, I

RE: [PATCH, MIPS] Support new interrupt handler options

Hi Catherine, I'm getting build errors with the current TOT and your patch. The first errors that I encounter are: gcc/config/mips/mips.c:1355:1: warning: 'mips_int_mask mips_interrupt_mask(tree)' defined but not used [-Wunused-function] gcc/config/mips/mips.c:1392:1: warning:

RE: [PATCH, MIPS] Fix restoration of hi/lo in MIPS64R2 interrupt handlers

Hi Catherine, Hi Robert, The patch is OK, but will you please name the test something other than the date? OK. I'll change it to interrupt_handler-5.c, add a comment and commit after approval for the new interrupt handler options. Regards, Robert diff --git

[PATCH, MIPS] Support new interrupt handler options

pointer. With this option rdpgpr $sp, $sp will not be generated for an ISR. Tested with mips-img-elf, mips-img-linux-gnu and mips64el-linux-gnu cross compilers. Ok to apply? Regards, Robert 2015-07-07 Matthew Fortune matthew.fort...@imgtec.com Robert Suchanek robert.sucha

[PATCH, MIPS] Support interrupt handlers with hard-float

Hi Matthew/Catherine, The attached patch removes the restriction to compile a TU with an ISR with -mhard-float. Instead of forcing -msoft-float, the coprocessor 1 is disabled in an ISR for -mhard-float. Ok to apply? Regards, Robert gcc/ * config/mips/mips.c

[PATCH, MIPS] Fix restoration of hi/lo in MIPS64R2 interrupt handlers

Hi, The attached patch fixes an ICE (unrecognizable insn) when accumulators are used in interrupt handlers for MIPS64R2. There was just a typo in the function name. Ok to apply? Regards, Robert gcc/ * config/mips/mips.c (mips_emit_save_slot_move): Fix typo. gcc/testsuite/ *

RE: [Patch MIPS] Enable TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook

Hi, Trim the extra trailing newline. OK to commit if you are happy with the comment. Committed as r224549. Regards, Robert

RE: [Patch MIPS] Enable TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook

Hi Matthew, /* LRA will allocate an FPR for an integer mode pseudo instead of spilling to memory if an FPR is present in the allocno class. It is rare that we actually need to place an integer mode value in an FPR so where possible limit the allocation to GR_REGS. This will

RE: [Patch MIPS] Enable TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook

Hi Matthew, + +/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. */ + +static reg_class_t +mips_ira_change_pseudo_allocno_class (int regno, reg_class_t +allocno_class) { + if (FLOAT_MODE_P (PSEUDO_REGNO_MODE (regno)) || allocno_class != ALL_REGS) +return allocno_class;

[Patch MIPS] Enable TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook

Hi, The patch enables the hook for MIPS as a result of the discussion: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65862 Tested on mips-mti-linux-gnu and mips-img-linux-gnu. Ok to apply? Regards, Robert gcc/ChangeLog: * config/mips/mips.c (mips_ira_change_pseudo_allocno_class): New

RE: [PATCH, MIPS]: Fix internal compiler error: in check_bool_attrs, at recog.c:2218 for micromips attribute

gcc/ * config/mips/mips.h (micromips_globals): Declare. OK, thanks. Matthew Committed as r223438. Robert

RE: [PATCH, MIPS]: Fix internal compiler error: in check_bool_attrs, at recog.c:2218 for micromips attribute

Hi, The original patch had a missing declaration of micromips_globals in mips.h that appears to be the cause of segmentation faults when building mips-mti-linux-gnu. I didn't get any failures just before the submission neither on mips-img-linux-gnu nor mips64el-linux-gnu and the test case is

RE: [PATCH, MIPS]: Fix internal compiler error: in check_bool_attrs, at recog.c:2218 for micromips attribute

Hi Matthew, This patch fixes an internal compiler error when micromips/nomicromips attributes are used. The problem here was that the cached boolean attributes for the current target did not agree with the uncached attributes throwing an assertion error. It appears that saving and

[PATCH, MIPS]: Fix internal compiler error: in check_bool_attrs, at recog.c:2218 for micromips attribute

Hi, This patch fixes an internal compiler error when micromips/nomicromips attributes are used. The problem here was that the cached boolean attributes for the current target did not agree with the uncached attributes throwing an assertion error. It appears that saving and restoring the state

RE: [PATCH MIPS RFA] Regression cleanup for nan2008 toolchain

2015-02-02 Robert Suchanek robert.sucha...@imgtec.com * gcc.target/mips/loongson-simd.c: Update comment to clarify the need for mips_nanlegacy target. diff --git a/gcc/testsuite/gcc.target/mips/loongson-simd.c b/gcc/testsuite/gcc.target/mips/loongson-simd.c index

RE: [PATCH MIPS RFA] Regression cleanup for nan2008 toolchain

of things being skipped in cases where the mips.exp options machinery could be updated instead.) True. Clarification added. Ok for trunk? Regards, Robert 2015-02-02 Robert Suchanek robert.sucha...@imgtec.com

RE: [PATCH RFA MIPS] Prohibit vector modes in accumulators

Since Catherine asked for further info then I will leave her to say if she is happy to accept on this basis. I withdraw my request for a testcase. Catherine Committed as r220200. Regards, Robert

RE: [PATCH MIPS RFA] Regression cleanup for nan2008 toolchain

2015-01-26 Robert Suchanek robert.sucha...@imgtec.com gcc/testsuite * lib/target-supports.exp (check_effective_target_mips_nanlegacy): New. * gcc.target/mips/loongson-simd.c: Require legacy NaN support. * gcc.target/mips/mips.exp (mips-dg-options): Imply -mnan=legacy

RE: [PATCH, RFC] LRA subreg handling

Here we do have a hard register, but it isn't valid to form the subreg on that hard register. Reload had to cope with that case too. Since the subreg on the original hard register is invalid, we can't use it to decide whether the intention was to write to only a part of the inner

[PATCH RFC] Running auto-vectorization tests multiple times

Hi, I'm trying to lift the restriction to run auto-vectorization tests more than once and would like to check if I'm going in the right direction. I attached a draft patch. Currently, auto-vectorization tests are enabled by a call to check_vect_support_and_set_flags procedure and if there is

[PATCH MIPS RFA] Regression cleanup for nan2008 toolchain

, Robert 2015-01-26 Robert Suchanek robert.sucha...@imgtec.com gcc/testsuite * lib/target-supports.exp (check_effective_target_mips_nanlegacy): New. * gcc.target/mips/loongson-simd.c: Require legacy NaN support. * gcc.target/mips/mips.exp (mips-dg-options): Imply -mnan=legacy

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