Re: [PATCH][GCC] arm: Optimize arm-mlib.h header inclusion (pr108505).

Ping!! From: Gcc-patches on behalf of Srinath Parvathaneni via Gcc-patches Sent: 27 January 2023 17:44 To: gcc-patches@gcc.gnu.org Cc: nd ; Richard Earnshaw ; Kyrylo Tkachov Subject: [PATCH][GCC] arm: Optimize arm-mlib.h header inclusion (pr108505). Hello

[PATCH][GCC] arm: Optimize arm-mlib.h header inclusion (pr108505).

target and found no regressions. Ok for master? [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-January/610513.html Regards, Srinath. gcc/ChangeLog: 2023-01-27 Srinath Parvathaneni PR target/108505 * config.gcc (tm_mlib_file): Define new variable

[PATCH][GCC] arm: Fix inclusion of arm-mlib.h header more than once (pr108505).

and found no regressions. Ok for master? Regards, Srinath. gcc/ChangeLog: 2023-01-24 Srinath Parvathaneni PR target/108505 * config.gcc (tm_file): Move the variable out of loop. ### Attachment also inlined for ease of reply### diff --git a/gcc

[Committed][GCC] arm: Documentation fix for -mbranch-protection option.

Hello, This patch fixes the documentation for -mbranch-protection command line option. Committed this patch to trunk as obvious fix. Regards, Srinath. gcc/ChangeLog: 2023-01-23 Srinath Parvathaneni * doc/invoke.texi (-mbranch-protection): Update documentation

[PATCH v2][GCC] arm: Add support for new frame unwinding instruction "0xb5".

f "0xb5" instruction is not encountered then CFA will be used as modifier in pointer authentication. [1] https://github.com/ARM-software/abi-aa/releases/download/2022Q3/ehabi32.pdf Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. gcc/C

RE: [PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".

Hi Ramana, > -Original Message- > From: Ramana Radhakrishnan > Sent: Sunday, November 20, 2022 10:48 PM > To: Srinath Parvathaneni > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > ; Kyrylo Tkachov > Subject: Re: [PATCH][GCC] arm: Add support for new frame unwindin

[GCC][PATCH 13/15, v6] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

push{r3, r7, ip, lr} .save {r3, r7, ra_auth_code, lr} ... .cfi_offset 143, -8 ... .cfi_restore 143 ... aut ip, lr, sp bx lr ... Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. 2023-01-18 Srinath

[GCC][PATCH v4] arm: Add pacbti related multilib support for armv8.1-m.main.

used in the multilib matching. Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2023-01-11 Srinath Parvathaneni * config.gcc ($tm_file): Update variable. * config/arm/arm-mlib.h: Create new header file.

[GCC][PATCH 13/15, v5] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

push{r3, r7, ip, lr} .save {r3, r7, ra_auth_code, lr} ... .cfi_offset 143, -8 ... .cfi_restore 143 ... aut ip, lr, sp bx lr ... Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. 2023-01-11 Srinath

[Committed] arm: Add cde feature support for Cortex-M55 CPU.

on arm-none-eabi target and found no regressions. [1] https://developer.arm.com/documentation/101051/0101/?lang=en (version: r1p1). Ok for master? Regards, Srinath. gcc/ChangeLog: 2023-01-13 Srinath Parvathaneni * common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde

RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.

Ping!! - From: Srinath Parvathaneni Sent: Tuesday, December 6, 2022 11:32 AM To: gcc-patches@gcc.gnu.org; Richard Earnshaw Cc: Christophe Lyon Subject: Re: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU. Ping

Re: [GCC][PATCH 13/15, v4] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

Ping!! From: Gcc-patches on behalf of Srinath Parvathaneni via Gcc-patches Sent: 09 November 2022 14:32 To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw ; Kyrylo Tkachov Subject: [GCC][PATCH 13/15, v4] arm: Add support for dwarf debug directives and pseudo

Re: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.

Ping!! From: Srinath Parvathaneni Sent: 31 October 2022 12:38 To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw ; Christophe Lyon Subject: RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU. Hi, > -Original Message- > From: Chri

Re: [GCC][PATCH v2] arm: Add pacbti related multilib support for armv8.1-m.main.

Ping!! From: Gcc-patches on behalf of Srinath Parvathaneni via Gcc-patches Sent: 31 October 2022 15:36 To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [GCC][PATCH v2] arm: Add pacbti related multilib support for armv8.1-m.main. Hi, This patch

RE: [PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".

Hi, > -Original Message- > From: Ramana Radhakrishnan > Sent: Thursday, November 17, 2022 8:27 PM > To: Srinath Parvathaneni > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > ; Kyrylo Tkachov > Subject: Re: [PATCH][GCC] arm: Add support for new frame unwindin

RE: [PATCH][GCC] aarch64: Add support for Cortex-X3 CPU.

Hi, > -Original Message- > From: Kyrylo Tkachov > Sent: Monday, November 14, 2022 2:47 PM > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Sandiford > Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-X3 CPU. > > > > >

[PATCH][GCC] aarch64: Add support for Cortex-X3 CPU.

Hi, This patch adds support for Cortex-X3 CPU. Bootstrapped on aarch64-none-linux-gnu and found no regressions. Ok for GCC master? Regards, Srinath. gcc/ChangeLog: 2022-11-09 Srinath Parvathaneni * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X3 CPU

RE: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.

Hi, > -Original Message- > From: Kyrylo Tkachov > Sent: Friday, November 11, 2022 2:24 PM > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Sandiford > Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU. > > Hi Srinath, &

[PATCH][GCC] aarch64: Add support for Cortex-X1C CPU.

Hi, This patch adds support for Cortex-X1C CPU. Bootstrapped on aarch64-none-linux-gnu and found no regressions. Ok for GCC master? Regards, Srinath. gcc/ChangeLog: 2022-11-09 Srinath Parvathaneni * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X1C CPU

[PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.

Hi, This patch adds support for Cortex-A715 CPU. Bootstrapped on aarch64-none-linux-gnu and found no regressions. Ok for GCC master? Regards, Srinath. gcc/ChangeLog: 2022-11-09 Srinath Parvathaneni * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A715 CPU

[PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".

f "0xb5" instruction is not encountered then CFA will be used as modifier in pointer authentication. [1] https://github.com/ARM-software/abi-aa/releases/download/2022Q3/ehabi32.pdf Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. gcc/C

[PATCH][GCC] arm: Add support for Cortex-X1C CPU.

Hi, This patch adds the -mcpu support for the Arm Cortex-X1C CPU. Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for GCC master? Regards, Srinath. gcc/ChangeLog: 2022-11-09 Srinath Parvathaneni * config/arm/arm-cpus.in

[GCC][PATCH 13/15, v4] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

push{r3, r7, ip, lr} .save {r3, r7, ra_auth_code, lr} ... .cfi_offset 143, -8 ... .cfi_restore 143 ... aut ip, lr, sp bx lr ... Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. gcc/testsuite/ChangeLo

[GCC][PATCH v2] arm: Add pacbti related multilib support for armv8.1-m.main.

one-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-10-28 Srinath Parvathaneni * common/config/arm/arm-common.cc (arm_canon_branch_protection_option): Define new function. * config/arm/arm-cpus.in (armv8.1-m.main): Move dsp op

RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.

Hi, > -Original Message- > From: Christophe Lyon > Sent: Monday, October 17, 2022 2:30 PM > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Earnshaw > Subject: Re: [GCC][PATCH] arm: Add cde feature support for Cortex-M55 > CPU. > > Hi S

[GCC][PATCH] arm: Add cde feature support for Cortex-M55 CPU.

on arm-none-eabi target and found no regressions. [1] https://developer.arm.com/documentation/101051/0101/?lang=en (version: r1p1). Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-10-07 Srinath Parvathaneni * common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde

[GCC 13/15][PATCH v3] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

r0, #0 aut ip, lr, sp bx lr .cfi_endproc ... Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-08-17 Srinath Parvathaneni * config/arm/aout.h (ra_auth_code): Add to enum.

RE: [GCC][PATCH v2] arm: Add support for Arm Cortex-M85 CPU.

-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-08-12 Srinath Parvathaneni * config/arm/arm-cpus.in (cortex-m85): Define new CPU. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * doc/invoke.texi (Arm Options

[PATCH 13/15] arm: Add pacbti related multilib support for armv8.1-m.main.

-mfloat-abi=hard -mthumb $ -march=armv8.1-m.main+dsp+pacbti+fp.dp -mbranch-protection=standard -mfloat-abi=hard -mthumb Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-08-12 Srinath Parvathaneni

[Committed] arm: Document +no options for Cortex-M55 CPU.

floating point instructions) +nofp (disables floating point instructions) Committed as obvious to master. Regards, Srinath. gcc/ChangeLog: 2022-08-12 Srinath Parvathaneni * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55 options. ### Attachment also inlined

[GCC][PATCH] arm: Add support for Arm Cortex-M85 CPU.

-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-08-05 Srinath Parvathaneni * config/arm/arm-cpus.in (cortex-m85): Define new cpu. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * config/arm/t-rmprofile: Re-use

RE: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

Ping!! > -Original Message- > From: Gcc-patches bounces+srinath.parvathaneni=arm@gcc.gnu.org> On Behalf Of Srinath > Parvathaneni via Gcc-patches > Sent: 05 May 2022 12:02 > To: gcc-patches@gcc.gnu.org > Cc: Richard Earnshaw > Subject: [PATCH v2][GCC] ar

[PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

? Regards, Srinath. gcc/ChangeLog: 2022-04-06 Srinath Parvathaneni * config/arm/aout.h (ra_auth_code): Add to enum. * config/arm/arm.cc (emit_multi_reg_push): Add RA_AUTH_CODE register to dwarf frame expression. (arm_emit_multi_reg_pop): Restore RA_AUTH_COD

Re: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

Ping!! From: Srinath Parvathaneni Sent: 13 December 2021 10:44 To: gcc-patches@gcc.gnu.org Cc: Kyrylo Tkachov ; Richard Earnshaw ; Tejas Belagod Subject: Re: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature

Re: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

Ping!! From: Srinath Parvathaneni Sent: 12 November 2021 18:03 To: gcc-patches@gcc.gnu.org Cc: Kyrylo Tkachov ; Richard Earnshaw ; Tejas Belagod Subject: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature

[PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify. (IS_PAC_Pseudo_REGNUM): Define. (enum reg_class): Add PAC_REG entry. * config/arm/arm.md (RA_AUTH_CODE): Define. gcc/testsuite/ChangeLog: 2021-11-12 Srinath Parvathaneni * g++.target/arm/pac-1.C

[PATCH][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.

config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify. (IS_PAC_Pseudo_REGNUM): Define. (enum reg_class): Add PAC_REG entry. * config/arm/arm.md (RA_AUTH_CODE): Define. gcc/testsuite/ChangeLog: 2021-11-12 Srinath Parvathaneni * gcc.target/arm/pac-6.c

[PATCH][GCC-11] arm: Fix multilib mapping for CDE extensions [PR100856].

compiler options which are not required for multilib linking from march string and assign the new string to mlibarch option. This mlibarch string is used for multilib comparison. Ok for gcc-11 branch? Regards, Srinath. gcc/ChangeLog: 2021-06-10 Srinath Parvathaneni PR target/100856

[PATCH][GCC-10] arm: Fix multilib mapping for CDE extensions [PR100856].

compiler options which are not required for multilib linking from march string and assign the new string to mlibarch option. This mlibarch string is used for multilib comparison. Ok for gcc-10 branch? Regards, Srinath. gcc/ChangeLog: 2021-06-10 Srinath Parvathaneni PR target/100856

[GCC][PATCH] arm: Fix multilib mapping for CDE extensions [PR100856].

/gcc-patches/2021-June/571731.html Regards, Srinath. gcc/ChangeLog: 2021-06-14 Srinath Parvathaneni PR target/100856 * common/config/arm/arm-common.c (arm_canon_arch_option_1): New function derived from arm_canon_arch. (arm_canon_arch_option): Call

[GCC-10 backport][PATCH] arm: Fix polymorphic variants failing with undefined reference to `__ARM_undef` error.

s, Srinath. gcc/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/101016 * config/arm/arm_mve.h (__arm_vld1q): Change __ARM_mve_coerce(p0, int8_t const *) to __ARM_mve_coerce1(p0, int8_t *) in the argument for the polymorphic variants mat

[GCC-11 backport][PATCH] arm: Fix polymorphic variants failing with undefined reference to `__ARM_undef` error.

/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/101016 * config/arm/arm_mve.h (__arm_vld1q): Change __ARM_mve_coerce(p0, int8_t const *) to __ARM_mve_coerce1(p0, int8_t *) in the argument for the polymorphic variants matching code. (__arm_vld1q_z)

[GCC-10 backport][PATCH] arm: Fix the mve multilib for the broken cmse support (pr99939).

-10 branch? Regards, Srinath. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/99939 * gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler directives check for target is v8.1-m.main+mve or not before comparing the assem

[GCC-11 backport][PATCH] arm: Fix the mve multilib for the broken cmse support (pr99939).

-11 branch? Regards, Srinath. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/99939 * gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler directives check for target is v8.1-m.main+mve or not before comparing the assem

[GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).

in PR99939 and this patch fixes the issue. Regression tested on arm-none-eabi and found no regressions. Ok for master? and Ok for GCC-10 branch? Regards, Srinath. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/99939 * gcc.target/arm/cmse/cmse-18.c: Add sep

[GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).

in PR99939 and this patch fixes the issue. Regression tested on arm-none-eabi and found no regressions. Ok for master? and Ok for GCC-10 branch? Regards, Srinath. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni * gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler

RE: [GCC][PATCH] arm: Fix multilib mapping for CDE extensions.

Hi Richard, I have all addressed all your review comments in the trailing in the patch attached. Please review and let me know if it ok for master? Regards, Srinath. > -Original Message- > From: Richard Earnshaw > Sent: 02 June 2021 15:20 > To: Srinath Parvathaneni ;

[GCC][PATCH] arm: Fix polymorphic variants failing with undefined reference to `__ARM_undef` error.

_arm_vld2q): Likewise. (__arm_vld4q): Likewise. (__arm_vldrbq_gather_offset): Likewise. (__arm_vldrbq_gather_offset_z): Likewise. gcc/testsuite/ChangeLog: 2021-06-10 Srinath Parvathaneni PR target/101016 * gcc.target/arm/mve/intrinsics/pr101016.c

RE: [GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).

Hi Richard, > -Original Message- > From: Richard Earnshaw > Sent: 13 April 2021 14:55 > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Earnshaw > Subject: Re: [GCC][Patch] arm: Fix the mve multilib for the broken cmse > support (pr99939). >

[GCC][PATCH] arm: Fix multilib mapping for CDE extensions.

no regressions. Ok for master? Regards, Srinath. gcc/ChangeLog: 2021-06-01 Srinath Parvathaneni PR target/100856 * common/config/arm/arm-common.c (arm_canon_arch_option): Modify function to generate canonical march string after removing cde related compiler extensions

RE: [GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for -O0 (pr97205).

Ping!! > -Original Message- > From: Srinath Parvathaneni > Sent: 30 April 2021 16:24 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > > Subject: [GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for > -O0 (pr97205). > &g

[GCC-10 backport][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).

/ChangeLog: 2021-05-04 Srinath Parvathaneni PR target/100419 * config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong arguments. (__arm_vcmpneq): Remove duplicate definition. (__arm_vstrwq_scatter_offset_p): Likewise. (__arm_vmaxq_x): Likewise

[GCC-11 backport][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).

/ChangeLog: 2021-05-04 Srinath Parvathaneni PR target/100419 * config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong arguments. (__arm_vcmpneq): Remove duplicate definition. (__arm_vstrwq_scatter_offset_p): Likewise. (__arm_vmaxq_x): Likewise

[GCC-10 backport][PATCH] arm: PR target/95646: Do not clobber callee saved registers with CMSE.

Hi, This is a backport to gcc-10, cleanly applied on the branch. As reported in bugzilla when the -mcmse option is used while compiling for size (-Os) with a thumb-1 target the generated code will clear the registers r7-r10. These however are callee saved and should be preserved accross ABI

[GCC-10 backport][PATCH] arm: Fix testisms introduced with fix for pr target/95646.

Hi, This is a backport to gcc-10, cleanly applied on the branch. This patch changes the test to use the effective-target machinery disables the error message "ARMv8-M Security Extensions incompatible with selected FPU" when -mfloat-abi=soft. Further changes 'asm' to '__asm__' to avoid failures

RE: [GCC][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).

Hi Richard, > -Original Message- > From: Richard Earnshaw > Sent: 05 May 2021 11:15 > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Cc: Richard Earnshaw > Subject: Re: [GCC][PATCH] arm: Remove duplicate definitions from > arm_mve.h (pr100419). >

[GCC][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).

-05-04 Srinath Parvathaneni PR target/100419 * config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong arguments. (__arm_vcmpneq): Remove duplicate definition. (__arm_vstrwq_scatter_offset_p): Likewise. (__arm_vmaxq_x): Likewise

[GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for -O0 (pr97205).

Hi, This is a backport to GCC-10 to fix PR97205, patch applies cleanly on the branch. Regression tested and found no issues. Ok for GCC-10 backport? Regards, Srinath. This makes sure that stack allocated SSA_NAMEs are at least MODE_ALIGNED. Also increase the MEM_ALIGN for the

[GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).

? Regards, Srinath. gcc/testsuite/ChangeLog: 2021-04-12 Srinath Parvathaneni PR target/99939 * gcc.target/arm/cmse/cmse-20.c: New test. libgcc/ChangeLog: 2021-04-12 Srinath Parvathaneni PR target/99939 * config/arm/t-arm: Make changes to use cmse

[PATCH][GCC-10 backport][COMMITTED] arm: Fix the warning -mcpu=cortex-m55 conflicting with -march=armv8.1-m.main (pr97327).

: cc1: warning: switch '-mcpu=cortex-m55' conflicts with '-march=armv8.1-m.main' switch After this patch for above combinations no warning/errors. gcc/ChangeLog: 2020-10-16 Srinath Parvathaneni PR target/97327 * config/arm/arm.c (fp_bitlist): Add isa_bit_mve_float to FP bits

[PATCH][GCC] arm: Fix the warning -mcpu=cortex-m55 conflicting with -march=armv8.1-m.main (pr97327).

no warning/errors. Regression tested on arm-none-eabi and found no regressions. Ok for master? Ok for GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2020-10-16 Srinath Parvathaneni PR target/97327 * config/arm/arm.c (fp_bitlist): Add isa_bit_mve_float to FP bits array. gcc

[PATCH][GCC-10 backport] arm: [MVE] Remove illegal intrinsics (PR target/96914)

Hello, Applied cleanly, Ok for backporting this patch to GCC-10? A few MVE intrinsics had an unsigned variant implement while they are supported by the hardware. This patch removes them: __arm_vqrdmlashq_n_u8 __arm_vqrdmlahq_n_u8 __arm_vqdmlahq_n_u8 __arm_vqrdmlashq_n_u16 __arm_vqrdmlahq_n_u16

[PATCH][GCC-10 backport] arm: [MVE] Add vqdmlashq intrinsics (PR target/96914)

Hello, Applied cleanly, Ok for backporting this patch to GCC-10? This patch adds: vqdmlashq_m_n_s16 vqdmlashq_m_n_s32 vqdmlashq_m_n_s8 vqdmlashq_n_s16 vqdmlashq_n_s32 vqdmlashq_n_s8 2020-10-08 Christophe Lyon gcc/ PR target/96914 * config/arm/arm_mve.h (vqdmlashq,

[PATCH][GCC-10 backport] arm: [MVE] Add missing __arm_vcvtnq_u32_f32 intrinsic (PR 96914)

Hello, Applied cleanly, Ok for backporting this patch to GCC-10? __arm_vcvtnq_u32_f32 was missing from arm_mve.h, although the s32_f32 and [su]16_f16 versions were present. This patch adds the missing version and testcase, which are cut-and-paste from the other versions. 2020-10-08 Christophe

[PATCH][COMMITTED][GCC-10 backport] arm: Fix wrong code generated for mve scatter store with writeback intrinsics with -O2 (PR97271).

one vstrw assembly instruction (C). Patch backport approved here https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556373.html gcc/ChangeLog: 2020-10-06 Srinath Parvathaneni PR target/97271 * config/arm/arm-builtins.c (arm_strsbwbs_qualifiers): Mod

[PATCH][GCC] arm: Fix wrong code generated for mve scatter store with writeback intrinsics with -O2 (PR97271).

s32 intrinsic where as fix generates only one vstrw assembly instruction (C). Bootstrapped on arm-none-linux-gnueabihf and regression tested on arm-none-eabi and found no regressions. Ok for master? Ok for GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2020-10-06 Srinath Parvathaneni

[PATCH][GCC-10 backport] arm: Add +nomve and +nomve.fp options to -mcpu=cortex-m55.

Backport of Joe's patch wit no changes. This patch rearranges feature bits for MVE and FP to implement the following flags for -mcpu=cortex-m55. - +nomve:equivalent to armv8.1-m.main+fp.dp+dsp. - +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve). - +nofp:

[GCC-10 backport][COMMITTED] arm: Move iterators from mve.md to iterators.md to maintain consistency.

to unspecs.md file. gcc/ChangeLog: 2020-10-06 Srinath Parvathaneni * config/arm/iterators.md (MVE_types): Move mode iterator from mve.md to iterators.md. (MVE_VLD_ST): Likewise. (MVE_0): Likewise. (MVE_1): Likewise. (MVE_3): Likewise. (MVE_2

RE: [PATCH][GCC] arm: Move iterators from mve.md to iterators.md to maintain consistency.

Hi Kyrill, > -Original Message- > From: Kyrylo Tkachov > Sent: 06 October 2020 14:42 > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Subject: RE: [PATCH][GCC] arm: Move iterators from mve.md to iterators.md > to maintain consistency. > > &

[PATCH][GCC-10 backport] arm: Remove coercion from scalar argument to vmin & vmax intrinsics.

Hello, Straight backport of Joe's patch with no changes. This patch fixes an issue with vmin* and vmax* intrinsics which accept a scalar argument. Previously when the scalar was of different width to the vector elements this would generate __ARM_undef. This change allows the scalar argument to

[PATCH][GCC] arm: Move iterators from mve.md to iterators.md to maintain consistency.

for master? Ok for GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2020-10-06 Srinath Parvathaneni * config/arm/iterators.md (MVE_types): Move mode iterator from mve.md to iterators.md. (MVE_VLD_ST): Likewise. (MVE_0): Likewise. (MVE_1): Likewise

[COMMITTED][GCC-10 backport] arm: Fix MVE intrinsics polymorphic variants wrongly generating __ARM_undef type (pr96795).

-linux-gnueabihf and regression tested on arm-none-eabi and found no regressions. Patch already approved in https://gcc.gnu.org/pipermail/gcc-patches/2020-September/555185.html , so committed this patch to releases/gcc-10 branch. Regards, Srinath. gcc/ChangeLog: 2020-09-30 Srinath

[GCC][PATCH] arm: Fix MVE intrinsics polymorphic variants wrongly generating __ARM_undef type (pr96795).

and found no regressions. Ok for master? Ok for GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2020-09-30 Srinath Parvathaneni PR target/96795 * config/arm/arm_mve.h (__ARM_mve_coerce2): Define. (__arm_vaddq): Correct the scalar argument. (__arm_vaddq_m

[PATCH][GCC-10 Backport] arm: Fix the failing mve scalar shift execution tests.

. Regression tested on arm-none-eabi and found no regressions. Ok for GCC-10 branch? Thanks, Srinath. 2020-06-18 Srinath Parvathaneni gcc/ * doc/sourcebuild.texi (arm_v8_1m_mve_fp_ok): Add item. (arm_mve_hw): Likewise. gcc/testsuite/ * gcc.target/arm/mve/intrinsics

RE: [PATCH][GCC-10 Backport] arm: Fix MVE scalar shift intrinsics code-gen.

Hi, > -Original Message- > From: Christophe Lyon > Sent: 18 June 2020 16:44 > To: Srinath Parvathaneni > Cc: gcc-patches@gcc.gnu.org; Kyrylo Tkachov > Subject: Re: [PATCH][GCC-10 Backport] arm: Fix MVE scalar shift intrinsics > code-gen. > > On Thu, 18

RE: [PATCH][GCC-10 Backport] arm: Fix MVE scalar shift intrinsics code-gen.

Hi, > -Original Message- > From: Christophe Lyon > Sent: 18 June 2020 16:06 > To: Kyrylo Tkachov > Cc: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Subject: Re: [PATCH][GCC-10 Backport] arm: Fix MVE scalar shift intrinsics > code-gen. > > Hi, >

RE: [PATCH][GCC] arm: Fix the failing mve scalar shift execution tests.

Hi, > -Original Message- > From: Christophe Lyon > Sent: 18 June 2020 14:38 > To: Srinath Parvathaneni > Cc: gcc Patches > Subject: Re: [PATCH][GCC] arm: Fix the failing mve scalar shift execution > tests. > > Hi, > > > On Thu, 18 Jun 2020 at

[PATCH][GCC] arm: Fix the failing mve scalar shift execution tests.

. Regression tested on arm-none-eabi and found no regressions. Ok for master? Ok for GCC-10 branch? Thanks, Srinath. 2020-06-18 Srinath Parvathaneni gcc/ * doc/sourcebuild.texi (arm_v8_1m_mve_fp_ok): Add item. (arm_mve_hw): Likewise. gcc/testsuite/ * gcc.target/arm/mve/mve.exp

[PATCH][GCC-10 Backport] arm: Fix the MVE ACLE vaddq_m polymorphic variants.

h? Thanks, Srinath. 2020-06-04 Srinath Parvathaneni gcc/ * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Correct the intrinsic arguments. (__arm_vaddq_m_n_s32): Likewise. (__arm_vaddq_m_n_s16): Likewise. (__arm_vaddq_m_n_u8): Likewise. (__arm_vad

[PATCH][GCC-10 Backport] arm: Fix MVE scalar shift intrinsics code-gen.

rinath. 2020-06-12 Srinath Parvathaneni gcc/ * config/arm/mve.md (mve_uqrshll_sat_di): Correct the predicate and constraint of all the operands. (mve_sqrshrl_sat_di): Likewise. (mve_uqrshl_si): Likewise. (mve_sqrshr_si): Likewise. (mve_uqshll_di): Li

[PATCH][GCC-10 Backport] arm: Fix the wrong code-gen generated by MVE vector load/store intrinsics (PR94959).

//developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics [2] https://developer.arm.com/docs/ddi0553/latest Regression tested on arm-none-eabi and found no regressions. Ok for gcc-10 branch? Thanks, Srinath. gcc/ChangeLog: 2020-06-09 Srinath Parvathaneni Back

[PATCH][GCC-10 Backport] arm: Fix the MVE ACLE vbicq intrinsics.

egressions. Ok for GCC-10 branch? Thanks, Srinath. gcc/ChangeLog: 2020-05-20 Srinath Parvathaneni Backported from mainline 2020-06-04 Srinath Parvathaneni * config/arm/arm_mve.h (__arm_vbicq_n_u16): Correct the intrinsic arguments. (__arm_v

[PATCH][GCC-10 Backport] arm: Correct the grouping of operands in MVE vector scatter store intrinsics (PR94735).

and found no regressions. Ok for GCC-10 branch? Thanks, Srinath. gcc/ChangeLog: 2020-06-09 Srinath Parvathaneni Backported from mainline 2020-06-04 Srinath Parvathaneni PR target/94735 * config/arm//predicates.md (mve_scatter_memory): Define to match

[PATCH][GCC-10 Backport] arm: Fix unintentional fall throughs in arm.c

Hi all, This small patch fix some unintentional fall-throughs in `mve_vector_mem_operand'. Regtested and bootstraped on arm-linux-gnueabihf. Okay for GCC-10 branch? Regards, Srinath gcc/ChangeLog 2020-06-09 Srinath Parvathaneni Backported from mainline 2020-05-28 Andrea

[PATCH][GCC] arm: Fix MVE scalar shift intrinsics code-gen.

more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for master and gcc-10 branch? Thanks, Srinath. gcc/ChangeLog: 2020-06-12 Srinath Parvathaneni * c

[PATCH][GCC] arm: Fix the MVE ACLE vaddq_m polymorphic variants.

etails. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for master and gcc-10 branch? Thanks, Srinath. gcc/ChangeLog: 2020-06-04 Srinath Parvathaneni * config/arm

[GCC][PATCH][ARM]: Correct the grouping of operands in MVE vector scatter store intrinsics (PR94735).

and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2020-06-02 Srinath Parvathaneni PR target/94735 * config/arm//predicates.md (mve_scatter_memory): Define to match (mem (reg)) for scatter store memory. * config/arm/mve.md (mve_v

[PATCH][GCC] arm: Fix the MVE ACLE vbicq intrinsics.

egressions. Ok for master and gcc-10 branch? Thanks, Srinath. gcc/ChangeLog: 2020-05-20 Srinath Parvathaneni * config/arm/arm_mve.h (__arm_vbicq_n_u16): Correct the intrinsic arguments. (__arm_vbicq_n_s16): Likewise. (__arm_vbicq_n_u32)

RE: [GCC][PATCH][ARM]: Fix the wrong code-gen generated by MVE vector load/store intrinsics (PR94959).

Hi Martin, > -Original Message- > From: Martin Liška > Sent: 20 May 2020 11:51 > To: Srinath Parvathaneni ; Christophe Lyon > > Cc: Richard Earnshaw ; gcc Patches patc...@gcc.gnu.org> > Subject: Re: [GCC][PATCH][ARM]: Fix the wrong code-gen generated by

[ARM]: Fix typo in documentation.

The command line option to enable Armv8.1-M Mainline Security Extensions has a typo and this patch corrects it. Committed it under the obvious rule. ### Attachment also inlined for ease of reply### diff --git a/htdocs/gcc-10/changes.html

[ARM][wwwdocs]: Document Armv8.1-M Mainline Security Extensions changes.

Armv8.1-M Mainline Security Extensions related changes in GCC-10. ### Attachment also inlined for ease of reply### diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html index

[ARM][wwwdocs]: Document Armv8.1-M, Helium Intrinsics and Cortex-M55 changes.

M-profile related changes in GCC-10. ### Attachment also inlined for ease of reply### diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html index d1a7df0a9259292d097c1c3b9daeab56329ea435..57ca749da72ed64da37b3eb5404cf5cde8be44dd 100644 ---

RE: [GCC][PATCH][ARM]: Fix the wrong code-gen generated by MVE vector load/store intrinsics (PR94959).

Hi, > -Original Message- > From: Christophe Lyon > Sent: 13 May 2020 11:20 > To: Srinath Parvathaneni > Cc: gcc Patches ; Richard Earnshaw > > Subject: Re: [GCC][PATCH][ARM]: Fix the wrong code-gen generated by MVE > vector load/store intrinsics (PR94959). >

[GCC][PATCH][ARM]: Fix the wrong code-gen generated by MVE vector load/store intrinsics (PR94959).

(mve_vstrwq_p_v4si): Likewise. (mve_vstrwq_v4si): Likewise.Modify constriant Us to Ux. * config/arm/predicates.md (mve_memory_operand): Define. gcc/testsuite/ChangeLog: 2020-05-13 Srinath Parvathaneni PR target/94959 * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Mod

[GCC][PATCH][ARM]: Change arm constraint name from "e" to "Te".

Hello, This patches changes the constraint "e" to "Te". Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2020-04-24 Srinath Parvathaneni * config/arm/constraints.md (e): Remove constraint. (Te

[GCC][PATCH][ARM]: Modify the MVE polymorphic variant arguments to match the MVE intrinsic definition.

-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2020-04-22 Srinath Parvathaneni * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's datatype

[GCC][PATCH][ARM]: Fix for MVE ACLE intrinsics with writeback (PR94317).

] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2020-03-31 Srinath Parvathaneni PR target/94317 * config

[GCC][ARM][PATCH]: Add MVE ACLE intrinsics vbicq_n_* polymorphic variant support.

] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2020-03-30 Srinath Parvathaneni * config/arm/arm_mve.h (vbicq

[GCC][ARM][PATCH]: Add support for MVE ACLE intrinsics polymorphic variants for +mve.fp option.

/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2020-03-24 Srinath Parvathaneni * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the common section of both MVE Integer

[PATCH v2][ARM][GCC][14x]: MVE ACLE whole vector left shift with carry intrinsics.

, Srinath. gcc/ChangeLog: 2019-11-08 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm_mve.h (vshlcq_m_s8): Define macro. (vshlcq_m_u8): Likewise. (vshlcq_m_s16): Likewise. (vshlcq_m_u16): Likewise. (vshlcq_m_s32

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