ping
> -Original Message-
> From: Tamar Christina
> Sent: Tuesday, August 20, 2024 2:06 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; rguent...@suse.de; j...@ventanamicro.com
> Subject: [PATCH 2/2]middle-end: use two's complement equality when comparing
> IVs
ping
> -Original Message-
> From: Tamar Christina
> Sent: Tuesday, August 20, 2024 2:06 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; rguent...@suse.de; j...@ventanamicro.com
> Subject: [PATCH 1/2]middle-end: refactor type to be explicit in
> operand_equal_p
>
> -Original Message-
> From: Richard Sandiford
> Sent: Monday, September 9, 2024 9:29 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; ktkac...@gcc.gnu.org
> Subject: Re: [PATCH 4/4]AArch64: Define VECTOR_STOR
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Friday, September 6, 2024 2:15 PM
> To: Tamar Christina
> Cc: GCC Patches ; nd ; Richard Biener
> ; j...@ventanamicro.com
> Subject: Re: [PATCH]middle-end: check that the lhs of a COND_EXPR is an
> SSA_NAME i
> -Original Message-
> From: Richard Sandiford
> Sent: Friday, September 6, 2024 2:21 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd
> Subject: Re: [PATCH 3/4][rtl]: simplify boolean vector EQ and NE comparisons
>
> Tamar Christina writes:
>
> -Original Message-
> From: Richard Biener
> Sent: Friday, September 6, 2024 2:09 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> Subject: Re: [PATCH 2/4]middle-end: lower COND_EXPR into gimple form in
> vect_recog_bool_patte
Hi All,
Because the vect_recog_bool_pattern can at the moment still transition
out of GIMPLE and back into GENERIC the vect_recog_cond_store_pattern can
end up using an expression as a mask rather than an SSA_NAME.
This adds an explicit check that we have a mask and not an expression.
Bootstrapp
Hi All,
This defines VECTOR_STORE_FLAG_VALUE to CONST1_RTX for AArch64
so we simplify vector comparisons in AArch64.
With this enabled
res:
moviv0.4s, 0
cmeqv0.4s, v0.4s, v0.4s
ret
is simplified to:
res:
mvniv0.4s, 0
ret
NOTE: I don't really
Hi All,
This adds vector constant simplification for EQ and NE. This is useful since
the vectorizer generates a lot more vector compares now, in particular NE and EQ
and so these help us optimize cases where the values were not known at GIMPLE
but instead only at RTL.
Bootstrapped Regtested on a
Hi All,
Currently the vectorizer cheats when lowering COND_EXPR during bool recog.
In the cases where the conditonal is loop invariant or non-boolean it instead
converts the operation back into GENERIC and hides much of the operation from
the analysis part of the vectorizer.
i.e.
a ? b : c
is
Hi All,
When vectorizing a conditional operation we rely on the bool_recog pattern to
hit and convert the bool of the operand to a valid mask.
However we are currently not using the converted operand as this is in a pattern
statement. This change updates it to look at the actual statement to be
Hi All,
The list of available architecture for Arm is incorrectly listing armv9-a twice.
This removes the duplicate armv9-a enumeration from the part of the list having
M-profile targets.
committed under the obvious rule.
Thanks,
Tamar
gcc/ChangeLog:
* doc/invoke.texi: Remove duplicate
Hi All,
The meaning of the testcase was changed by passing it -fwrapv. The reason for
the test failures on some platform was because the test was testing some
implementation defined behavior wrt INT_MIN in generic code.
Instead of using -fwrapv this just removes the border case from the test so
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Wednesday, August 28, 2024 8:55 AM
> To: Tamar Christina
> Cc: Richard Sandiford ; Jennifer Schmitz
> ; gcc-patches@gcc.gnu.org; Kyrylo Tkachov
>
> Subject: Re: [RFC][PATCH] AArch64: Remove
> AARCH64_EXTR
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, August 27, 2024 11:46 AM
> To: Tamar Christina
> Cc: Jennifer Schmitz ; gcc-patches@gcc.gnu.org; Kyrylo
> Tkachov
> Subject: Re: [RFC][PATCH] AArch64: Remove
> AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_CO
Hi Jennifer,
> -Original Message-
> From: Jennifer Schmitz
> Sent: Friday, August 23, 2024 1:07 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford ; Kyrylo Tkachov
>
> Subject: [RFC][PATCH] AArch64: Remove
> AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
>
> This patch removes the AARCH6
> -Original Message-
> From: Richard Biener
> Sent: Wednesday, August 21, 2024 12:12 PM
> To: Tamar Christina
> Cc: GCC Patches
> Subject: Re: [RFC] Support single lane SLP early break
>
> On Tue, 20 Aug 2024, Tamar Christina wrote:
>
> > Hi,
> &g
> -Original Message-
> From: Torbjorn SVENSSON
> Sent: Wednesday, August 21, 2024 2:23 PM
> To: Tamar Christina ; Richard Biener
>
> Cc: Jeff Law ; gcc-patches@gcc.gnu.org; Richard
> Earnshaw ; quic_apin...@quicinc.com;
> yvan.r...@foss.st.com
> Subject:
Hi All,
IVOPTS normally uses affine trees to perform comparisons between different IVs,
but these seem to have been missing in two key spots and instead normal tree
equivalencies used.
In some cases where we have a two-complements equivalence but not a strict
signedness equivalencies we end up ge
Hi All,
This is a refactoring with no expected behavioral change.
The goal with this is to make the type of the expressions being used explicit.
I did not change all the recursive calls to operand_equal_p () to recurse
directly to the new function but instead this goes through the top level call
> -Original Message-
> From: Richard Biener
> Sent: Tuesday, August 20, 2024 1:54 PM
> To: Tamar Christina
> Cc: Victor Do Nascimento ; gcc-
> patc...@gcc.gnu.org; claz...@gmail.com; hongtao@intel.com;
> s...@gcc.gnu.org; bernds_...@t-online.de; al...@
> -Original Message-
> From: Richard Biener
> Sent: Tuesday, August 20, 2024 12:33 PM
> To: Torbjorn SVENSSON
> Cc: Jeff Law ; gcc-patches@gcc.gnu.org; Richard
> Earnshaw ; quic_apin...@quicinc.com;
> yvan.r...@foss.st.com; Tamar Christina
> Subject: Re: [PATCH
Hi,
I've been working on a prototype of moving early break to SLP.
As we've discussed on IRC I've decided to first try adding the gconds as roots
and start SLP discovery using them as roots.
This works great and doesn't require any changed to build_slp, it also has the
additional benefit in that
Hi,
As you know I've been working on removing the code that demotes GIMPLE
COND_EXPR to GENERIC during vect_recog_bool_pattern.
To restate why, The issue we currently have today is that the mask (boolean
argument of a COND_EXPR) is not always available during pattern matching.
This is a problem
> -Original Message-
> From: Richard Biener
> Sent: Tuesday, August 20, 2024 10:37 AM
> To: Victor Do Nascimento
> Cc: gcc-patches@gcc.gnu.org; Tamar Christina ;
> claz...@gmail.com; hongtao@intel.com; s...@gcc.gnu.org; bernds_cb1@t-
> online.de; al...@
Hi Pan,
> -Original Message-
> From: Li, Pan2
> Sent: Tuesday, August 20, 2024 1:58 AM
> To: Tamar Christina ; Jakub Jelinek
>
> Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
> juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
> rdapp
> -Original Message-
> From: Jakub Jelinek
> Sent: Monday, August 19, 2024 8:25 PM
> To: Tamar Christina
> Cc: Li, Pan2 ; Richard Biener ;
> gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
> jeffreya...@gmail.com; rdapp@gmail.com; Liu, Hon
Hi Pan,
>
> Thanks Jakub for explaining.
>
> Hi Richard,
>
> Does it mean we need to do some promotion similar as this patch to make the
> vectorizable_call happy
> when there is a constant operand? I am not sure if there is a better approach
> for
> this case.
I'll leave it up to Richi, but
Hi Victor,
> -Original Message-
> From: Victor Do Nascimento
> Sent: Thursday, August 15, 2024 9:44 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Tamar Christina ; claz...@gmail.com;
> hongtao@intel.com; s...@gcc.gnu.org; bernds_...@t-online.de;
> al...@redhat.com;
Hi Victor,
> -Original Message-
> From: Victor Do Nascimento
> Sent: Tuesday, August 13, 2024 1:42 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Tamar Christina ; claz...@gmail.com;
> hongtao@intel.com; s...@gcc.gnu.org; bernds_...@t-online.de;
> al...@redhat.com;
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Monday, August 12, 2024 3:54 PM
> To: Tamar Christina
> Cc: GCC Patches ; Richard Sandiford
>
> Subject: Re: [PATCH][RFC] aarch64: Reduce FP reassociation width for Neoverse
> V2 and set AARCH64_EXTRA_TUNE_FUL
Hi Kyrill,
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Monday, August 12, 2024 3:07 PM
> To: GCC Patches
> Cc: Tamar Christina ; Richard Sandiford
>
> Subject: [PATCH][RFC] aarch64: Reduce FP reassociation width for Neoverse V2
> and set AARCH64_EXTRA_
Hi All,
The optimization to generate a DI signbit constant by using fneg was relying
on nothing being able to push the constant into the negate. It's run quite
late for this reason.
However late combine now runs after it and triggers RTL simplification based on
the neg. When -fno-signed-zeros t
> -Original Message-
> From: Tamar Christina
> Sent: Thursday, August 1, 2024 9:51 AM
> To: Richard Sandiford
> Cc: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org; nd
> ; Richard Earnshaw ; Marcus
> Shawcroft ; ktkac...@gcc.gnu.org
> Subject: RE: [PATCH 8/8]AArch64: ta
> -Original Message-
> From: Richard Sandiford
> Sent: Wednesday, July 31, 2024 7:17 PM
> To: Tamar Christina
> Cc: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org; nd
> ; Richard Earnshaw ; Marcus
> Shawcroft ; ktkac...@gcc.gnu.org
> Subject: Re: [PATCH 8/8]AArch64: ta
Hi Kyrill,
> > /* True if the vector body contains a store to a decl and if the
> > function is known to have a vld1 from the same decl.
> >
> > @@ -17291,6 +17297,17 @@ aarch64_vector_costs::add_stmt_cost (int count,
> vect_cost_for_stmt kind,
> >stmt_cost = aarch64_detect_vector_s
> -Original Message-
> From: Richard Biener
> Sent: Thursday, July 18, 2024 10:00 AM
> To: Tamar Christina
> Cc: GCC Patches ; Richard Sandiford
>
> Subject: RE: [RFC][middle-end] SLP Early break and control flow support in GCC
>
> On Wed, 17 Jul
> -Original Message-
> From: Richard Sandiford
> Sent: Friday, July 26, 2024 2:12 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; ktkac...@gcc.gnu.org
> Subject: Re: [PATCH 1/8]AArch64: Update Neoverse
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Friday, July 26, 2024 1:35 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; ktkac...@gcc.gnu.org; Richard Sandiford
>
> Subject: Re: [PATCH 5/8]AArch64:
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Friday, July 26, 2024 1:10 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; ktkac...@gcc.gnu.org; Richard Sandiford
>
> Subject: Re: [PATCH 1/8]AArch
Hi All,
This is a new version with the confirmed correct part number.
An update TRM is being published.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (neoverse-v3ae): New.
* confi
> -Original Message-
> From: Richard Sandiford
> Sent: Friday, July 26, 2024 10:43 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; ktkac...@gcc.gnu.org
> Subject: Re: [PATCH]AArch64: check for vector mode in g
Hi All,
For historical reasons AArch64 has TI mode vector types but does not consider
TImode a vector mode.
What's happening in the PR is that get_vectype_for_scalar_type is returning
vector(1) TImode for a TImode scalar. This then fails when we call
targetm.vectorize.get_mask_mode (vecmode).exi
> -Original Message-
> From: Richard Sandiford
> Sent: Friday, July 26, 2024 10:24 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; ktkac...@gcc.gnu.org
> Subject: Re: [PATCH]AArch64: check for vector mode in g
Hi All,
this updates the costs for gener-armv9-a based on the updated costs for
Neoverse V2 and Neoverse N2.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/tuning_models/generic_armv9_a.h: Update costs.
---
Hi All,
This adds a cost model and core definition for Neoverse V3AE.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (neoverse-v3ae): New.
* config/aarch64/aarch64-tune.md: Regenera
Hi All,
This adds a cost model and core definition for Cortex-X925.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (cortex-x925): New.
* config/aarch64/aarch64-tune.md: Regenerate.
Hi All,
Gather and scatters are not usually beneficial when the loop count is small.
This is because there's not only a cost to their execution within the loop but
there is also some cost to enter loops with them.
As such this patch models this overhead. For generic tuning we however still
prefe
Hi All,
This adds a cost model and core definition for Neoverse V3.
It also makes Cortex-X4 use the Neoverse V3 cost model.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (cortex-x4): Upda
Hi All,
This updates the cost for Neoverse N2 to reflect the updated
Software Optimization Guide.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/tuning_models/neoversen2.h: Update costs.
---
diff --git a/gc
Hi All,
This adds a cost model and core definition for Neoverse N3 and Cortex-A725.
It also makes Cortex-A725 use the Neoverse N3 cost model.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def
Hi All,
This updates the cost for Neoverse V2 to reflect the updated
Software Optimization Guide.
It also makes Cortex-X3 use the Neoverse V2 cost model.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch
Hi All,
For historical reasons AArch64 has TI mode vector types but does not consider
TImode a vector mode.
What's happening in the PR is that get_vectype_for_scalar_type is returning
vector(1) TImode for a TImode scalar. This then fails when we call
targetm.vectorize.get_mask_mode (vecmode).exi
Hi Both,
> -Original Message-
> From: Jonathan Wakely
> Sent: Monday, July 22, 2024 3:21 PM
> To: Filip Kastl
> Cc: Tamar Christina ; gcc-patches@gcc.gnu.org; nd
>
> Subject: Re: [PATCH][contrib]: support json output from check_GNU_style_lib.py
>
> On Mon,
> -Original Message-
> From: pan2...@intel.com
> Sent: Thursday, July 18, 2024 1:27 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
> Tamar Christina ; jeffreya...@gmail.com;
> rdapp@gmail.com; hongt
Hi All,
It would be useful to automated tools if check_GNU_style[_lib] supported
returning the result in a structured format like json.
With this change calling:
> cat patch | ./contrib/check_GNU_style.py --format json - | jq .
produces:
[
{
"type": 1,
"msg": "lines should not excee
> -Original Message-
> From: Richard Sandiford
> Sent: Wednesday, July 17, 2024 8:55 PM
> To: Richard Biener
> Cc: pan2...@intel.com; gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai;
> kito.ch...@gmail.com; Tamar Christina ;
> jeffreya...@gmail.com; rdapp..
> -Original Message-
> From: Richard Biener
> Sent: Tuesday, July 16, 2024 4:08 PM
> To: Tamar Christina
> Cc: GCC Patches ; Richard Sandiford
>
> Subject: Re: [RFC][middle-end] SLP Early break and control flow support in GCC
>
> On Mon, 15 Jul 2024, Tamar
> -Original Message-
> From: Richard Biener
> Sent: Tuesday, July 16, 2024 12:47 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> Subject: Re: [PATCH]middle-end: fix 0 offset creation and folding [PR115936]
>
> On Tue, 16 J
Hi All,
As shown in PR115936 SCEV and IVOPTS create an invalidate IV when the IV is
a pointer type:
ivtmp.39_65 = ivtmp.39_59 + 0B;
where the IVs are DI mode and the offset is a pointer.
This comes from this weird candidate:
Candidate 8:
Var befor: ivtmp.39_59
Var after: ivtmp.39_65
Incr
Hi All,
This RFC document covers at a high level how to extend early break support in
GCC to support SLP and how this will be extended in the future to support
full control flow in GCC.
The basic idea in this is based on the paper "All You Need Is Superword-Level
Parallelism: Systematic Control-F
> -Original Message-
> From: Richard Biener
> Sent: Thursday, July 11, 2024 1:10 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; bin.ch...@linux.alibaba.com
> Subject: RE: [PATCH][ivopts]: use affine_tree when comparing IVs during
> candidate
> sele
-Original Message-
> From: Richard Biener
> Sent: Thursday, July 11, 2024 12:39 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; bin.ch...@linux.alibaba.com
> Subject: RE: [PATCH][ivopts]: perform affine fold on unsigned addressing modes
> known not to o
Hi Victor,
> -Original Message-
> From: Victor Do Nascimento
> Sent: Wednesday, July 10, 2024 3:06 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford ; Richard Earnshaw
> ; Victor Do Nascimento
>
> Subject: [PATCH 02/10] autovectorizer: Add basic support for convert optabs
>
> Giv
Hi Victor,
> -Original Message-
> From: Victor Do Nascimento
> Sent: Wednesday, July 10, 2024 3:06 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford ; Richard Earnshaw
> ; Victor Do Nascimento
>
> Subject: [PATCH 10/10] autovectorizer: Test autovectorization of different
> dot-
>
Sorry missed a review comment to change !DR_IS_WRITE into DR_IS_READ.
Updated patch:
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
PR tree-optimization/115531
* tree-vect-patterns.cc (vect_cond_store_pattern_same_re
> -Original Message-
> From: Richard Biener
> Sent: Wednesday, July 10, 2024 10:04 AM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH 2/3] Support group-size of three in SLP load permutation
> lowering
>
> The following adds support for group-size three in SLP load permutation
> lowering
Hi All,
This implements the new target hook indicating that for AArch64 when possible
we prefer masked operations for any type vs doing LOAD + SELECT or
SELECT + STORE.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
PR tree-
> > >
> > > > + }
> > > > +
> > > > + if (new_code == ERROR_MARK)
> > > > + {
> > > > + /* We couldn't flip the condition, so invert the mask
> > > > instead. */
> > > > + itype = TREE_TYPE (cmp_ls);
> > > > + conv = gimple_build_assign (var, BIT_XOR_EXPR,
> > > I might also point back to the idea I threw in somewhere, adding
> > > OEP_VALUE (or a better name) to the set of flags accepted by
> > > operand_equal_p. You mentioned hashing IIRC but I don't see the patches
> > > touching hashing?
> > >
> >
> > Yes, That can indeed be done with this appro
> -Original Message-
> From: Richard Biener
> Sent: Thursday, June 20, 2024 8:55 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; bin.ch...@linux.alibaba.com
> Subject: RE: [PATCH][ivopts]: perform affine fold on unsigned addressing modes
> known not t
> > +v16qi f3b (v16qi a)
> > +{
> > + v16qi zeros = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
> > + return __builtin_shufflevector (a, zeros, 0, 5, 1, 6, 2, 7, 3, 8, 4, 9,
> > 5, 10, 6, 11,
> 7, 12);
> > +}
> > +
> > +/* { dg-final { scan-assembler-times {tbl\tv[0-9]+.16b, \{v[0-9]+.16b\},
> > v[0-
>
> > The principle is that, say:
> >
> > (vec_select:V2SI (reg:V2DI R) (parallel [(const_int 0) (const_int 1)]))
> >
> > is (for little-endian) equivalent to:
> >
> > (subreg:V2SI (reg:V2DI R) 0)
>
> Sigh, of course I meant V4SI rather than V2DI in the above :)
>
> > and similarly for the equi
> -Original Message-
> From: Richard Sandiford
> Sent: Thursday, July 4, 2024 12:46 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; ktkac...@gcc.gnu.org
> Subject: Re: [PATCH 1/2]AArch64: make aarch64_
Hi All,
When a two reg TBL is performed with one operand being a zero vector we can
instead use a single reg TBL and map the indices for accessing the zero vector
to an out of range constant.
On AArch64 out of range indices into a TBL have a defined semantics of setting
the element to zero. Many
Hi All,
The fix for PR18127 reworked the uxtl to zip optimization.
In doing so it undid the changes in aarch64_simd_vec_unpack_lo_ and this now
no longer matches aarch64_simd_vec_unpack_hi_. It still works because the
RTL generated by aarch64_simd_vec_unpack_lo_ overlaps with the general zero
ext
Hi All,
The PR was about SVE codegen, the testcase accidentally used neoverse-n1
instead of neoverse-v1 as was the original report.
This updates the tool options.
Regtested on aarch64-none-linux-gnu and no issues.
committed under the obvious rule.
Thanks,
Tamar
gcc/testsuite/ChangeLog:
nks,
Tamar
> -Original Message-
> From: pan2...@intel.com
> Sent: Tuesday, July 2, 2024 2:32 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
> Tamar Christina ; jeffreya...@gmail.com;
> rdapp@gmail.com; Pan
> -Original Message-
> From: Tamar Christina
> Sent: Monday, July 1, 2024 9:14 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; rguent...@suse.de; j...@ventanamicro.com
> Subject: [PATCH 1/2]middle-end: fix wide_int_constant_multiple_p when VAL and
> DIV are 0. [
Hi All,
The current implementation of constant_multiple_of is doing a more limited
version of aff_combination_constant_multiple_p.
The only non-debug usage of constant_multiple_of will proceed with the values
as affine trees. There is scope for further optimization here, namely I believe
that if
Hi All,
wide_int_constant_multiple_p tries to check if for two tree expressions a and b
that there is a multiplier which makes a == b * c.
This code however seems to think that there's no c where a=0 and b=0 are equal
which is of course wrong.
This fixes it and also fixes the comment.
Bootstrap
> -Original Message-
> From: Richard Biener
> Sent: Friday, June 28, 2024 6:39 AM
> To: Li, Pan2
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
> jeffreya...@gmail.com; rdapp....@gmail.com; Tamar Christina
>
> Subject: Re: [PATCH v3
Hi,
> -Original Message-
> From: Palmer Dabbelt
> Sent: Thursday, June 27, 2024 10:57 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Palmer Dabbelt
> Subject: [RFC PATCH] cse: Add another CSE pass after split1
>
> This is really more of a question than a patch.
>
> Looking at PR/115687 I manag
> -Original Message-
> From: Jason Merrill
> Sent: Tuesday, June 25, 2024 10:24 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; nat...@acm.org
> Subject: Re: [PATCH][c++ frontend]: check for missing condition for novector
> [PR115623]
>
> On 6/2
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Thursday, June 27, 2024 3:49 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw ;
> Richard Sandiford
> Subject: Re: [PATCH] aarch64: Remove RNG and MTE from -mcpu=neoverse-v2
>
> H
Hi Kyrill,
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Thursday, June 27, 2024 9:58 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
>
> Subject: [PATCH] aarch64: Remove RNG and MTE from -mcpu=neoverse-v2
>
> Hi all,
>
> According to the TRM for Neove
> -Original Message-
> From: Richard Biener
> Sent: Wednesday, June 26, 2024 2:23 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com
> Subject: Re: [PATCH]middle-end: Implement conditonal store vectorizer pattern
> [PR115531]
>
The 06/25/2024 17:10, Jason Merrill wrote:
> On 6/25/24 04:01, Tamar Christina wrote:
> > Hi All,
> >
> > It looks like I forgot to check in the C++ frontend if a condition exist
> > for the
> > loop being adorned with novector. This causes a segfault because c
Hi All,
This adds a conditional store optimization for the vectorizer as a pattern.
The vectorizer already supports modifying memory accesses because of the pattern
based gather/scatter recognition.
Doing it in the vectorizer allows us to still keep the ability to vectorize such
loops for archite
Hi All,
It looks like I forgot to check in the C++ frontend if a condition exist for the
loop being adorned with novector. This causes a segfault because cond isn't
expected to be null.
This fixes it by issuing the same kind of diagnostics we issue for the other
pragmas.
Bootstrapped Regtested
> -Original Message-
> From: Li, Pan2
> Sent: Tuesday, June 25, 2024 7:06 AM
> To: Tamar Christina ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
> jeffreya...@gmail.com; pins...@gmail.com
> Subject: RE: [PA
> -Original Message-
> From: Li, Pan2
> Sent: Tuesday, June 25, 2024 3:25 AM
> To: Tamar Christina ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
> jeffreya...@gmail.com; pins...@gmail.com
> Subject: RE: [PA
Hi,
> -Original Message-
> From: pan2...@intel.com
> Sent: Monday, June 24, 2024 2:55 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
> jeffreya...@gmail.com; pins...@gmail.com; Pan Li
> Subject: [PATCH v2] Vect: Support trun
> -Original Message-
> From: Richard Biener
> Sent: Thursday, June 20, 2024 8:55 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; bin.ch...@linux.alibaba.com
> Subject: RE: [PATCH][ivopts]: perform affine fold on unsigned addressing modes
> known not t
> -Original Message-
> From: Richard Biener
> Sent: Monday, June 24, 2024 1:34 PM
> To: Hu, Lin1
> Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ;
> ubiz...@gmail.com
> Subject: RE: [PATCH 1/3 v3] vect: generate suitable convert insn for int ->
> int, float
> -> float and int <-> float.
>
>
> -Original Message-
> From: Richard Biener
> Sent: Thursday, June 20, 2024 8:49 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; bin.ch...@linux.alibaba.com
> Subject: RE: [PATCH][ivopts]: use affine_tree when comparing IVs during
> candidate
> -Original Message-
> From: Michael Matz
> Sent: Wednesday, June 19, 2024 3:46 PM
> To: Tamar Christina
> Cc: Richard Biener ; gcc-patches@gcc.gnu.org; nd
> ; bin.ch...@linux.alibaba.com
> Subject: RE: [PATCH][ivopts]: use affine_tree when comparing IVs during
&g
> -Original Message-
> From: Richard Biener
> Sent: Wednesday, June 19, 2024 12:55 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; bin.ch...@linux.alibaba.com
> Subject: Re: [PATCH][ivopts]: use affine_tree when comparing IVs during
> candidate
> -Original Message-
> From: Richard Biener
> Sent: Wednesday, June 19, 2024 1:14 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; bin.ch...@linux.alibaba.com
> Subject: Re: [PATCH][ivopts]: perform affine fold on unsigned addressing modes
> known not t
Hi,
> -Original Message-
> From: Pengxuan Zheng
> Sent: Friday, June 14, 2024 12:57 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Pengxuan Zheng
> Subject: [PATCH v3] aarch64: Add vector popcount besides QImode [PR113859]
>
> This patch improves GCC’s vectorization of __builtin_popcount for aa
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