rth it to implement insn patterns with generic
RTXes instead of unspecs. Maybe some future improvement to generic RTX
simplification will be able to handle them.
>
> 2024-09-19 Uros Bizjak
> Jakub Jelinek
>
> PR target/116738
> * config/i386/subst
On Sat, Sep 14, 2024 at 12:58 PM H.J. Lu wrote:
>
> On Sun, Sep 8, 2024 at 12:10 AM Uros Bizjak wrote:
> >
> > On Fri, Sep 6, 2024 at 2:24 PM H.J. Lu wrote:
> > >
> > > Don't use temp for a PARALLEL BLKmode argument of an EXPR_LIST expression
> >
Enable V4QI, V2QI and V2HI mode signed saturated arithmetic insn patterns
and add a couple of testcases to test for PADDSB and PADDSW instructions.
PR target/112600
gcc/ChangeLog:
* config/i386/mmx.md (3): Rename
from *3.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr112600-3a.c
Double-word memory operands are accessed as their high and low parts, so the
memory location has to be offsettable. Use "o" constraint instead of "m"
for double-word memory operands.
gcc/ChangeLog:
* config/i386/i386.md (*insvdi_lowpart_1): Use "o" constraint
instead of "m" for double-wo
On Fri, Sep 6, 2024 at 2:24 PM H.J. Lu wrote:
>
> Don't use temp for a PARALLEL BLKmode argument of an EXPR_LIST expression
> in a TImode register. Otherwise, the TImode variable will be put in
> the GPR save area which guarantees only 8-byte alignment.
>
> gcc/
>
> PR target/116621
>
On Sat, Aug 31, 2024 at 3:28 PM Roger Sayle wrote:
>
>
> Hi Uros,
>
> As requested this patch is split out from my previous submission.
> https://gcc.gnu.org/pipermail/gcc-patches/2024-August/659450.html
> This patch enables STV when the first operand of a TImode binary
> logic operand (AND, IOR o
On Fri, Aug 30, 2024 at 6:49 AM liuhongt wrote:
>
> > Can the above loop be a part of ix86_check_avx_upper_register, so this
> > function would scan the full RTX for avx upper register?
> Changed, also adjust ix86_check_avx_upper_stores and ix86_avx_u128_mode_needed
> to either inline the old ix86
On Thu, Aug 29, 2024 at 9:33 AM liuhongt wrote:
>
> For function arguments/return, when it's BLK mode, it's put in a
> parallel with an expr_list, and the expr_list contains the real mode
> and registers.
> Current ix86_check_avx_upper_register only checked for SSE_REG_P, and
> failed to handle th
V sob., 24. avg. 2024 17:11 je oseba Roger Sayle
napisala:
>
> This patch tweaks timode_scalar_chain::compute_convert_gain to better
> reflect the expansion of V1TImode arithmetic right shifts by the i386
> backend. The comment "see ix86_expand_v1ti_ashiftrt" appears after
> "case ASHIFTRT" in c
On Tue, Aug 20, 2024 at 3:06 PM Rainer Orth
wrote:
>
> The new g++.target/i386/pr116275-2.C test FAILs on 32-bit Solaris/x86:
>
> FAIL: g++.target/i386/pr116275-2.C scan-assembler vpslld
>
> This happens because Solaris defaults to -mstackrealign, disabling -mstv.
>
> Fixed by disabling the for
On Tue, Aug 20, 2024 at 12:25 PM liuhongt wrote:
>
> From [1]
> > > It's not obvious to me why movv16qi requires a nonimmediate_operand
> > > source, especially since ix86_expand_vector_mode does have code to
> > > cope with constant operand[1]s. emit_move_insn_1 doesn't check the
> > > predicate
On Thu, Aug 15, 2024 at 9:27 AM liuhongt wrote:
>
> It results in 2 failures for x86_64-pc-linux-gnu{\
> -march=cascadelake};
>
> gcc: gcc.target/i386/extendditi3-1.c scan-assembler cqt?o
> gcc: gcc.target/i386/pr113560.c scan-assembler-times \tmulq 1
>
> For pr113560.c, now GCC generates mulx ins
On Thu, Aug 15, 2024 at 11:34 AM Roger Sayle wrote:
>
>
> As requested this patch is split out from my earlier submission.
> This patch provides more accurate costs/gains for (wide) immediate
> constants in STV, suitably adjusting the costs/gains when the highpart
> and lowpart words are the same.
with make bootstrap
> and make -k check, both with and without --target_board=unix{-m32}
> with no new failures. Ok for mainline?
>
>
> 2024-08-15 Roger Sayle
> Uros Bizjak
>
> gcc/ChangeLog
> * config/i386/i386.md (*extendv2di2_highpart
On Wed, Aug 14, 2024 at 3:28 AM liuhongt wrote:
>
> It results in 2 failures for x86_64-pc-linux-gnu{\
> -march=cascadelake};
>
> gcc: gcc.target/i386/extendditi3-1.c scan-assembler cqt?o
> gcc: gcc.target/i386/pr113560.c scan-assembler-times \tmulq 1
>
> For pr113560.c, now GCC generates mulx ins
On Wed, Aug 14, 2024 at 3:28 AM liuhongt wrote:
>
> It results in 2 failures for x86_64-pc-linux-gnu{\
> -march=cascadelake};
>
> gcc: gcc.target/i386/extendditi3-1.c scan-assembler cqt?o
> gcc: gcc.target/i386/pr113560.c scan-assembler-times \tmulq 1
>
> For pr113560.c, now GCC generates mulx ins
On Sun, Aug 11, 2024 at 12:16 PM Roger Sayle wrote:
>
>
> This patch resolves PR target/116275, a recent ICE-on-valid regression on
> -m32 caused by my recent change to enable STV of DImode arithmeric right
> shift on non-AVX512VL targets. The oversight is that the i386 backend
> contains an *ext
On Fri, Aug 9, 2024 at 9:29 AM Jakub Jelinek wrote:
>
> Hi!
>
> The GENERIC folding of these builtins have cases where it folds to a
> constant regardless of the value of the first operand. If so, we need
> to use omit_one_operand to avoid throwing away side-effects in the first
> operand if any.
On Thu, Aug 8, 2024 at 10:28 AM Roger Sayle wrote:
>
>
> This minor patch, very similar to one posted and approved previously at
> https://gcc.gnu.org/pipermail/gcc-patches/2024-July/657229.html is
> required to restore builds on systems using gcc 4.8 as a host compiler.
> Using the enumeration co
On Mon, Aug 5, 2024 at 5:50 PM Roger Sayle wrote:
>
>
> Hi Uros,
> Very many thanks for the quick review and approval. Here's another.
>
> This patch implements two improvements/refinements to the i386 backend's
> Scalar-To-Vector (STV) pass. The first is to support memory destinations
> in bina
On Mon, Aug 5, 2024 at 12:22 PM Roger Sayle wrote:
>
>
> This patch refactors ashrv2di RTL expansion into a function so that it may
> be reused by a pre-reload splitter, such that DImode right shifts may be
> considered candidates during the Scalar-To-Vector (STV) pass. Currently
> DImode arithme
On Tue, Jul 30, 2024 at 5:05 AM liuhongt wrote:
>
> (insn 98 94 387 2 (parallel [
> (set (reg:TI 337 [ _32 ])
> (ashift:TI (reg:TI 329)
> (reg:QI 521)))
> (clobber (reg:CC 17 flags))
> ]) "test.c":11:13 953 {ashlti3_doubleword}
>
On Wed, Jul 31, 2024 at 11:33 AM Richard Biener wrote:
> > > > > > OK. Richard, can you please mention the above in the comment why
> > > > > > XFmode is rejected in the hook?
> > > > > >
> > > > > > Later, we can perhaps benchmark XFmode move vs. generic memory copy
> > > > > > to
> > > > > > g
On Wed, Jul 31, 2024 at 3:40 PM Richard Biener wrote:
>
> The following implements the hook, excluding x87 modes for scalar
> and complex float modes.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu.
>
> OK this way?
>
> Thanks,
> Richard.
>
> * i386.cc (TARGET_MODE_CAN_TRANSFER_BI
On Wed, Jul 31, 2024 at 11:33 AM Richard Biener wrote:
>
> On Wed, 31 Jul 2024, Uros Bizjak wrote:
>
> > On Wed, Jul 31, 2024 at 10:48 AM Richard Biener wrote:
> > >
> > > On Wed, 31 Jul 2024, Uros Bizjak wrote:
> > >
> > > >
On Wed, Jul 31, 2024 at 10:48 AM Richard Biener wrote:
>
> On Wed, 31 Jul 2024, Uros Bizjak wrote:
>
> > On Wed, Jul 31, 2024 at 10:24 AM Jakub Jelinek wrote:
> > >
> > > On Wed, Jul 31, 2024 at 10:11:44AM +0200, Uros Bizjak wrote:
> > > > OK. Ric
On Wed, Jul 31, 2024 at 10:24 AM Jakub Jelinek wrote:
>
> On Wed, Jul 31, 2024 at 10:11:44AM +0200, Uros Bizjak wrote:
> > OK. Richard, can you please mention the above in the comment why
> > XFmode is rejected in the hook?
> >
> > Later, we can perhaps benchmark
On Wed, Jul 31, 2024 at 10:02 AM Hongtao Liu wrote:
> > > > > > On Tue, 30 Jul 2024, Richard Biener wrote:
> > > > > >
> > > > > > > > Oh, and please add a small comment why we don't use XFmode here.
> > > > > > >
> > > > > > > Will do.
> > > > > > >
> > > > > > > /* Do not enable XFmode,
On Wed, Jul 31, 2024 at 9:11 AM Hongtao Liu wrote:
>
> On Wed, Jul 31, 2024 at 1:06 AM Uros Bizjak wrote:
> >
> > On Tue, Jul 30, 2024 at 3:00 PM Richard Biener wrote:
> > >
> > > On Tue, 30 Jul 2024, Alexander Monakov wrote:
> > >
> > &g
PR target/51492
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr51492.c: New test.
Tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/testsuite/gcc.target/i386/pr51492.c
b/gcc/testsuite/gcc.target/i386/pr51492.c
new file mode 100644
index 000..0892e0c79a7
--- /dev/null
+++
On Tue, Jul 30, 2024 at 3:00 PM Richard Biener wrote:
>
> On Tue, 30 Jul 2024, Alexander Monakov wrote:
>
> >
> > On Tue, 30 Jul 2024, Richard Biener wrote:
> >
> > > > Oh, and please add a small comment why we don't use XFmode here.
> > >
> > > Will do.
> > >
> > > /* Do not enable XFmode
On Tue, Jul 30, 2024 at 1:07 PM Uros Bizjak wrote:
>
> On Tue, Jul 30, 2024 at 12:18 PM Richard Biener wrote:
> >
> > The following implements the hook, excluding x87 modes for scalar
> > and complex float modes.
> >
> > Bootstrapped and tested on
On Tue, Jul 30, 2024 at 12:18 PM Richard Biener wrote:
>
> The following implements the hook, excluding x87 modes for scalar
> and complex float modes.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu.
>
> OK?
>
> Thanks,
> Richard.
>
> * i386.cc (TARGET_MODE_CAN_TRANSFER_BITS): Def
On Tue, Jul 23, 2024 at 4:59 AM Haochen Jiang wrote:
>
> Hi all,
>
> I tested with %a and it works. Therefore I suppose it is a better solution.
>
> Bootstrapped and regtested on x86-64-pc-linux-gnu. Ok for trunk and backport
> to GCC 13 and 14?
OK, also for backports.
Thanks,
Uros.
>
> Thx,
>
On Tue, Jul 23, 2024 at 3:08 AM liuhongt wrote:
>
> ix86_hardreg_mov_ok is added by r11-5066-gbe39636d9f68c4
>
> >The solution proposed here is to have the x86 backend/recog prevent
> >early RTL passes composing instructions (that set likely_spilled hard
> >registers) that they (combin
From: mayshao
PR target/104688
libatomic/ChangeLog:
* config/x86/init.c (__libat_feat1_init): Don't clear
bit_AVX on ZHAOXIN CPUs.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/libatomic/config/x86/init.c b/libatomic/config/x86/init.c
index 261
Check the result of __get_cpuid and process FEAT1_REGISTER only when
__get_cpuid returns success. Use __cpuid instead of nested __get_cpuid.
libatomic/ChangeLog:
* config/x86/init.c (__libat_feat1_init): Check the result of
__get_cpuid and process FEAT1_REGISTER only when __get_cpuid
On Thu, Jul 18, 2024 at 2:07 PM Jakub Jelinek wrote:
>
> On Thu, Jul 18, 2024 at 01:57:11PM +0200, Uros Bizjak wrote:
> > Attached patch illustrates the proposed improvement with nested cpuid
> > calls. Bootstrapped and teased with libatomic testsuite.
> >
> > Jaku
On Thu, Jul 18, 2024 at 10:31 AM Uros Bizjak wrote:
>
> On Thu, Jul 18, 2024 at 10:21 AM Jakub Jelinek wrote:
> >
> > On Thu, Jul 18, 2024 at 10:12:46AM +0200, Uros Bizjak wrote:
> > > On Thu, Jul 18, 2024 at 9:50 AM Jakub Jelinek wrote:
> > > >
> >
On Thu, Jul 18, 2024 at 10:21 AM Jakub Jelinek wrote:
>
> On Thu, Jul 18, 2024 at 10:12:46AM +0200, Uros Bizjak wrote:
> > On Thu, Jul 18, 2024 at 9:50 AM Jakub Jelinek wrote:
> > >
> > > On Thu, Jul 18, 2024 at 09:34:14AM +0200, Uros Bizjak wrote:
> >
On Thu, Jul 18, 2024 at 9:50 AM Jakub Jelinek wrote:
>
> On Thu, Jul 18, 2024 at 09:34:14AM +0200, Uros Bizjak wrote:
> > > > + unsigned int ecx2 = 0, family = 0;
> >
> > No need to initialize these two variables.
>
> The function ignores __get_cpuid resu
On Thu, Jul 18, 2024 at 9:29 AM Jakub Jelinek wrote:
>
> On Thu, Jul 18, 2024 at 03:23:05PM +0800, MayShao-oc wrote:
> > From: mayshao
> >
> > Hi Jakub:
> >
> > Thanks for your review,We should just amend this to handle Zhaoxin.
> >
> > Bootstrapped /regtested X86_64.
> >
> > Ok for t
On Thu, Jul 18, 2024 at 8:52 AM Haochen Jiang wrote:
>
> Hi all,
>
> I revised the patch according to the comment.
>
> Ok for trunk?
>
> Thx,
> Haochen
>
> ---
>
> Changes in v2: Add suffix for mov to make the test more robust.
>
> ---
>
> For compile test, we should generate valid asm except for
On Thu, Jul 18, 2024 at 3:35 AM liuhongt wrote:
>
> > Also, in case the insn is deleted, do:
> >
> > emit_note (NOTE_INSN_DELETED);
> >
> > DONE;
> >
> > instead of leaving (const_int 0) in the stream.
> >
> > So, the above insn preparation statements should read:
> >
> > --cut here--
> > if (cons
On Thu, Jul 18, 2024 at 3:46 AM Haochen Jiang wrote:
>
> Hi all,
>
> For compile test, we should generate valid asm except for special purposes.
> Fix the compile test that generates invalid asm.
>
> Regtested on x86-64-pc-linux-gnu. Ok for trunk?
>
> Thx,
> Haochen
>
> gcc/testsuite/ChangeLog:
>
Add missing "cannot_copy" attribute to instructions that have to
stay in 1-1 correspondence with another insn.
PR target/115526
gcc/ChangeLog:
* config/alpha/alpha.md (movdi_er_high_g): Add cannot_copy attribute.
(movdi_er_tlsgd): Ditto.
(movdi_er_tlsldm): Ditto.
(call_value_
On Wed, Jul 17, 2024 at 8:54 AM Liu, Hongtao wrote:
>
>
>
> > -Original Message-
> > From: Uros Bizjak
> > Sent: Wednesday, July 17, 2024 2:52 PM
> > To: Liu, Hongtao
> > Cc: gcc-patches@gcc.gnu.org; crazy...@gmail.com; hjl.to...@gmail.com
> >
On Wed, Jul 17, 2024 at 3:27 AM liuhongt wrote:
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ready push to trunk.
>
> gcc/ChangeLog:
>
> PR target/115843
> * config/i386/predicates.md (const0_or_m1_operand): New
> predicate.
> * config/i386/sse.md
On Sun, Jul 14, 2024 at 3:42 PM Roger Sayle wrote:
>
>
> This is a minor change to restore bootstrap on systems using gcc 4.8
> as a host compiler. The fatal error is:
>
> In file included from gcc/gcc/coretypes.h:471:0,
> from gcc/gcc/config/i386/i386-expand.cc:23:
> gcc/gcc/con
On Wed, Jul 10, 2024 at 3:42 PM haochen.jiang
wrote:
>
> On Linux/x86_64,
>
> 80e446e829d818dc19daa6e671b9626e93ee4949 is the first bad commit
> commit 80e446e829d818dc19daa6e671b9626e93ee4949
> Author: Pan Li
> Date: Fri Jul 5 20:36:35 2024 +0800
>
> Match: Support form 2 for the .SAT_TRUN
A last minute change led to a wrong operand order in the compare insn.
gcc/ChangeLog:
* config/i386/i386.md (ustruncdi2): Swap compare operands.
(ustruncsi2): Ditto.
(ustrunchiqi2): Ditto.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/config
emit_store_flag_1 calculates scode (swapped condition code) at the
beginning of the function from the value of code variable. However,
code variable may change before scode usage site, resulting in
invalid stalled scode value.
Move calculation of scode value just before its only usage site to
avo
On Thu, Jun 13, 2024 at 9:37 AM Alexandre Oliva wrote:
>
> Hello, Maciej,
>
> On Jun 12, 2024, "Maciej W. Rozycki" wrote:
>
> > This has regressed building the `alpha-linux-gnu' target, in libada, as
> > from commit d6b756447cd5 including GCC 14 and up to current GCC 15 trunk:
>
> > | Error dete
The following testcase:
unsigned short foo (unsigned int x)
{
_Bool overflow = x > (unsigned int)(unsigned short)(-1);
return ((unsigned short)x | (unsigned short)-overflow);
}
currently compiles (-O2) to:
foo:
xorl%eax, %eax
cmpl$65535, %edi
seta%al
negl%eax
On Tue, Jul 9, 2024 at 10:38 AM Haochen Jiang wrote:
>
> Hi all,
>
> AVX10 Documentaion has specified ecx value as 0 for AVX10 version and
> vector size under 0x24 subleaf. Although for ecx=1, the bits are all
> reserved for now, we still need to specify ecx as 0 to avoid dirty
> value in ecx.
>
>
Promote HImode x86_movcc_0_m1_neg insn to SImode to avoid
redundant prefixes. Also promote QImode insn when TARGET_PROMOTE_QImode
is set. This is similar to promotable_binary_operator splitter, where we
promote the result to SImode.
Also correct insn condition for splitters to SImode of NEG and NO
On Fri, Jul 5, 2024 at 9:07 AM Hu, Lin1 wrote:
>
> I Modified the changelog and comments.
>
> ssedoublemode's double should mean double type, like SI -> DI.
> And we need to refactor some patterns with instead of
> .
>
> BRs,
> Lin
>
> gcc/ChangeLog:
>
> * config/i386/sse.md (ssedoublemod
On Fri, Jul 5, 2024 at 7:48 AM Hu, Lin1 wrote:
>
> Hi, all
>
> ssedoublemode's double should mean double type, like SI -> DI.
> And we need to refactor some patterns with instead of
> .
>
> Bootstrapped and regtested on x86-64-linux-gnu, OK for trunk?
>
> BRs,
> Lin
>
> gcc/ChangeLog:
>
>
On Mon, Jul 1, 2024 at 3:20 PM Roger Sayle wrote:
>
>
> This patch adds an additional variation of the peephole2 used to convert
> bswaphisi2_lowpart into rotlhi3_1_slp, which converts xchgb %ah,%al into
> rotw if the flags register isn't live. The motivating example is:
>
> void ext(int x);
> vo
On Sun, Jun 30, 2024 at 9:09 PM Roger Sayle wrote:
>
>
> Hi Uros,
> > On Sat, Jun 29, 2024 at 6:21 PM Roger Sayle
> > wrote:
> > > A common idiom for implementing an integer division that rounds
> > > upwards is to write (x + y - 1) / y. Conveniently on x86, the two
> > > additions to form the n
On Sat, Jun 29, 2024 at 6:21 PM Roger Sayle wrote:
>
>
> A common idiom for implementing an integer division that rounds upwards is
> to write (x + y - 1) / y. Conveniently on x86, the two additions to form
> the numerator can be performed by a single lea instruction, and indeed gcc
> currently g
Remove extra assignment, extra temp variable and variable shadowing.
No functional changes intended.
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_expand_move): Remove extra
assignment to tmp variable, reuse tmp variable instead of
declaring new temporary variable and remove tmp
On Fri, Jun 28, 2024 at 1:41 PM Evgeny Karpov
wrote:
>
> Thursday, June 27, 2024 8:13 PM
> Uros Bizjak wrote:
>
> >
> > So, there is no problem having #endif just after else.
> >
> > Anyway, it's your call, this is not a hill I'm willing to die on.
On Fri, Jun 28, 2024 at 7:29 AM liuhongt wrote:
>
> Move pass_stv2 and pass_rpad after pre_reload pass_late_combine, also
> define target_insn_cost to prevent post_reload pass_late_combine to
> revert the optimziation did in pass_rpad.
>
> Adjust testcases since pass_late_combine generates better
On Fri, Jun 28, 2024 at 7:29 AM liuhongt wrote:
>
> late_combine will combine lshift + zero into *lshifrtsi3_1_zext which
> cause extra mov between gpr and kmask, add ?k to the pattern.
>
> gcc/ChangeLog:
>
> PR target/115610
> * config/i386/i386.md (<*insnsi3_zext): Add alternativ
On Thu, Jun 27, 2024 at 9:40 PM Roger Sayle wrote:
>
>
> This patch generalizes some of the patterns in i386.md that recognize
> double word concatenation, so they handle sign_extend the same way that
> they handle zero_extend in appropriate contexts.
>
> As a motivating example consider the follo
On Thu, Jun 27, 2024 at 12:50 PM Evgeny Karpov
wrote:
>
> Thursday, June 27, 2024 10:39 AM
> Uros Bizjak wrote:
>
> > > diff --git a/gcc/config/i386/i386-expand.cc
> > > b/gcc/config/i386/i386-expand.cc
> > > index 5dfa7d49f58..20adb42e17b 100644
>
On Thu, Jun 27, 2024 at 12:49 AM David Malcolm wrote:
>
> On Thu, 2023-11-23 at 17:17 -0500, Antoni Boucher wrote:
> > Hi.
> > I did split the patch and sent one for the bfloat16 support and
> > another
> > one for the vector support.
> >
> > Here's the updated patch for the machine-dependent buil
EN_STORE (vectp_out.12_75, 32B, { -1, ... }, _81, 0,
> vect_patt_49.11_73);
> vectp_op_1.7_69 = vectp_op_1.7_68 + ivtmp_67;
> vectp_out.12_76 = vectp_out.12_75 + ivtmp_74;
> ivtmp_80 = ivtmp_79 - _81;
>
> riscv64-unknown-elf-gcc (GCC) 15.0.0 20240627 (experimental)
>
On Thu, Jun 27, 2024 at 9:16 AM Evgeny Karpov
wrote:
>
> Thank you for reporting the issues and discussing the root causes.
> It helped in preparing the patch.
>
> This patch fixes 3 bugs reported after merging
> the "Add DLL import/export implementation to AArch64" series.
> https://gcc.gnu.org/p
On Mon, Jun 24, 2024 at 3:55 PM wrote:
>
> From: Pan Li
>
> The zip benchmark of coremark-pro have one SAT_SUB like pattern but
> truncated as below:
>
> void test (uint16_t *x, unsigned b, unsigned n)
> {
> unsigned a = 0;
> register uint16_t *p = x;
>
> do {
> a = *--p;
> *p = (ui
On Thu, Jun 27, 2024 at 5:57 AM liuhongt wrote:
>
> > But rtx_cost invokes targetm.rtx_cost which allows to avoid that
> > recursive processing at any level. You're dealing with MEM [addr]
> > here, so why's rtx_cost (addr, Pmode, MEM, 0, speed) not always
> > the best way to deal with this? Sin
On Thu, Jun 20, 2024 at 3:16 AM Hongyu Wang wrote:
>
> Hi,
>
> This patch adjusts several new feature check in ix86_option_override_interal
> that directly use TARGET_* instead of TARGET_*_P (opts->ix86_isa_flags),
> which caused cmdline option overrides target_attribute isa flag.
>
> Bootstrapped
On Tue, Jun 18, 2024 at 9:21 AM mayshao-oc wrote:
>
>
>
> On 5/28/24 14:15, Uros Bizjak wrote:
> >
> >
> >
> > On Mon, May 27, 2024 at 10:33 AM MayShao wrote:
> >>
> >> From: mayshao
> >>
> >> Hi all:
> >>
On Thu, Jun 13, 2024 at 3:44 AM Hongyu Wang wrote:
>
> Thanks for the advice, updated patch in attachment.
>
> Bootstrapped/regtested on x86-64-pc-linux-gnu. Ok for trunk?
>
> Uros Bizjak 于2024年6月12日周三 18:12写道：
> >
> > On Wed, Jun 12, 2024 at 12:00 PM Uros Bizjak
On Wed, Jun 12, 2024 at 12:00 PM Uros Bizjak wrote:
>
> On Wed, Jun 12, 2024 at 5:12 AM Hongyu Wang wrote:
> >
> > Hi,
> >
> > For CTEST, we don't have conditional AND so there's no optimization
> > opportunity to write a new ctest pattern. Emit ct
On Wed, Jun 12, 2024 at 5:12 AM Hongyu Wang wrote:
>
> Hi,
>
> For CTEST, we don't have conditional AND so there's no optimization
> opportunity to write a new ctest pattern. Emit ctest when ccmp did
> comparison to const 0 to save bytes.
>
> Bootstrapped & regtested under x86-64-pc-linux-gnu.
>
>
On Tue, Jun 11, 2024 at 11:21 AM Arthur Cohen wrote:
>
> Thanks Richi!
>
> Tested again and pushed on trunk.
This patch introduced a couple of errors during ./configure:
checking for library containing dlopen... none required
checking for library containing pthread_create... none required
/git/
For TARGET_CMOV targets emit insn sequence involving conditional move.
.SAT_ADD:
addl%esi, %edi
movl$-1, %eax
cmovnc %edi, %eax
ret
.SAT_SUB:
subl%esi, %edi
movl$0, %eax
cmovnc %edi, %eax
ret
PR target/112600
gc
The following testcase:
unsigned
sub_sat (unsigned x, unsigned y)
{
unsigned res;
res = x - y;
res &= -(x >= y);
return res;
}
currently compiles (-O2) to:
sub_sat:
movl%edi, %edx
xorl%eax, %eax
subl%esi, %edx
cmpl%esi, %edi
setnb
On Sat, Jun 8, 2024 at 2:09 PM Gerald Pfeifer wrote:
>
> On Sat, 8 Jun 2024, Uros Bizjak wrote:
> > gcc/ChangeLog:
> >
> > * config/i386/i386.md (usadd3): New expander.
> > (x86_movcc_0_m1_neg): Use SWI mode iterator.
>
> When you write "committed
The following testcase:
unsigned
add_sat(unsigned x, unsigned y)
{
unsigned z;
return __builtin_add_overflow(x, y, &z) ? -1u : z;
}
currently compiles (-O2) to:
add_sat:
addl%esi, %edi
jc .L3
movl%edi, %eax
ret
.L3:
orl $-1, %eax
On Fri, Jun 7, 2024 at 11:48 AM Evgeny Karpov
wrote:
>
> This patch extracts the ix86 implementation for expanding a SYMBOL
> into its corresponding dllimport, far-address, or refptr symbol.
> It will be reused in the aarch64-w64-mingw32 target.
> The implementation is copied as is from i386/i386.
On Fri, Jun 7, 2024 at 11:21 AM Roger Sayle wrote:
>
>
> This patch addresses PR target/115351, which is a code quality regression
> on x86 when passing floating point complex numbers. The ABI considers
> these arguments to have TImode, requiring interunit moves to place the
> FP values (which ar
PR middle-end/112600
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr112600-2a.c: New test.
* gcc.target/i386/pr112600-2b.c: New test.
Tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/testsuite/gcc.target/i386/pr112600-2a.c
b/gcc/testsuite/gcc.target/i386/pr112600-2a.c
new f
tting .SAT_SUB via
__builtin_sub_overflow (and in similar way for saturated add).
Uros.
>
> Pan
>
> -Original Message-
> From: Uros Bizjak
> Sent: Wednesday, June 5, 2024 4:46 PM
> To: Li, Pan2
> Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
> juzhe.zh...@rivai.ai;
On Wed, Jun 5, 2024 at 10:38 AM Li, Pan2 wrote:
>
> > I see. x86 doesn't have scalar saturating instructions, so the scalar
> > version indeed can't be converted.
>
> > I will amend x86 testcases after the vector part of your patch is committed.
>
> Thanks for the confirmation. Just curious, the .
On Wed, Jun 5, 2024 at 10:22 AM Li, Pan2 wrote:
>
> > Is the above testcase correct? You need "(x + y)" as the first term.
>
> Thanks for comments, should be copy issue here, you can take SAT_SUB (x, y)
> => (x - y) & (-(TYPE)(x >= y)) or below template for reference.
>
> +#define DEF_SAT_U_SUB_F
On Wed, Jun 5, 2024 at 9:38 AM Li, Pan2 wrote:
>
> Thanks Richard, will commit after the rebased pass the regression test.
>
> Pan
>
> -Original Message-
> From: Richard Biener
> Sent: Wednesday, June 5, 2024 3:19 PM
> To: Li, Pan2
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kit
On Tue, Jun 4, 2024 at 10:10 PM Evgeny Karpov
wrote:
>
> Richard and Uros, could you please review the changes for v2?
LGTM for the generic x86 part, OS-specific part (cygming) should also
be reviewed by OS port maintainer (CC'd).
Thanks,
Uros.
> Additionally, we have detected an issue with GCC
PR target/115321
gcc/ChangeLog:
* config/i386/i386.md (bswapsi2): Force operand 1
to a register also for !TARGET_BSWAP.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr115321.c: New test.
Bootstrapped and regression tested on x86_64-linux-gnu {,m32}.
Uros.
diff --git a/gcc/config
On Mon, Jun 3, 2024 at 5:11 AM liuhongt wrote:
>
> W/o TARGET_SSE4_1, it takes 3 instructions (pand, pandn and por) for
> movdfcc/movsfcc, and could possibly fail cost comparison. Increase
> branch cost could hurt performance for other modes, so specially add
> some preference for floating point i
On Mon, Jun 3, 2024 at 5:02 AM Kewen Lin wrote:
>
> This is to remove macros {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE
> defines in i386 port, and add new port specific hook
> implementation ix86_c_mode_for_floating_type.
>
> gcc/ChangeLog:
>
> * config/i386/i386.cc (ix86_c_mode_for_floating_type):
any_divmod instructions are modelled with invalid RTX:
[(set (match_operand:DI 0 "register_operand" "=c")
(sign_extend:DI (match_operator:SI 3 "divmod_operator"
[(match_operand:DI 1 "register_operand" "a")
(match_operand:DI 2 "register_ope
Introduce *bswaphi2 instruction pattern and enable bswaphi2 expander
also for non-movbe targets. The testcase:
unsigned short bswap8 (unsigned short val)
{
return ((val & 0xff00) >> 8) | ((val & 0xff) << 8);
}
now expands through bswaphi2 named expander.
Rewrite bswaphi_lowpart insn pattern a
Use MOVD/PEXTRD and MOVD/PINSRD insn sequences to move DImode value
between XMM and GPR register sets for SSE4.1 x86_32 targets in order
to avoid spilling the value to stack.
The load from _Atomic location a improves from:
movqa, %xmm0
movq%xmm0, (%esp)
movl(%esp), %eax
On Tue, May 28, 2024 at 12:48 PM liuhongt wrote:
>
> > IMO, there is no need for CONST_INT_P condition, we should also allow
> > symbol_ref, label_ref and const (all allowed by
> > x86_64_immediate_operand predicate), these all decay to an immediate
> > value.
>
> Changed.
>
> Bootstrapped and reg
On Mon, May 27, 2024 at 10:33 AM MayShao wrote:
>
> From: mayshao
>
> Hi all:
> This patch enables -march/-mtune=shijidadao, costs and tunings are set
> according to the characteristics of the processor.
>
> Bootstrapped /regtested X86_64.
>
> Ok for trunk?
OK.
Thanks,
Uros.
> BR
On Tue, May 28, 2024 at 4:48 AM liuhongt wrote:
>
> For MEM, rtx_cost iterates each subrtx, and adds up the costs,
> so for MEM (reg) and MEM (reg + 4), the former costs 5,
> the latter costs 9, it is not accurate for x86. Ideally
> address_cost should be used, but it reduce cost too much.
> So cu
On Thu, May 23, 2024 at 7:53 PM Evgeny Karpov
wrote:
>
>
> Thursday, May 23, 2024 10:35 AM
> Uros Bizjak wrote:
>
> > Richard Sandiford wrote:
> > >
> > > > This looks good to me apart from a couple of very minor comments
> > > > below, bu
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