From: yulong
This patch add the mininal support for zabha extension.
The doc url as follow:
https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc
There are have no amocas.[b|h] instructions, because the zacas extension is not
merged.
gcc/ChangeLog:
*
From: yulong
I test the following rvv intrinsics.
vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t
value, size_t vl) {
return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);}
And I got an error info,that is error: unrecognizable insn:(insn 17 16 18 2
(set
From: yulong
gcc/ChangeLog:
* config/riscv/vector.md: Add float16 attr at sew、vlmul and ratio.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-10.c: Add float16 tuple type case.
* gcc.target/riscv/rvv/base/abi-11.c: Ditto.
*
From: yulong
This patch adds support for the float16 tuple type.
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (valid_type): Enable FP16 tuple.
* config/riscv/riscv-modes.def (RVV_TUPLE_MODES): New macro.
(ADJUST_ALIGNMENT): Ditto.
From: yulong
I find fail of the xtheadcondmov-indirect-rv64.c test case and provide a way to
solve it.
In this patch, I take Kito's advice that I modify the form of the function
bodies.It likes
*[a-x0-9].
gcc/testsuite/ChangeLog:
*
From: yulong
I find fail of the xtheadcondmov-indirect-rv64.c test case and provide the way
to solve it.
In this patch, I modify the check information of the
function(ConEmv_imm_imm_reg and ConNmv_imm_imm_reg) body.
gcc/testsuite/ChangeLog:
*
From: yulong
This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the
definition in types.h that be included by stdio.h.
Thanks to Jeff Law for reviewing the previous version.
gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/fd-4.c:
From: yulong
This patch fixes the problem of the contracts-tmpl-spec2.c running failure.
When run the dejagnu test, I find that the output is inconsistent with that
verified
in the testcase. So I try to modify it, and then it can be passed.
gcc/testsuite/ChangeLog:
*
From: yulong
This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the
definition in types.h that be included by stdio.h.
gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/fd-4.c: delete the definition of mode_t.
---
From: yulong
This patch fixes the problem of the contracts-tmpl-spec2.c running failure.
When run the dejagnu test, I find that the output is inconsistent with that
verified
in the testcase. So I try to modify it, and then it can be passed.
gcc/testsuite/ChangeLog:
*
From: yulong
This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the
definition in stdio.h.
gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/fd-4.c: delete the definition of mode_t.
---
gcc/testsuite/gcc.dg/analyzer/fd-4.c | 5 -
From: yulong
[DO NOT MERGE]
Until 'ZiCond' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream. This commit uses
version 1.0 as in the documentation.
This commit adds support for the latest draft of RISC-V Integer Conditional
(ZiCond)
From: yulong
*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and not frozen RISC-V extension
and not intended to be merged for now.
The intent to submit this patchset is to synchronize with the implementation
of binutils about the ZiCond extension.
This patchset
From: yulong
This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the
definition in stdio.h.There are have a definition about mode_t in the fd-4.c,
but it duplicates the definition in stdio.h.
gcc/testsuite/ChangeLog:
*
From: yulong
This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the
definition in stdio.h.
gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/fd-4.c: delete the definition of mode_t.
---
gcc/testsuite/gcc.dg/analyzer/fd-4.c | 5 -
From: yulong
We changed builtins format about zicbom and zicboz subextensions and modified
test cases.
diff with the previous version:
1.We modified the FUNCTION_TYPE from RISCV_VOID_FTYPE_SI/DI to
RISCV_VOID_FTYPE_VOID_PTR.
2.We added a new RISCV_ATYPE_VOID_PTR in riscv-builtins.cc and a new
From: yulong
We changed builtins format about zicbom and zicboz subextensions and added test
cases.
diff with the previous version:
1.We deleted the RLT mode's second input operand.
2.We modified the type of builtins from RISCV_BUILTIN_DIRECT to
RISCV_BUILTIN_DIRECT_NO_TARGET.
3.We modified
From: yulong
We changed the RTL mode and builtins format about zicbom and zicboz
subextensions.
gcc/ChangeLog:
* config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed
"RISCV_SI(DI)_FTYPE" to "RISCV_SI(DI)_FTPYE_SI(DI)"
* config/riscv/riscv-ftypes.def (0): deleted
From: yulong
This commit adds testcases about CMO instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicbom-1.c: New test.
* gcc.target/riscv/cmo-zicbom-2.c: New test.
* gcc.target/riscv/cmo-zicbop-1.c: New test.
* gcc.target/riscv/cmo-zicbop-2.c: New
From: yulong
This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r
and prefetch.w instructions.
diff with the previous version:
We use unspec_volatile instead of unspec for those cache operations. We use
UNSPECV instead of UNSPEC and move them to unspecv.
gcc/ChangeLog:
From: yulong
This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop
extensions.
* config/riscv/riscv-opts.h (MASK_ZICBOZ): New.
(MASK_ZICBOM): New.
From: yulong
This patchset adds support for three recently ratified RISC-V extensions:
- Zicbom (Cache-Block Management Instructions)
- Zicbop (Cache-Block Prefetch hint instructions)
- Zicboz (Cache-Block Zero Instructions)
Patch 1: Add Zicbom/z/p mininal support
Patch 2: Add Zicbom/z/p
From: yulong
This commit adds testcases about CMO instructions.
diff with the previous two versions:
We change the names of builtin about cbo.clean, cbo.flush, cbo.inval, cbo.zero
and prefetch.i instructions in the testcases.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicbom-1.c:
From: yulong
This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r
and prefetch.w instructions.
diff with the previous two versions:
1.We change the instruction format from "prefetch.i\t%0" to "prefetch.i\t%a0"
about the prefetch.i, cbo.clean, cbo.flush, cbo.inval,
From: yulong
This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop
extensions.
* config/riscv/riscv-opts.h (MASK_ZICBOZ): New.
(MASK_ZICBOM): New.
From: yulong
This patchset adds support for three recently ratified RISC-V extensions:
- Zicbom (Cache-Block Management Instructions)
- Zicbom (Cache-Block Management Instructions)
- Zicboz (Cache-Block Zero Instructions)
Patch 1: Add Zicbom/z/p mininal support
Patch 2: Add Zicbom/z/p
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