PR 67211 is an error that shows up on the GCC 5.x branch when the test case is
compiled with -mcpu=power7 -mtune=power8 -O3. In looking at the code, I noticed
that the code optimized adjancent 64-bit integer/pointers in a structure from
DImode to V2DImode. The compiler optimized these to the vector registers, and
then tried to move a common field used later back to the GPR field. If the cpu
was power8, it would be able to use the direct move instructions, but on power7
those instructions don't exist. The current trunk compiler has dialed back on
the optimization, and it no longer tries to optimize adjacent fields in this
particular case to V2DImode, but it is an issue in the GCC 5 branch.
In debugging the issue, I noticed the -mefficient-unaligned-VSX option was
being set if -mtune=power8 was used, even if the architecture was not a
power8. Efficient unaligned VSX is an architecture feature, and not a tuning
feature. In fixing this to be an architecture feature, it no longer tried to do
the V2DImode optimization because it didn't have fast unaligned support.
I have checked this on a big endian power7 and a little endian power8 system,
using the GCC 5.x patches and the patches for the trunk. There were no
regressions in any of the runs. Is it ok to install these patches on both the
GCC 5.x branch and trunk?
I would like to commit a similar patch for the 4.9 branch as well. Is this ok?
Note, due to rs6000.opt being slightly different between GCC 5.x and trunk,
there are two different patches, one for GCC 5.x and the other for GCC 6.x
(trunk).
[gcc]
2015-08-20 Michael Meissner meiss...@linux.vnet.ibm.com
PR target/67211
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Set
-mefficient-unaligned-vsx on ISA 2.7.
* config/rs6000/rs6000.opt (-mefficient-unaligned-vsx): Convert
option to a masked option.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Rework
logic for -mefficient-unaligned-vsx so that it is set via an arch
ISA option, instead of being set if -mtune=power8 is set. Move
-mefficient-unaligned-vsx and -mallow-movmisalign handling to be
near other default option handling.
[gcc/testsuite]
2015-08-20 Michael Meissner meiss...@linux.vnet.ibm.com
PR target/67211
* g++.dg/pr67211.C: New test.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000-cpus.def
===
--- gcc/config/rs6000/rs6000-cpus.def (revision 226986)
+++ gcc/config/rs6000/rs6000-cpus.def (working copy)
@@ -53,6 +53,7 @@
| OPTION_MASK_P8_VECTOR\
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DIRECT_MOVE \
+| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_HTM \
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC \
@@ -78,6 +79,7 @@
| OPTION_MASK_DFP \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_DLMZB\
+| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FPRND\
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
Index: gcc/config/rs6000/rs6000.opt
===
--- gcc/config/rs6000/rs6000.opt(revision 226986)
+++ gcc/config/rs6000/rs6000.opt(working copy)
@@ -212,7 +212,7 @@ Target Undocumented Var(TARGET_ALLOW_MOV
; Allow/disallow the movmisalign in DF/DI vectors
mefficient-unaligned-vector
-Target Undocumented Report Var(TARGET_EFFICIENT_UNALIGNED_VSX) Init(-1) Save
+Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
; Consider unaligned VSX accesses to be efficient/inefficient
mallow-df-permute
Index: gcc/config/rs6000/rs6000.c
===
--- gcc/config/rs6000/rs6000.c (revision 226986)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -3692,6 +3692,45 @@ rs6000_option_override_internal (bool gl
optimize = 3)
rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
+ /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
+ support. If we only have ISA 2.06 support, and the user did not specify
+ the switch, leave it set to -1 so the movmisalign patterns are enabled,
+ but we don't
