Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
Hello, This commit (211211) causes gcc.target/aarch64/vect-mull.c execution test to FAIL for target aarch64_be-none-elf. (tested using qemu) Christophe. On 3 June 2014 13:08, Marcus Shawcroft marcus.shawcr...@gmail.com wrote: On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote: Missing patch. On Wed, May 28, 2014 at 3:02 PM, bin.cheng bin.ch...@arm.com wrote: Hi, I was surprised that GCC didn't support addressing modes like [REG+OFF]/[REG_REG] for instructions ldr/str in vectorization scenarios. The generated assembly is bad since all address expressions have to be computed outside of memory reference. The root cause is because aarch64 effectively rejects reg-indexing (and const-offset) addressing modes in aarch64_classify_address and miscellaneous simd patterns. By fixing this issue, performance of fp benchmarks can be obviously improved. It can also help vectorized int cases. The patch passes bootstrap and regression test on aarch64/little-endian. It also passes regression test on aarch64/big-endian except for case gcc.target/aarch64/vect-mull.c. I analyzed the failed case and now believe it reveals a latent bug in vectorizer on aarch64/big-endian. The analysis report is posted at https://gcc.gnu.org/ml/gcc-patches/2014-05/msg00182.html. So is it OK? Thanks, bin 2014-05-28 Bin Cheng bin.ch...@arm.com * config/aarch64/aarch64.c (aarch64_classify_address) (aarch64_legitimize_reload_address): Support full addressing modes for vector modes. * config/aarch64/aarch64.md (movmode, movmisalignmode) (*aarch64_simd_movmode, *aarch64_simd_movmode): Relax predicates. OK Thanks /Marcus
Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
On 10 June 2014 15:29, Christophe Lyon christophe.l...@linaro.org wrote: Hello, This commit (211211) causes gcc.target/aarch64/vect-mull.c execution test to FAIL for target aarch64_be-none-elf. (tested using qemu) Yep, that is exactly what Bin said in his original submission.. /Marcus On Wed, May 28, 2014 at 3:02 PM, bin.cheng bin.ch...@arm.com wrote: The patch passes bootstrap and regression test on aarch64/little-endian. It also passes regression test on aarch64/big-endian except for case gcc.target/aarch64/vect-mull.c. I analyzed the failed case and now believe it reveals a latent bug in vectorizer on aarch64/big-endian. The analysis report is posted at https://gcc.gnu.org/ml/gcc-patches/2014-05/msg00182.html.
Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
On Wed, Jun 4, 2014 at 7:18 PM, Charles Baylis charles.bay...@linaro.org wrote: On 4 June 2014 10:06, Charles Baylis charles.bay...@linaro.org wrote: On 4 June 2014 03:11, Bin.Cheng amker.ch...@gmail.com wrote: Yes, If there is a PR, I can evaluate how this can help and ask release maintainer for approval. I'll reduce the test case and create one shortly I have created PR61411 with a reduced test case. Hi Charles, According to comments at https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61411, I think it's a latent bug in LRA, which shouldn't be covered by this patch. Thanks, bin -- Best Regards.
Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
On 4 June 2014 03:11, Bin.Cheng amker.ch...@gmail.com wrote: Yes, If there is a PR, I can evaluate how this can help and ask release maintainer for approval. I'll reduce the test case and create one shortly
Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
On 4 June 2014 10:06, Charles Baylis charles.bay...@linaro.org wrote: On 4 June 2014 03:11, Bin.Cheng amker.ch...@gmail.com wrote: Yes, If there is a PR, I can evaluate how this can help and ask release maintainer for approval. I'll reduce the test case and create one shortly I have created PR61411 with a reduced test case.
Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote: Missing patch. On Wed, May 28, 2014 at 3:02 PM, bin.cheng bin.ch...@arm.com wrote: Hi, I was surprised that GCC didn't support addressing modes like [REG+OFF]/[REG_REG] for instructions ldr/str in vectorization scenarios. The generated assembly is bad since all address expressions have to be computed outside of memory reference. The root cause is because aarch64 effectively rejects reg-indexing (and const-offset) addressing modes in aarch64_classify_address and miscellaneous simd patterns. By fixing this issue, performance of fp benchmarks can be obviously improved. It can also help vectorized int cases. The patch passes bootstrap and regression test on aarch64/little-endian. It also passes regression test on aarch64/big-endian except for case gcc.target/aarch64/vect-mull.c. I analyzed the failed case and now believe it reveals a latent bug in vectorizer on aarch64/big-endian. The analysis report is posted at https://gcc.gnu.org/ml/gcc-patches/2014-05/msg00182.html. So is it OK? Thanks, bin 2014-05-28 Bin Cheng bin.ch...@arm.com * config/aarch64/aarch64.c (aarch64_classify_address) (aarch64_legitimize_reload_address): Support full addressing modes for vector modes. * config/aarch64/aarch64.md (movmode, movmisalignmode) (*aarch64_simd_movmode, *aarch64_simd_movmode): Relax predicates. OK Thanks /Marcus
Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
On 3 June 2014 12:08, Marcus Shawcroft marcus.shawcr...@gmail.com wrote: On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote: So is it OK? 2014-05-28 Bin Cheng bin.ch...@arm.com * config/aarch64/aarch64.c (aarch64_classify_address) (aarch64_legitimize_reload_address): Support full addressing modes for vector modes. * config/aarch64/aarch64.md (movmode, movmisalignmode) (*aarch64_simd_movmode, *aarch64_simd_movmode): Relax predicates. OK Thanks /Marcus Hi Bin, This resolves an ICE in 4.9 in Neon intrinsics code, so I'd like to see it backported to the branch too, please. Thanks Charles
Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
On 3 Jun 2014, at 18:08, Charles Baylis charles.bay...@linaro.org wrote: On 3 June 2014 12:08, Marcus Shawcroft marcus.shawcr...@gmail.com wrote: On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote: So is it OK? 2014-05-28 Bin Cheng bin.ch...@arm.com * config/aarch64/aarch64.c (aarch64_classify_address) (aarch64_legitimize_reload_address): Support full addressing modes for vector modes. * config/aarch64/aarch64.md (movmode, movmisalignmode) (*aarch64_simd_movmode, *aarch64_simd_movmode): Relax predicates. OK Thanks /Marcus Hi Bin, This resolves an ICE in 4.9 in Neon intrinsics code, so I'd like to see it backported to the branch too, please. Thanks Charles Charles, Have you got a PR/bugzilla no for the ICE in question please?
Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
On Wed, Jun 4, 2014 at 1:50 AM, Marcus Shawcroft marcus.shawcr...@gmail.com wrote: On 3 Jun 2014, at 18:08, Charles Baylis charles.bay...@linaro.org wrote: On 3 June 2014 12:08, Marcus Shawcroft marcus.shawcr...@gmail.com wrote: On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote: So is it OK? 2014-05-28 Bin Cheng bin.ch...@arm.com * config/aarch64/aarch64.c (aarch64_classify_address) (aarch64_legitimize_reload_address): Support full addressing modes for vector modes. * config/aarch64/aarch64.md (movmode, movmisalignmode) (*aarch64_simd_movmode, *aarch64_simd_movmode): Relax predicates. OK Thanks /Marcus Hi Bin, This resolves an ICE in 4.9 in Neon intrinsics code, so I'd like to see it backported to the branch too, please. Thanks Charles Charles, Have you got a PR/bugzilla no for the ICE in question please? Yes, If there is a PR, I can evaluate how this can help and ask release maintainer for approval. Thanks, bin -- Best Regards.
[PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
Hi, I was surprised that GCC didn't support addressing modes like [REG+OFF]/[REG_REG] for instructions ldr/str in vectorization scenarios. The generated assembly is bad since all address expressions have to be computed outside of memory reference. The root cause is because aarch64 effectively rejects reg-indexing (and const-offset) addressing modes in aarch64_classify_address and miscellaneous simd patterns. By fixing this issue, performance of fp benchmarks can be obviously improved. It can also help vectorized int cases. The patch passes bootstrap and regression test on aarch64/little-endian. It also passes regression test on aarch64/big-endian except for case gcc.target/aarch64/vect-mull.c. I analyzed the failed case and now believe it reveals a latent bug in vectorizer on aarch64/big-endian. The analysis report is posted at https://gcc.gnu.org/ml/gcc-patches/2014-05/msg00182.html. So is it OK? Thanks, bin 2014-05-28 Bin Cheng bin.ch...@arm.com * config/aarch64/aarch64.c (aarch64_classify_address) (aarch64_legitimize_reload_address): Support full addressing modes for vector modes. * config/aarch64/aarch64.md (movmode, movmisalignmode) (*aarch64_simd_movmode, *aarch64_simd_movmode): Relax predicates.
Re: [PATCH][AARCH64]Support full addressing modes for ldr/str in vectorization scenarios
Missing patch.
On Wed, May 28, 2014 at 3:02 PM, bin.cheng bin.ch...@arm.com wrote:
Hi,
I was surprised that GCC didn't support addressing modes like
[REG+OFF]/[REG_REG] for instructions ldr/str in vectorization scenarios.
The generated assembly is bad since all address expressions have to be
computed outside of memory reference. The root cause is because aarch64
effectively rejects reg-indexing (and const-offset) addressing modes in
aarch64_classify_address and miscellaneous simd patterns.
By fixing this issue, performance of fp benchmarks can be obviously
improved. It can also help vectorized int cases.
The patch passes bootstrap and regression test on aarch64/little-endian. It
also passes regression test on aarch64/big-endian except for case
gcc.target/aarch64/vect-mull.c. I analyzed the failed case and now
believe it reveals a latent bug in vectorizer on aarch64/big-endian. The
analysis report is posted at
https://gcc.gnu.org/ml/gcc-patches/2014-05/msg00182.html.
So is it OK?
Thanks,
bin
2014-05-28 Bin Cheng bin.ch...@arm.com
* config/aarch64/aarch64.c (aarch64_classify_address)
(aarch64_legitimize_reload_address): Support full addressing modes
for vector modes.
* config/aarch64/aarch64.md (movmode, movmisalignmode)
(*aarch64_simd_movmode, *aarch64_simd_movmode): Relax
predicates.
--
Best Regards.
Index: gcc/config/aarch64/aarch64-simd.md
===
--- gcc/config/aarch64/aarch64-simd.md (revision 210319)
+++ gcc/config/aarch64/aarch64-simd.md (working copy)
@@ -19,8 +19,8 @@
;; http://www.gnu.org/licenses/.
(define_expand movmode
- [(set (match_operand:VALL 0 aarch64_simd_nonimmediate_operand )
- (match_operand:VALL 1 aarch64_simd_general_operand ))]
+ [(set (match_operand:VALL 0 nonimmediate_operand )
+ (match_operand:VALL 1 general_operand ))]
TARGET_SIMD
if (GET_CODE (operands[0]) == MEM)
@@ -29,8 +29,8 @@
)
(define_expand movmisalignmode
- [(set (match_operand:VALL 0 aarch64_simd_nonimmediate_operand )
-(match_operand:VALL 1 aarch64_simd_general_operand ))]
+ [(set (match_operand:VALL 0 nonimmediate_operand )
+(match_operand:VALL 1 general_operand ))]
TARGET_SIMD
{
/* This pattern is not permitted to fail during expansion: if both arguments
@@ -91,9 +91,9 @@
)
(define_insn *aarch64_simd_movmode
- [(set (match_operand:VD 0 aarch64_simd_nonimmediate_operand
+ [(set (match_operand:VD 0 nonimmediate_operand
=w, m, w, ?r, ?w, ?r, w)
- (match_operand:VD 1 aarch64_simd_general_operand
+ (match_operand:VD 1 general_operand
m, w, w, w, r, r, Dn))]
TARGET_SIMD
(register_operand (operands[0], MODEmode)
@@ -119,9 +119,9 @@
)
(define_insn *aarch64_simd_movmode
- [(set (match_operand:VQ 0 aarch64_simd_nonimmediate_operand
+ [(set (match_operand:VQ 0 nonimmediate_operand
=w, m, w, ?r, ?w, ?r, w)
- (match_operand:VQ 1 aarch64_simd_general_operand
+ (match_operand:VQ 1 general_operand
m, w, w, w, r, r, Dn))]
TARGET_SIMD
(register_operand (operands[0], MODEmode)
Index: gcc/config/aarch64/aarch64.c
===
--- gcc/config/aarch64/aarch64.c(revision 210319)
+++ gcc/config/aarch64/aarch64.c(working copy)
@@ -3075,11 +3075,11 @@ aarch64_classify_address (struct aarch64_address_i
enum rtx_code code = GET_CODE (x);
rtx op0, op1;
bool allow_reg_index_p =
-outer_code != PARALLEL GET_MODE_SIZE(mode) != 16;
-
+outer_code != PARALLEL (GET_MODE_SIZE (mode) != 16
+ || aarch64_vector_mode_supported_p (mode));
/* Don't support anything other than POST_INC or REG addressing for
AdvSIMD. */
- if (aarch64_vector_mode_p (mode)
+ if (aarch64_vect_struct_mode_p (mode)
(code != POST_INC code != REG))
return false;
@@ -4010,7 +4010,7 @@ aarch64_legitimize_reload_address (rtx *x_p,
rtx x = *x_p;
/* Do not allow mem (plus (reg, const)) if vector mode. */
- if (aarch64_vector_mode_p (mode)
+ if (aarch64_vect_struct_mode_p (mode)
GET_CODE (x) == PLUS
REG_P (XEXP (x, 0))
CONST_INT_P (XEXP (x, 1)))
