The Advanced SIMD and SVE permute patterns both split the permute
operation into a base name and a hilo suffix. That works well, but it
means that for "@" patterns, we need to pass the permute code twice,
once for the base name and once for the suffix.
Having a unified name avoids that and also makes the definitions
slightly simpler.
Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf.
OK to install?
Richard
2019-08-07 Richard Sandiford
gcc/
* config/aarch64/iterators.md (perm_insn): Include the "1"/"2" suffix.
(perm_hilo): Remove UNSPEC_ZIP*, UNSEPC_TRN* and UNSPEC_UZP*.
* config/aarch64/aarch64-simd.md
(aarch64_): Rename to..
(aarch64_): ...this and remove perm_hilo
from the asm template.
* config/aarch64/aarch64-sve.md
(aarch64_): Rename to..
(aarch64_): ...this and remove perm_hilo
from the asm template.
(aarch64_): Rename to..
(aarch64_): ...this and remove perm_hilo
from the asm template.
* config/aarch64/aarch64-simd-builtins.def: Update comment.
Index: gcc/config/aarch64/iterators.md
===
--- gcc/config/aarch64/iterators.md 2019-08-07 20:05:39.029879208 +0100
+++ gcc/config/aarch64/iterators.md 2019-08-07 20:22:04.962550985 +0100
@@ -1888,18 +1888,15 @@ (define_int_attr pauth_hint_num [(UNSPEC
(UNSPEC_AUTIA1716 "12")
(UNSPEC_AUTIB1716 "14")])
-(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
- (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
- (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
+(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2")
+ (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2")
+ (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2")])
; op code for REV instructions (size within which elements are reversed).
(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
(UNSPEC_REV16 "16")])
-(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
- (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
- (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")
- (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
+(define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
(UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
;; Return true if the associated optab refers to the high-numbered lanes,
Index: gcc/config/aarch64/aarch64-simd.md
===
--- gcc/config/aarch64/aarch64-simd.md 2019-07-29 09:39:46.666190099 +0100
+++ gcc/config/aarch64/aarch64-simd.md 2019-08-07 20:22:04.958551015 +0100
@@ -5781,13 +5781,13 @@ (define_insn_and_split "aarch64_combinev
;; This instruction's pattern is generated directly by
;; aarch64_expand_vec_perm_const, so any changes to the pattern would
;; need corresponding changes there.
-(define_insn "aarch64_"
+(define_insn "aarch64_"
[(set (match_operand:VALL_F16 0 "register_operand" "=w")
(unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "w")
(match_operand:VALL_F16 2 "register_operand" "w")]
PERMUTE))]
"TARGET_SIMD"
- "\\t%0., %1., %2."
+ "\\t%0., %1., %2."
[(set_attr "type" "neon_permute")]
)
Index: gcc/config/aarch64/aarch64-sve.md
===
--- gcc/config/aarch64/aarch64-sve.md 2019-08-07 20:12:11.454961437 +0100
+++ gcc/config/aarch64/aarch64-sve.md 2019-08-07 20:22:04.958551015 +0100
@@ -3356,13 +3356,13 @@ (define_insn "*aarch64_sve_rev16vnx16qi"
;; Permutes that take half the elements from one vector and half the
;; elements from the other.
-(define_insn "aarch64_sve_"
+(define_insn "aarch64_sve_"
[(set (match_operand:SVE_ALL 0 "register_operand" "=w")
(unspec:SVE_ALL [(match_operand:SVE_ALL 1 "register_operand" "w")
(match_operand:SVE_ALL 2 "register_operand" "w")]
PERMUTE))]
"TARGET_SVE"
- "\t%0., %1., %2."
+ "\t%0., %1., %2."
)
;; Concatenate two vectors and extract a subvector. Note that the
@@ -3395,13 +3395,13 @@ (define_insn "*aarch64_sve_ext"
;; Permutes that take half the elements from one vector and half the
;; elements from the other.
-(define_insn "*aarch64_sve_"
+(define_insn "*aarch64_sve_"
[(set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
(unspec:PRED_ALL [(match_operand:PRED_ALL 1 "register_operand" "Upa")
(match_operand:PRED_ALL 2 "register_operand" "Upa")]
PERMUTE))]
"TARGET_SVE"
- "\t%0., %1., %2."
+ "\t%0., %1., %2."
)
;;
