On Tue, May 22, 2018 at 08:13:22AM -0500, Kyrill Tkachov wrote:
> [sending on behalf of Jackson Woodruff]
>
> Hi all,
>
> This patch merges loads and stores from D-registers that are of different
> modes.
>
> Code like this:
>
> typedef int __attribute__((vector_size(8))) vec;
>
[sending on behalf of Jackson Woodruff]
Hi all,
This patch merges loads and stores from D-registers that are of different modes.
Code like this:
typedef int __attribute__((vector_size(8))) vec;
struct pair
{
vec v;
double d;
}
Now generates a store pair
On 09/12/2017 07:32 PM, Richard Sandiford wrote:
Thanks for doing this, looks good to me FWIW. I was just wondering:
Jackson Woodruff writes:
@@ -14712,6 +14712,11 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool
load,
if (!rtx_equal_p (base_1,
Thanks for doing this, looks good to me FWIW. I was just wondering:
Jackson Woodruff writes:
> @@ -14712,6 +14712,11 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool
> load,
>if (!rtx_equal_p (base_1, base_2))
> return false;
>
> + /* Check that
Hi all,
This patch merges loads and stores from D-registers that are of
different modes.
Code like this:
typedef int __attribute__((vector_size(8))) vec;
struct pair
{
vec v;
double d;
}
void
assign (struct pair *p, vec v)
{
p->v = v;
p->d