Hi, This patch documents the following options for Arm Cortex-M55 CPU under -mcpu= list.
+nomve.fp (disables MVE single precision floating point instructions) +nomve (disables MVE integer and single precision floating point instructions) +nodsp (disables dsp, MVE integer and single precision floating point instructions) +nofp (disables floating point instructions) Committed as obvious to master. Regards, Srinath. gcc/ChangeLog: 2022-08-12 Srinath Parvathaneni <srinath.parvathan...@arm.com> * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55 options. ############### Attachment also inlined for ease of reply ############### diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3b529c420c94f70519abfd79acd90d216203c8a7..b264ae28fe6dbe5c298f3b91e4ce3fd8e6a0fb7f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21638,14 +21638,25 @@ The following extension options are common to the listed CPUs: @table @samp @item +nodsp -Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}. +Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p} +and @samp{cortex-m55}. Also disable the M-Profile Vector Extension (MVE) +integer and single precision floating-point instructions on @samp{cortex-m55}. + +@item +nomve +Disable the M-Profile Vector Extension (MVE) integer and single precision +floating-point instructions on @samp{cortex-m55}. + +@item +nomve.fp +Disable the M-Profile Vector Extension (MVE) single precision floating-point +instructions on @samp{cortex-m55}. @item +nofp Disables the floating-point instructions on @samp{arm9e}, @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s}, @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, -@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33} and @samp{cortex-m35p}. +@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p} +and @samp{cortex-m55}. Disables the floating-point and SIMD instructions on @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3b529c420c94f70519abfd79acd90d216203c8a7..b264ae28fe6dbe5c298f3b91e4ce3fd8e6a0fb7f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21638,14 +21638,25 @@ The following extension options are common to the listed CPUs: @table @samp @item +nodsp -Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}. +Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p} +and @samp{cortex-m55}. Also disable the M-Profile Vector Extension (MVE) +integer and single precision floating-point instructions on @samp{cortex-m55}. + +@item +nomve +Disable the M-Profile Vector Extension (MVE) integer and single precision +floating-point instructions on @samp{cortex-m55}. + +@item +nomve.fp +Disable the M-Profile Vector Extension (MVE) single precision floating-point +instructions on @samp{cortex-m55}. @item +nofp Disables the floating-point instructions on @samp{arm9e}, @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s}, @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, -@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33} and @samp{cortex-m35p}. +@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p} +and @samp{cortex-m55}. Disables the floating-point and SIMD instructions on @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},