Hello,
This commit (211211) causes gcc.target/aarch64/vect-mull.c execution
test to FAIL for target aarch64_be-none-elf.
(tested using qemu)
Christophe.
On 3 June 2014 13:08, Marcus Shawcroft marcus.shawcr...@gmail.com wrote:
On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote:
On 10 June 2014 15:29, Christophe Lyon christophe.l...@linaro.org wrote:
Hello,
This commit (211211) causes gcc.target/aarch64/vect-mull.c execution
test to FAIL for target aarch64_be-none-elf.
(tested using qemu)
Yep, that is exactly what Bin said in his original submission..
/Marcus
On
On Wed, Jun 4, 2014 at 7:18 PM, Charles Baylis
charles.bay...@linaro.org wrote:
On 4 June 2014 10:06, Charles Baylis charles.bay...@linaro.org wrote:
On 4 June 2014 03:11, Bin.Cheng amker.ch...@gmail.com wrote:
Yes, If there is a PR, I can evaluate how this can help and ask
release maintainer
On 4 June 2014 03:11, Bin.Cheng amker.ch...@gmail.com wrote:
Yes, If there is a PR, I can evaluate how this can help and ask
release maintainer for approval.
I'll reduce the test case and create one shortly
On 4 June 2014 10:06, Charles Baylis charles.bay...@linaro.org wrote:
On 4 June 2014 03:11, Bin.Cheng amker.ch...@gmail.com wrote:
Yes, If there is a PR, I can evaluate how this can help and ask
release maintainer for approval.
I'll reduce the test case and create one shortly
I have created
On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote:
Missing patch.
On Wed, May 28, 2014 at 3:02 PM, bin.cheng bin.ch...@arm.com wrote:
Hi,
I was surprised that GCC didn't support addressing modes like
[REG+OFF]/[REG_REG] for instructions ldr/str in vectorization scenarios.
The
On 3 June 2014 12:08, Marcus Shawcroft marcus.shawcr...@gmail.com wrote:
On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote:
So is it OK?
2014-05-28 Bin Cheng bin.ch...@arm.com
* config/aarch64/aarch64.c (aarch64_classify_address)
On 3 Jun 2014, at 18:08, Charles Baylis charles.bay...@linaro.org wrote:
On 3 June 2014 12:08, Marcus Shawcroft marcus.shawcr...@gmail.com wrote:
On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote:
So is it OK?
2014-05-28 Bin Cheng bin.ch...@arm.com
*
On Wed, Jun 4, 2014 at 1:50 AM, Marcus Shawcroft
marcus.shawcr...@gmail.com wrote:
On 3 Jun 2014, at 18:08, Charles Baylis charles.bay...@linaro.org wrote:
On 3 June 2014 12:08, Marcus Shawcroft marcus.shawcr...@gmail.com wrote:
On 28 May 2014 08:30, Bin.Cheng amker.ch...@gmail.com wrote:
Hi,
I was surprised that GCC didn't support addressing modes like
[REG+OFF]/[REG_REG] for instructions ldr/str in vectorization scenarios.
The generated assembly is bad since all address expressions have to be
computed outside of memory reference. The root cause is because aarch64
effectively
Missing patch.
On Wed, May 28, 2014 at 3:02 PM, bin.cheng bin.ch...@arm.com wrote:
Hi,
I was surprised that GCC didn't support addressing modes like
[REG+OFF]/[REG_REG] for instructions ldr/str in vectorization scenarios.
The generated assembly is bad since all address expressions have to be
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