On Mon, Jul 27, 2015 at 03:38:55PM +0100, Wilco Dijkstra wrote:
This is basically the same as the shl version but for the shr patterns.
Various instructions are supported as integer operations as well as SIMD on
AArch64. When
register pressure is high, lra-constraints inserts spill code
This is basically the same as the shl version but for the shr patterns.
Various instructions are supported as integer operations as well as SIMD on
AArch64. When
register pressure is high, lra-constraints inserts spill code without taking
the allocation
class into account, and basically chooses
