For thumb1 use move + add instructions for immediate move [256-510].
Following is a complete range if combine an imm mov with listed
instructions. Among them, lsls and neg have already been implemented. The
only missing opportunity is add, in which I enabled in this patch. Others
are replicated with lsls or neg.
1. Result imm range with 16bit movs
InsnResult imm with movs
lsls[0x1-0xff] shifted by 1-31
add [256, 510]
neg [-255, 0]
rev [0x100-0xff00] step 0x100
rev16 [0x100-0xff00] step 0x100
revsh [0x1-0xff] step 0x1
rsb [-255, 0]
mvn [-255, 0]
sub [-255, 0]
sxtb[-255, 0]
ChangeLog:
* config/arm/constraints.md (Pe): New constraint.
* config/arm/arm.md: New split for imm 256-510.
Testcase:
* gcc.target/arm/thumb1-imm.c: New testcase.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 4f6d965..c86d42e 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -5635,6 +5635,21 @@
}
)
+;; For thumb1 split imm move [256-510] into mov [1-255] and add #255
+(define_split
+ [(set (match_operand:SI 0 register_operand )
+ (match_operand:SI 1 const_int_operand ))]
+ TARGET_THUMB1 satisfies_constraint_Pe (operands[1])
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))]
+
+ {
+operands[1] = GEN_INT (INTVAL (operands[1]) - 255);
+operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) :
operands[0];
+operands[3] = GEN_INT (255);
+ }
+)
+
;; When generating pic, we need to load the symbol offset into a register.
;; So that the optimizer does not confuse this with a normal symbol load
;; we use an unspec. The offset will be loaded from a constant pool entry,
diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index 3ff968b..6b59e87 100644
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -30,7 +30,7 @@
;; The following multi-letter normal constraints have been used:
;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
-;; in Thumb-1 state: Pa, Pb, Pc, Pd
+;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
;; The following memory constraints have been used:
@@ -172,6 +172,11 @@
(and (match_code const_int)
(match_test TARGET_THUMB1 ival = 0 ival = 7)))
+(define_constraint Pe
+ @internal In Thumb-1 state a constant in the range 256 to +510
+ (and (match_code const_int)
+ (match_test TARGET_THUMB1 ival = 256 ival = 510)))
+
(define_constraint Ps
@internal In Thumb-2 state a constant in the range -255 to +255
(and (match_code const_int)
diff --git a/gcc/testsuite/gcc.target/arm/thumb1-imm.c
b/gcc/testsuite/gcc.target/arm/thumb1-imm.c
new file mode 100644
index 000..b47c08c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/thumb1-imm.c
@@ -0,0 +1,10 @@
+/* Check for thumb1 imm [255-510] moves. */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+int f()
+{
+ return 257;
+}
+
+/* { dg-final { scan-assembler-not ldr } } */
+
