Re: [PATCH] Cleanup: Replace UNSPEC_COPYSIGN with copysign RTL
On Fri, Sep 29, 2023 at 02:09:12PM -0400, Michael Meissner wrote: > * config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete. > (copysign3_fcpsg): Use copysign RTL instead of UNSPEC. (typo, it is _fcpsgn) Nice to see unnecessary unspecs going away :-) Segher
Re: [PATCH] Cleanup: Replace UNSPEC_COPYSIGN with copysign RTL
On Fri, Sep 29, 2023 at 2:09 PM Michael Meissner
wrote:
> When I first implemented COPYSIGN support in the power7 days, we did not
> have a
> copysign RTL insn, so I had to use UNSPEC to represent the copysign
> instruction. This patch removes those UNSPECs, and it uses the native RTL
> copysign insn.
>
> I have tested this on both big endian and little endian PowerPC server
> systems,
> and there were no regressions. Can I check this into the master branch?
> Since
> it is just a clean-up, I don't see the need to back port it, but it is
> simple
> to do the back port if desired.
>
> 2023-09-29 Michael Meissner
>
> gcc/
>
> * config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete.
> (copysign3_fcpsg): Use copysign RTL instead of UNSPEC.
> (copysign3_hard): Likewise.
> (copysign3_soft): Likewise.
> * config/rs6000/vector.md (vector_copysign3): Use copysign
> RTL
> instead of UNSPEC.
> * config/rs6000/vsx.md (vsx_copysign3): Use copysign RTL
> instead
> of UNSPEC.
> ---
> gcc/config/rs6000/rs6000.md | 20
> gcc/config/rs6000/vector.md | 4 ++--
> gcc/config/rs6000/vsx.md| 7 +++
> 3 files changed, 13 insertions(+), 18 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 7b583d7a69a..1b6b6cb5bbe 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -108,7 +108,6 @@ (define_c_enum "unspec"
> UNSPEC_TOCREL
> UNSPEC_MACHOPIC_OFFSET
> UNSPEC_BPERM
> - UNSPEC_COPYSIGN
> UNSPEC_PARITY
> UNSPEC_CMPB
> UNSPEC_FCTIW
> @@ -5383,9 +5382,8 @@ (define_expand "copysign3"
> ;; compiler from optimizing -0.0
>
The comment above the define_insn refers to UNSPEC instead of if-then-else
because of -0.0.
Please remove or update the comment because the pattern no longer uses
UNSPEC.
The rest of the patch is okay with that change.
Thanks, David
> (define_insn "copysign3_fcpsgn"
>[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
> - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
> - (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")]
> -UNSPEC_COPYSIGN))]
> + (copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
> + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
>"TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode))"
>"@
> fcpsgn %0,%2,%1
> @@ -14984,10 +14982,9 @@ (define_expand "copysign3"
>
> (define_insn "copysign3_hard"
>[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
> - (unspec:IEEE128
> -[(match_operand:IEEE128 1 "altivec_register_operand" "v")
> - (match_operand:IEEE128 2 "altivec_register_operand" "v")]
> -UNSPEC_COPYSIGN))]
> + (copysign:IEEE128
> +(match_operand:IEEE128 1 "altivec_register_operand" "v")
> +(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
>"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)"
> "xscpsgnqp %0,%2,%1"
>[(set_attr "type" "vecmove")
> @@ -14995,10 +14992,9 @@ (define_insn "copysign3_hard"
>
> (define_insn "copysign3_soft"
>[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
> - (unspec:IEEE128
> -[(match_operand:IEEE128 1 "altivec_register_operand" "v")
> - (match_operand:IEEE128 2 "altivec_register_operand" "v")]
> -UNSPEC_COPYSIGN))
> + (copysign:IEEE128
> +(match_operand:IEEE128 1 "altivec_register_operand" "v")
> +(match_operand:IEEE128 2 "altivec_register_operand" "v")))
> (clobber (match_scratch:IEEE128 3 "="))]
>"!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)"
> "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
> diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
> index 1ae04c8e0a8..f4fc620b653 100644
> --- a/gcc/config/rs6000/vector.md
> +++ b/gcc/config/rs6000/vector.md
> @@ -332,8 +332,8 @@ (define_expand "vector_btrunc2"
>
> (define_expand "vector_copysign3"
>[(set (match_operand:VEC_F 0 "vfloat_operand")
> - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")
> - (match_operand:VEC_F 2 "vfloat_operand")]
> UNSPEC_COPYSIGN))]
> + (copysign:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
> + (match_operand:VEC_F 2 "vfloat_operand")))]
>"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
> {
>if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 4de41e78d51..f3b40229094 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -2233,10 +2233,9 @@ (define_insn "*vsx_ge__p"
> ;; Copy sign
> (define_insn "vsx_copysign3"
>[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
> - (unspec:VSX_F
> -[(match_operand:VSX_F 1 "vsx_register_operand" "wa")
> - (match_operand:VSX_F 2
[PATCH] Cleanup: Replace UNSPEC_COPYSIGN with copysign RTL
When I first implemented COPYSIGN support in the power7 days, we did not have a
copysign RTL insn, so I had to use UNSPEC to represent the copysign
instruction. This patch removes those UNSPECs, and it uses the native RTL
copysign insn.
I have tested this on both big endian and little endian PowerPC server systems,
and there were no regressions. Can I check this into the master branch? Since
it is just a clean-up, I don't see the need to back port it, but it is simple
to do the back port if desired.
2023-09-29 Michael Meissner
gcc/
* config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete.
(copysign3_fcpsg): Use copysign RTL instead of UNSPEC.
(copysign3_hard): Likewise.
(copysign3_soft): Likewise.
* config/rs6000/vector.md (vector_copysign3): Use copysign RTL
instead of UNSPEC.
* config/rs6000/vsx.md (vsx_copysign3): Use copysign RTL instead
of UNSPEC.
---
gcc/config/rs6000/rs6000.md | 20
gcc/config/rs6000/vector.md | 4 ++--
gcc/config/rs6000/vsx.md| 7 +++
3 files changed, 13 insertions(+), 18 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7b583d7a69a..1b6b6cb5bbe 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -108,7 +108,6 @@ (define_c_enum "unspec"
UNSPEC_TOCREL
UNSPEC_MACHOPIC_OFFSET
UNSPEC_BPERM
- UNSPEC_COPYSIGN
UNSPEC_PARITY
UNSPEC_CMPB
UNSPEC_FCTIW
@@ -5383,9 +5382,8 @@ (define_expand "copysign3"
;; compiler from optimizing -0.0
(define_insn "copysign3_fcpsgn"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
- (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")]
-UNSPEC_COPYSIGN))]
+ (copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode))"
"@
fcpsgn %0,%2,%1
@@ -14984,10 +14982,9 @@ (define_expand "copysign3"
(define_insn "copysign3_hard"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (unspec:IEEE128
-[(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
-UNSPEC_COPYSIGN))]
+ (copysign:IEEE128
+(match_operand:IEEE128 1 "altivec_register_operand" "v")
+(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)"
"xscpsgnqp %0,%2,%1"
[(set_attr "type" "vecmove")
@@ -14995,10 +14992,9 @@ (define_insn "copysign3_hard"
(define_insn "copysign3_soft"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (unspec:IEEE128
-[(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
-UNSPEC_COPYSIGN))
+ (copysign:IEEE128
+(match_operand:IEEE128 1 "altivec_register_operand" "v")
+(match_operand:IEEE128 2 "altivec_register_operand" "v")))
(clobber (match_scratch:IEEE128 3 "="))]
"!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)"
"xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 1ae04c8e0a8..f4fc620b653 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -332,8 +332,8 @@ (define_expand "vector_btrunc2"
(define_expand "vector_copysign3"
[(set (match_operand:VEC_F 0 "vfloat_operand")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")
- (match_operand:VEC_F 2 "vfloat_operand")]
UNSPEC_COPYSIGN))]
+ (copysign:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
{
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4de41e78d51..f3b40229094 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2233,10 +2233,9 @@ (define_insn "*vsx_ge__p"
;; Copy sign
(define_insn "vsx_copysign3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
- (unspec:VSX_F
-[(match_operand:VSX_F 1 "vsx_register_operand" "wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "wa")]
-UNSPEC_COPYSIGN))]
+ (copysign:VSX_F
+(match_operand:VSX_F 1 "vsx_register_operand" "wa")
+(match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (mode)"
"xvcpsgnp %x0,%x2,%x1"
[(set_attr "type" "")])
--
2.41.0
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
