This patch fix incorrect mode tieable between DI and V2SI which cause ICE
in RA.
PR target/111296
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_modes_tieable_p): Fix bug.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr111296.C: New test.
---
gcc/config/riscv/riscv.cc | 7 +++
.../g++.target/riscv/rvv/base/pr111296.C | 18 ++
2 files changed, 25 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 228515acc1f..2c0c4c2f3ae 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7648,6 +7648,13 @@ riscv_hard_regno_mode_ok (unsigned int regno,
machine_mode mode)
static bool
riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
+ /* We don't allow different REG_CLASS modes tieable since it
+ will cause ICE in register allocation (RA).
+ E.g. V2SI and DI are not tieable. */
+ if (riscv_v_ext_mode_p (mode1) && !riscv_v_ext_mode_p (mode2))
+return false;
+ else if (riscv_v_ext_mode_p (mode2) && !riscv_v_ext_mode_p (mode1))
+return false;
return (mode1 == mode2
|| !(GET_MODE_CLASS (mode1) == MODE_FLOAT
&& GET_MODE_CLASS (mode2) == MODE_FLOAT));
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C
b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C
new file mode 100644
index 000..6eb14fd83a8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize
--param=riscv-autovec-preference=scalable" } */
+
+struct a
+{
+ int b;
+ int c;
+};
+int d;
+a
+e ()
+{
+ a f;
+ int g = d - 1, h = d / 2 - 1;
+ f.b = g;
+ f.c = h;
+ return f;
+}
--
2.36.3
