Re: [PATCH 00/13] [RFC] Support Intel APX EGPR
Richard Biener via Gcc-patches 于2023年8月31日周四 17:21写道： > > On Thu, Aug 31, 2023 at 10:22 AM Hongyu Wang via Gcc-patches > wrote: > > > > Intel Advanced performance extension (APX) has been released in [1]. > > It contains several extensions such as extended 16 general purpose registers > > (EGPRs), push2/pop2, new data destination (NDD), conditional compare > > (CCMP/CTEST) combined with suppress flags write version of common > > instructions > > (NF). This RFC focused on EGPR implementation in GCC. > > > > APX introduces a REX2 prefix to help represent EGPR for several legacy/SSE > > instructions. For the remaining ones, it promotes some of them using evex > > prefix for EGPR. The main issue in APX is that not all legacy/sse/vex > > instructions support EGPR. For example, instructions in legacy opcode map2/3 > > cannot use REX2 prefix since there is only 1bit in REX2 to indicate map0/1 > > instructions, e.g., pinsrd. Also, for most vector extensions, EGPR is > > supported > > in their evex forms but not vex forms, which means the mnemonics with no > > evex > > forms also cannot use EGPR, e.g., vphaddw. > > > > Such limitation brings some challenge with current GCC infrastructure. > > Generally, we use constraints to guide register allocation behavior. For > > register operand, it is easy to add a new constraint to certain insn and > > limit > > it to legacy or REX registers. But for memory operand, if we only use > > constraint to limit base/index register choice, reload has no backoff when > > process_address allocates any egprs to base/index reg, and then any > > post-reload > > pass would get ICE from the constraint. > > How realistic would it be to simply disable instructions not supporting EGPR? Part of SSE and AVX instructions without the EVEX counterpart do not support EGPR. We are trying to prohibit EGPR usage under -mapxf in this RFC, but I suppose it is not realistic to disable them. > I hope there are alternatives that would be available in actual APX > implementations? > Otherwise this design limitation doesn't shed a very positive light on > the designers ... I'm a bit confused by "alternatives" here, did you mean the alternative instructions for all the non-EGPR SSE/AVX ones? > How sure are we actual implementations with APX will appear (just > remembering SSE5...)? > I'm quite sure it's not going to be 2024 so would it be realistic to > post-pone APX work > to next stage1, targeting GCC 15 only? APX is a pretty big feature which contains several separate sub features and takes a lot of effort to implement. I suspect that only one release timeframe can accommodate all of them. I would prefer to split it into phases and implement it in GCC phase by phase. Phase1 will include the fundamental features, e.g. EGPR, NDD and PUSH2POP2. We plan to implement and land into GCC14 if it becomes good enough. Phase2 will include CCMP/CTEST/NF and target GCC15. The advantage is that interested users can use GCC14 and try fundamental EGPR feature then. > > > Here is what we did to address the issue: > > > > Middle-end: > > - Add rtx_insn parameter to base_reg_class, reuse the > > MODE_CODE_BASE_REG_CLASS macro with rtx_insn parameter. > > - Add index_reg_class like base_reg_class, calls new > > INSN_INDEX_REG_CLASS > > macro with rtx_insn parameter. > > - In process_address_1, add rtx_insn parameter to call sites of > > base_reg_class, replace usage of INDEX_REG_CLASS to index_reg_class with > > rtx_insn parameter. > > > > Back-end: > > - Extend GENERAL_REG_CLASS, INDEX_REG_CLASS and their supersets with > > corresponding regno checks for EGPRs. > > - Add GENERAL_GPR16/INDEX_GPR16 class for old 16 GPRs. > > - Whole component is controlled under -mapxf/TARGET_APX_EGPR. If it is > > not enabled, clear r16-r31 in accessible_reg_set. > > - New register_constraint “h” and memory_constraint “Bt” that > > disallows > > EGPRs in operand. > > - New asm_gpr32 flag option to enable/disable gpr32 for inline asm, > > disabled by default. > > - If asm_gpr32 is disabled, replace constraints “r” to “h”, and > > “m/memory” to “Bt”. > > - Extra insn attribute gpr32, value 0 indicates the alternative cannot > > use EGPRs. > > - Add target functions for base_reg_class and index_reg_class, calls a > > helper function to verify if insn can use EGPR in its memory_operand. > > - In the helper function, the verify process works as follow: > > 1. Returns true if APX_EGPR disabled or insn is null. > > 2. If the insn is inline asm, returns asm_gpr32 flag. > > 3. Returns false for unrecognizable insn. > > 4. Save recog_data and which_alternative, extract the insn, and restore > > them > > before return. > > 5. Loop through all enabled alternatives, if one of the enabled > > alternatives > > have attr_gpr32 0, returns false, otherwise returns true. > > - For insn alternatives that cannot use gpr32 in
Re: [PATCH 00/13] [RFC] Support Intel APX EGPR
On Thu, Aug 31, 2023 at 10:22 AM Hongyu Wang via Gcc-patches wrote: > > Intel Advanced performance extension (APX) has been released in [1]. > It contains several extensions such as extended 16 general purpose registers > (EGPRs), push2/pop2, new data destination (NDD), conditional compare > (CCMP/CTEST) combined with suppress flags write version of common instructions > (NF). This RFC focused on EGPR implementation in GCC. > > APX introduces a REX2 prefix to help represent EGPR for several legacy/SSE > instructions. For the remaining ones, it promotes some of them using evex > prefix for EGPR. The main issue in APX is that not all legacy/sse/vex > instructions support EGPR. For example, instructions in legacy opcode map2/3 > cannot use REX2 prefix since there is only 1bit in REX2 to indicate map0/1 > instructions, e.g., pinsrd. Also, for most vector extensions, EGPR is > supported > in their evex forms but not vex forms, which means the mnemonics with no evex > forms also cannot use EGPR, e.g., vphaddw. > > Such limitation brings some challenge with current GCC infrastructure. > Generally, we use constraints to guide register allocation behavior. For > register operand, it is easy to add a new constraint to certain insn and limit > it to legacy or REX registers. But for memory operand, if we only use > constraint to limit base/index register choice, reload has no backoff when > process_address allocates any egprs to base/index reg, and then any > post-reload > pass would get ICE from the constraint. How realistic would it be to simply disable instructions not supporting EGPR? I hope there are alternatives that would be available in actual APX implementations? Otherwise this design limitation doesn't shed a very positive light on the designers ... How sure are we actual implementations with APX will appear (just remembering SSE5...)? I'm quite sure it's not going to be 2024 so would it be realistic to post-pone APX work to next stage1, targeting GCC 15 only? > Here is what we did to address the issue: > > Middle-end: > - Add rtx_insn parameter to base_reg_class, reuse the > MODE_CODE_BASE_REG_CLASS macro with rtx_insn parameter. > - Add index_reg_class like base_reg_class, calls new > INSN_INDEX_REG_CLASS > macro with rtx_insn parameter. > - In process_address_1, add rtx_insn parameter to call sites of > base_reg_class, replace usage of INDEX_REG_CLASS to index_reg_class with > rtx_insn parameter. > > Back-end: > - Extend GENERAL_REG_CLASS, INDEX_REG_CLASS and their supersets with > corresponding regno checks for EGPRs. > - Add GENERAL_GPR16/INDEX_GPR16 class for old 16 GPRs. > - Whole component is controlled under -mapxf/TARGET_APX_EGPR. If it is > not enabled, clear r16-r31 in accessible_reg_set. > - New register_constraint “h” and memory_constraint “Bt” that disallows > EGPRs in operand. > - New asm_gpr32 flag option to enable/disable gpr32 for inline asm, > disabled by default. > - If asm_gpr32 is disabled, replace constraints “r” to “h”, and > “m/memory” to “Bt”. > - Extra insn attribute gpr32, value 0 indicates the alternative cannot > use EGPRs. > - Add target functions for base_reg_class and index_reg_class, calls a > helper function to verify if insn can use EGPR in its memory_operand. > - In the helper function, the verify process works as follow: > 1. Returns true if APX_EGPR disabled or insn is null. > 2. If the insn is inline asm, returns asm_gpr32 flag. > 3. Returns false for unrecognizable insn. > 4. Save recog_data and which_alternative, extract the insn, and restore > them > before return. > 5. Loop through all enabled alternatives, if one of the enabled > alternatives > have attr_gpr32 0, returns false, otherwise returns true. > - For insn alternatives that cannot use gpr32 in register_operand, use h > constraint instead of r. > - For insn alternatives that cannot use gpr32 in memory operand, use Bt > constraint instead of m, and set corresponding attr_gpr32 to 0. > - Split output template with %v if the sse version of mnemonic cannot > use > gpr32. > - For insn alternatives that cannot use gpr32 in memory operand, > classify > the isa attribute and split alternatives to noavx, avx_noavx512f and etc., so > the helper function can properly loop through the available enabled mask. > > Specifically for inline asm, we currently just map “r/m/memory” constraints as > an example. Eventually we will support entire mapping of all common > constraints > if the mapping method was accepted. > > Also, for vex instructions, currently we assume egpr was supported if they > have > evex counterpart, since any APX enabled machine will have AVX10 support for > all > the evex encodings. We just disabled those mnemonics that doesn’t support > EGPR. > So EGPR will be allowed under -mavx2 -mapxf for many vex mnemonics. > > We haven’t disabled EGPR for
[PATCH 00/13] [RFC] Support Intel APX EGPR
Intel Advanced performance extension (APX) has been released in [1]. It contains several extensions such as extended 16 general purpose registers (EGPRs), push2/pop2, new data destination (NDD), conditional compare (CCMP/CTEST) combined with suppress flags write version of common instructions (NF). This RFC focused on EGPR implementation in GCC. APX introduces a REX2 prefix to help represent EGPR for several legacy/SSE instructions. For the remaining ones, it promotes some of them using evex prefix for EGPR. The main issue in APX is that not all legacy/sse/vex instructions support EGPR. For example, instructions in legacy opcode map2/3 cannot use REX2 prefix since there is only 1bit in REX2 to indicate map0/1 instructions, e.g., pinsrd. Also, for most vector extensions, EGPR is supported in their evex forms but not vex forms, which means the mnemonics with no evex forms also cannot use EGPR, e.g., vphaddw. Such limitation brings some challenge with current GCC infrastructure. Generally, we use constraints to guide register allocation behavior. For register operand, it is easy to add a new constraint to certain insn and limit it to legacy or REX registers. But for memory operand, if we only use constraint to limit base/index register choice, reload has no backoff when process_address allocates any egprs to base/index reg, and then any post-reload pass would get ICE from the constraint. Here is what we did to address the issue: Middle-end: - Add rtx_insn parameter to base_reg_class, reuse the MODE_CODE_BASE_REG_CLASS macro with rtx_insn parameter. - Add index_reg_class like base_reg_class, calls new INSN_INDEX_REG_CLASS macro with rtx_insn parameter. - In process_address_1, add rtx_insn parameter to call sites of base_reg_class, replace usage of INDEX_REG_CLASS to index_reg_class with rtx_insn parameter. Back-end: - Extend GENERAL_REG_CLASS, INDEX_REG_CLASS and their supersets with corresponding regno checks for EGPRs. - Add GENERAL_GPR16/INDEX_GPR16 class for old 16 GPRs. - Whole component is controlled under -mapxf/TARGET_APX_EGPR. If it is not enabled, clear r16-r31 in accessible_reg_set. - New register_constraint “h” and memory_constraint “Bt” that disallows EGPRs in operand. - New asm_gpr32 flag option to enable/disable gpr32 for inline asm, disabled by default. - If asm_gpr32 is disabled, replace constraints “r” to “h”, and “m/memory” to “Bt”. - Extra insn attribute gpr32, value 0 indicates the alternative cannot use EGPRs. - Add target functions for base_reg_class and index_reg_class, calls a helper function to verify if insn can use EGPR in its memory_operand. - In the helper function, the verify process works as follow: 1. Returns true if APX_EGPR disabled or insn is null. 2. If the insn is inline asm, returns asm_gpr32 flag. 3. Returns false for unrecognizable insn. 4. Save recog_data and which_alternative, extract the insn, and restore them before return. 5. Loop through all enabled alternatives, if one of the enabled alternatives have attr_gpr32 0, returns false, otherwise returns true. - For insn alternatives that cannot use gpr32 in register_operand, use h constraint instead of r. - For insn alternatives that cannot use gpr32 in memory operand, use Bt constraint instead of m, and set corresponding attr_gpr32 to 0. - Split output template with %v if the sse version of mnemonic cannot use gpr32. - For insn alternatives that cannot use gpr32 in memory operand, classify the isa attribute and split alternatives to noavx, avx_noavx512f and etc., so the helper function can properly loop through the available enabled mask. Specifically for inline asm, we currently just map “r/m/memory” constraints as an example. Eventually we will support entire mapping of all common constraints if the mapping method was accepted. Also, for vex instructions, currently we assume egpr was supported if they have evex counterpart, since any APX enabled machine will have AVX10 support for all the evex encodings. We just disabled those mnemonics that doesn’t support EGPR. So EGPR will be allowed under -mavx2 -mapxf for many vex mnemonics. We haven’t disabled EGPR for 3DNOW/XOP/LWP/FMA4/TBM instructions, as they will be co-operated with -mapxf. We can disable EGPR for them if AMD guys requires. For testing, currently we tested GCC testsuite and spec2017 with -maxf+sde simulater and no more errors. Also, we inverted the register allocation order to force r31 to be allocated first, and no more error except those AMD only instructions. We will conduct further tests like changing all do-compile to do-assemble and add more to gcc/testsuite in the future. The RFC intends to describe our approach for APX implementation for EGPR component. It may still have potential issues or bugs and requires futher optimization. Any comments are very appreciated. [1].
