Hi Kito & Jeff
A new series for
zcmp(https://patchwork.sourceware.org/project/gcc/list/?series=23929) to:
1. solve the 2 issues Kito catched
2. rebase
The new series would be a replacement of the following:
https://patchwork.sourceware.org/project/gcc/list/?series=21577
Hi Kito
This issue is due to zcmp and shrink-wrap-separate conflict,
which has been addressed by an under-review patch.
[PATCH 0/2] resolve confilct between RISC-V zcmp and shrink-wrap-separate
https://patchwork.sourceware.org/project/gcc/list/?series=21577
Hi Kito
Root cause has been identified.
Here's the frame layout fo the TC, please use courier font :)
+---+
| |
| GPR save area 112 B |
| |
Hi Kito
Thanks for reporting these 2 issues.
Let me check and feedback you soon.
BR
Fei
On 2023-08-16 16:38 Kito Cheng wrote:
>
>Another fail case for CFI:
>
>$ riscv64-unknown-elf-gcc _mulhc3.i
>-march=rv64imafd_zicsr_zifencei_zca_zcmp -mabi=lp64d -g -O2 -o
>_mulhc3.s
>
>typedef float a
Another fail case for CFI:
$ riscv64-unknown-elf-gcc _mulhc3.i
-march=rv64imafd_zicsr_zifencei_zca_zcmp -mabi=lp64d -g -O2 -o
_mulhc3.s
typedef float a __attribute__((mode(HF)));
b, c;
f() {
a a, d, e = a + d;
if (g() && e)
c = b;
}
0x10e508a maybe_record_trace_start
Hi Fei:
Tried to use Jiawei's patch to test this patch and found some issue:
> @@ -5430,13 +5632,15 @@ riscv_expand_prologue (void)
>/* Save the registers. */
>if ((frame->mask | frame->fmask) != 0)
> {
> - HOST_WIDE_INT step1 = riscv_first_stack_step (frame, remaining_size);
not apply
```
-原始邮件-
发件人: "Fei Gao"
发送时间: 2023-06-07 13:52:12 (星期三)
收件人: gcc-patches@gcc.gnu.org
抄送: kito.ch...@gmail.com, pal...@dabbelt.com, jeffreya...@gmail.com,
sinan@linux.alibaba.com, jia...@iscas.ac.cn, "Fei Gao"
主题: [PATCH 1/4][V4][RISC-V] support cm.p
Zcmp can share the same logic as save-restore in stack allocation:
pre-allocation
by cm.push, step 1 and step 2.
please be noted cm.push pushes ra, s0-s11 in reverse order than what
save-restore does.
So adaption has been done in .cfi directives in my patch.
Signed-off-by: Fei Gao
