V3 changes
Redo ChangeLog for code move.
Replace spaces with tabs in ChangeLog.
Replaced intruction names using * with the actual list of names. For
example vextdu*vrx with the explicit instruction names vextdubvrx,
vextduhvrx, etc.
-
v2 changes
config/rs6000/altivec.md log entry for move from changed as suggested.
config/rs6000/vsx.md log entro for moved to here changed as suggested.
define_mode_iterator VI2 also moved, included in both change log entries
GCC maintainers:
Move the existing vector extract support in altivec.md to vsx.md
so all of the vector insert and extract support is in the same file.
The patch also updates the name of the builtins and descriptions for the
builtins in the documentation file so they match the approved builtin
names and descriptions.
The patch does not make any functional changes.
Please let me know if the changes are acceptable for mainline. Thanks.
Carl Love
--
gcc/ChangeLog
2020-06-18 Carl Love
* config/rs6000/altivec.md: (UNSPEC_EXTRACTL, UNSPEC_EXTRACTR)
(vextractl, vextractr)
(vextractl_internal, vextractr_internal)
(VI2): Move to ...
* config/rs6000/vsx.md: (UNSPEC_EXTRACTL, UNSPEC_EXTRACTR)
(vextractl, vextractr)
(vextractl_internal, vextractr_internal)
(VI2): ..here.
* gcc/doc/extend.texi: Update documentation for vec_extractl.
Replace builtin name vec_extractr with vec_extracth. Update description
of vec_extracth.
---
gcc/config/rs6000/altivec.md | 64 --
gcc/config/rs6000/vsx.md | 66 +++
gcc/doc/extend.texi | 77 ++--
3 files changed, 105 insertions(+), 102 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 159f24ebc10..0b0b49ee056 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -171,8 +171,6 @@
UNSPEC_XXEVAL
UNSPEC_VSTRIR
UNSPEC_VSTRIL
- UNSPEC_EXTRACTL
- UNSPEC_EXTRACTR
])
(define_c_enum "unspecv"
@@ -183,8 +181,6 @@
UNSPECV_DSS
])
-;; Like VI, defined in vector.md, but add ISA 2.07 integer vector ops
-(define_mode_iterator VI2 [V4SI V8HI V16QI V2DI])
;; Short vec int modes
(define_mode_iterator VIshort [V8HI V16QI])
;; Longer vec int modes for rotate/mask ops
@@ -785,66 +781,6 @@
DONE;
})
-(define_expand "vextractl"
- [(set (match_operand:V2DI 0 "altivec_register_operand")
- (unspec:V2DI [(match_operand:VI2 1 "altivec_register_operand")
- (match_operand:VI2 2 "altivec_register_operand")
- (match_operand:SI 3 "register_operand")]
-UNSPEC_EXTRACTL))]
- "TARGET_FUTURE"
-{
- if (BYTES_BIG_ENDIAN)
-{
- emit_insn (gen_vextractl_internal (operands[0], operands[1],
- operands[2], operands[3]));
- emit_insn (gen_xxswapd_v2di (operands[0], operands[0]));
-}
- else
-emit_insn (gen_vextractr_internal (operands[0], operands[2],
-operands[1], operands[3]));
- DONE;
-})
-
-(define_insn "vextractl_internal"
- [(set (match_operand:V2DI 0 "altivec_register_operand" "=v")
- (unspec:V2DI [(match_operand:VEC_I 1 "altivec_register_operand" "v")
- (match_operand:VEC_I 2 "altivec_register_operand" "v")
- (match_operand:SI 3 "register_operand" "r")]
-UNSPEC_EXTRACTL))]
- "TARGET_FUTURE"
- "vextvlx %0,%1,%2,%3"
- [(set_attr "type" "vecsimple")])
-
-(define_expand "vextractr"
- [(set (match_operand:V2DI 0 "altivec_register_operand")
- (unspec:V2DI [(match_operand:VI2 1 "altivec_register_operand")
- (match_operand:VI2 2 "altivec_register_operand")
- (match_operand:SI 3 "register_operand")]
-UNSPEC_EXTRACTR))]
- "TARGET_FUTURE"
-{
- if (BYTES_BIG_ENDIAN)
-{
- emit_insn (gen_vextractr_internal (operands[0], operands[1],
- operands[2], operands[3]));
- emit_insn (gen_xxswapd_v2di (operands[0], operands[0]));
-}
- else
-emit_insn (gen_vextractl_internal (operands[0], operands[2],
-operands[1], operands[3]));
- DONE;
-})
-
-(define_insn "vextractr_internal"
- [(set (match_operand:V2DI 0 "altivec_register_operand" "=v")
- (unspec:V2DI [(match_operand:VEC_I 1 "altivec_register_operand" "v")
- (match_operand:VEC_I 2 "altivec_register_operand" "v")
- (match_operand:SI 3 "register_operand" "r")]
-UNSPEC_EXTRACTR))]
- "TARGET_FUTURE"
- "vextvrx %0,%1,%2,%3"
- [(set_attr "type" "vecsimple")])
-
(define_expand "vstrir_"
