On 12 August 2014 15:55, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
* config/aarch64/aarch64.c (LOGICAL:optab_one_cmplmode3):
Reparameterize to...
(NLOGICAL:optab_one_cmplmode3): with extra SIMD-register
variant.
(xor_one_cmplmode3): New
So my reasoning was that the alternative is likely to be more expensive *on all
cores*, as it is split to two instructions, whereas add/sub could be more
expensive for *some* processors.
But yes I can see the argument, by my own logic and James Greenhalgh's, for
removing the '?': it still
[When I wrote that xor was broken on GPRs and this fixes it, I meant
xor_one_cmpl rather than xor, sorry!]
The pattern for xor_one_cmpl never matched, due to the action of
combine_simplify_rtx; hence, separate this pattern out from that for ORN/BIC.
ORN/BIC have equivalent SIMD-reg variants,
...patch attached...
Alan Lawrence wrote:
[When I wrote that xor was broken on GPRs and this fixes it, I meant
xor_one_cmpl rather than xor, sorry!]
The pattern for xor_one_cmpl never matched, due to the action of
combine_simplify_rtx; hence, separate this pattern out from that for ORN/BIC.
On 13/08/14 00:55, Alan Lawrence wrote:
...patch attached...
Alan Lawrence wrote:
[When I wrote that xor was broken on GPRs and this fixes it, I meant
xor_one_cmpl rather than xor, sorry!]
The pattern for xor_one_cmpl never matched, due to the action of
combine_simplify_rtx; hence,
