Re: [PATCH rs6000], Move Power 8 tests, fix ICE for vec_unsigned2, vec_signed2

2018-02-22 Thread Segher Boessenkool 
Hi!

On Wed, Feb 21, 2018 at 11:10:25AM -0800, Carl Love wrote:
> Per discussions with Segher, we felt it would be best to move the
> vec_float2 test to a Power 8 test as it is only defined for Power 8 and
> beyond. In doing this, I found that compiling builtins-3-runnable.c
> with -mcpu=power7 then generated an ICE for vec_signed2 and
> vec_unsigned2.  It seems that once gcc saw the unsupported vec_float2
> it exited with -mcpu=power7 it exited before seeing the vec_signed2 and
> vec_unsigned2 builtins.  The vec_signed2 and vec_unsigned2 are also
> only defined for Power 8 and beyond.
> 
> This patch moves the three power 8 builtins to a new test file
> builtins-3-runnable-p8.c.  It also fixed the ICE by restricting the
> vec_signed2 and vec_unsigned2 builtins to Power 8.  The builtins-3-
> runnable.c dg settings are then set to enable the test to run on Power
> 7.

> --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
> +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
> @@ -1,7 +1,6 @@
>  /* { dg-do run { target { p8vector_hw } } } */
>  /* { dg-require-effective-target vsx_hw } */
> -/* { dg-options "-O2 -mvsx -mcpu=power8" } */
> -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
> "-mcpu=power8" } } */
> +/* { dg-options "-maltivec -mvsx" } */

I think you should change the p8vector_hw here?  To vsx_hw?

Okay for trunk with that change (please retest this test, of course).
Thanks!


Segher

[PATCH rs6000], Move Power 8 tests, fix ICE for vec_unsigned2, vec_signed2

2018-02-21 Thread Carl Love 
GCC maintainers:

Per discussions with Segher, we felt it would be best to move the
vec_float2 test to a Power 8 test as it is only defined for Power 8 and
beyond. In doing this, I found that compiling builtins-3-runnable.c
with -mcpu=power7 then generated an ICE for vec_signed2 and
vec_unsigned2.  It seems that once gcc saw the unsupported vec_float2
it exited with -mcpu=power7 it exited before seeing the vec_signed2 and
vec_unsigned2 builtins.  The vec_signed2 and vec_unsigned2 are also
only defined for Power 8 and beyond.

This patch moves the three power 8 builtins to a new test file
builtins-3-runnable-p8.c.  It also fixed the ICE by restricting the
vec_signed2 and vec_unsigned2 builtins to Power 8.  The builtins-3-
runnable.c dg settings are then set to enable the test to run on Power
7.

The patch has been tested on:

 powerpc64-unknown-linux-gnu (Power 8BE)
 powerpc64le-unknown-linux-gnu
(Power 8LE)
 powerpc64le-unknown-linux-gnu (Power 9LE)

and no regressions were found.  Additionally, the tests were compiled
by hand with -mcpu=power7 to ensure gcc doesn't give and ICE.

Please let me know if the patch looks OK or not. Thanks.

   Carl Love

---

gcc/ChangeLog:

2018-02-19  Carl Love  

* config/rs6000/rs6000-builtin.def: Change VSIGNED2 and VUNSIGNED2
macro expansions from BU_VSX_2 to BU_P8V_VSX_2 and BU_VSX_OVERLOAD_2 to
BU_P8V_OVERLOAD_2.
* config/rs6000/rs6000-c.c: Change VSX_BUILTIN_VEC_VSIGNED2 to
P8V_BUILTIN_VEC_VSIGNED2.  Change VSX_BUILTIN_VEC_VUNSIGNED2 to
P8V_BUILTIN_VEC_VUNSIGNED2.

gcc/testsuite/ChangeLog:

2018-02-19  Carl Love  

* gcc.target/powerpc/builtins-3-runnable.c: Move tests for vec_float2,
vec_signed2 and vec_unsigned2 to new Power 8 test file.
* gcc.target/powerpc/builtins-3-runnable-p8.c: New test file for
Power 8 tests.
---
 gcc/config/rs6000/rs6000-builtin.def   |  10 +-
 gcc/config/rs6000/rs6000-c.c   |   4 +-
 .../gcc.target/powerpc/builtins-3-runnable-p8.c| 162 +
 .../gcc.target/powerpc/builtins-3-runnable.c   |  31 +---
 4 files changed, 170 insertions(+), 37 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3-runnable-p8.c

diff --git a/gcc/config/rs6000/rs6000-builtin.def 
b/gcc/config/rs6000/rs6000-builtin.def
index 876b1d9..f9548a0 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1659,9 +1659,6 @@ BU_VSX_2 (CMPLE_U8HI, "cmple_u8hi", CONST,  
vector_ngtuv8hi)
 BU_VSX_2 (CMPLE_U4SI, "cmple_u4si", CONST,  vector_ngtuv4si)
 BU_VSX_2 (CMPLE_U2DI, "cmple_u2di", CONST,  vector_ngtuv2di)
 
-BU_VSX_2 (VEC_VSIGNED2_V2DF,  "vsigned2_v2df",CONST,  vsigned2_v2df)
-BU_VSX_2 (VEC_VUNSIGNED2_V2DF,"vunsigned2_v2df",  CONST,  vunsigned2_v2df)
-
 /* VSX abs builtin functions.  */
 BU_VSX_A (XVABSDP,   "xvabsdp",CONST,  absv2df2)
 BU_VSX_A (XVNABSDP,  "xvnabsdp",   CONST,  vsx_nabsv2df2)
@@ -1852,8 +1849,6 @@ BU_VSX_OVERLOAD_2 (XXMRGHW,  "xxmrghw")
 BU_VSX_OVERLOAD_2 (XXMRGLW,  "xxmrglw")
 BU_VSX_OVERLOAD_2 (XXSPLTD,  "xxspltd")
 BU_VSX_OVERLOAD_2 (XXSPLTW,  "xxspltw")
-BU_VSX_OVERLOAD_2 (VSIGNED2, "vsigned2")
-BU_VSX_OVERLOAD_2 (VUNSIGNED2,   "vunsigned2")
 
 /* 1 argument VSX overloaded builtin functions.  */
 BU_VSX_OVERLOAD_1 (DOUBLE,   "double")
@@ -1917,6 +1912,9 @@ BU_P8V_AV_1 (NEG_V2DF,  "neg_v2df",   CONST,  
negv2df2)
 BU_P8V_VSX_2 (FLOAT2_V2DF,"float2_v2df",   CONST,  float2_v2df)
 BU_P8V_VSX_2 (FLOAT2_V2DI,"float2_v2di",   CONST,  float2_v2di)
 BU_P8V_VSX_2 (UNS_FLOAT2_V2DI,"uns_float2_v2di",CONST,  
uns_float2_v2di)
+BU_P8V_VSX_2 (VEC_VSIGNED2_V2DF,   "vsigned2_v2df",CONST,  vsigned2_v2df)
+BU_P8V_VSX_2 (VEC_VUNSIGNED2_V2DF, "vunsigned2_v2df",  CONST,  vunsigned2_v2df)
+
 
 /* 1 argument altivec instructions added in ISA 2.07.  */
 BU_P8V_AV_1 (ABS_V2DI,   "abs_v2di",   CONST,  absv2di2)
@@ -2063,6 +2061,8 @@ BU_P8V_OVERLOAD_2 (VSUBUDM,   "vsubudm")
 BU_P8V_OVERLOAD_2 (VSUBUQM,"vsubuqm")
 BU_P8V_OVERLOAD_2 (FLOAT2,   "float2")
 BU_P8V_OVERLOAD_2 (UNS_FLOAT2,   "uns_float2")
+BU_P8V_OVERLOAD_2 (VSIGNED2, "vsigned2")
+BU_P8V_OVERLOAD_2 (VUNSIGNED2,   "vunsigned2")
 
 /* ISA 2.07 vector overloaded 3 argument functions.  */
 BU_P8V_OVERLOAD_3 (VADDECUQ,   "vaddecuq")
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 6e4a269..cc8e4e1 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -5876,7 +5876,7 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
   { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
-  {