RE: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its constraints [PR114714]
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, April 25, 2024 5:27 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2 ; Kito.cheng
Subject: Re: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its
constraints [PR114714]
LGTM. THANKS
juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
From: pan2.li<mailto:pan2...@intel.com>
Date: 2024-04-25 17:25
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>;
kito.cheng<mailto:kito.ch...@gmail.com>; rdapp.gcc<mailto:rdapp@gmail.com>;
Pan Li<mailto:pan2...@intel.com>; Kito Cheng<mailto:kito.ch...@sifive.com>
Subject: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its
constraints [PR114714]
From: Pan Li mailto:pan2...@intel.com>>
We have one ICE when RVV register overlap is enabled. We reverted this
feature as it is in stage 4 and there is no much time to figure a better
solution for this. Thus, for now add the related test cases which will
trigger ICE when register overlap enabled.
This will gate the RVV register overlap support in GCC-15.
PR target/114714
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr114714-1.C: New test.
* g++.target/riscv/rvv/base/pr114714-2.C: New test.
Signed-off-by: Pan Li mailto:pan2...@intel.com>>
Co-Authored-by: Kito Cheng mailto:kito.ch...@sifive.com>>
---
.../g++.target/riscv/rvv/base/pr114714-1.C| 85 +++
.../g++.target/riscv/rvv/base/pr114714-2.C| 85 +++
2 files changed, 170 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
new file mode 100644
index 000..d3230f7f23e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
@@ -0,0 +1,85 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -std=c++17" } */
+
+typedef int a;
+typedef short b;
+typedef unsigned c;
+template < typename > using e = unsigned;
+template < typename > void ab();
+#pragma riscv intrinsic "vector"
+template < typename f, int, int ac > struct g {
+ using i = f;
+ template < typename m > using j = g< m, 0, ac >;
+ using k = g< i, 1, ac - 1 >;
+ using ad = g< i, 1, ac + 1 >;
+};
+namespace ae {
+struct af {
+ using h = g< short, 6, 0 < 3 >;
+};
+struct ag {
+ using h = af::h;
+};
+} template < typename, int > using ah = ae::ag::h;
+template < class ai > using aj = typename ai::i;
+template < class i, class ai > using j = typename ai::j< i >;
+template < class ai > using ak = j< e< ai >, ai >;
+template < class ai > using k = typename ai::k;
+template < class ai > using ad = typename ai::ad;
+template < a ap > vuint16m1_t ar(g< b, ap, 0 >, b);
+template < a ap > vuint16m2_t ar(g< b, ap, 1 >, b);
+template < a ap > vuint32m2_t ar(g< c, ap, 1 >, c);
+template < a ap > vuint32m4_t ar(g< c, ap, 2 >, c);
+template < class ai > using as = decltype(ar(ai(), aj< ai >()));
+template < class ai > as< ai > at(ai);
+namespace ae {
+template < int ap > vuint32m4_t au(g< c, ap, 1 + 1 >, vuint32m2_t l) {
+ return __riscv_vlmul_ext_v_u32m2_u32m4(l);
+}
+} template < int ap > vuint32m2_t aw(g< c, ap, 1 >, vuint16m1_t l) {
+ return __riscv_vzext_vf2_u32m2(l, 0);
+}
+namespace ae {
+vuint32m4_t ax(vuint32m4_t, vuint32m4_t, a);
+}
+template < class ay, class an > as< ay > az(ay ba, an bc) {
+ an bb;
+ return ae::ax(ae::au(ba, bc), ae::au(ba, bb), 2);
+}
+template < class bd > as< bd > be(bd, as< ad< bd > >);
+namespace ae {
+template < class bh, class bi > void bj(bh bk, bi bl) {
+ ad< decltype(bk) > bn;
+ az(bn, bl);
+}
+} template < int ap, int ac, class bp, class bq >
+void br(g< c, ap, ac > bk, bp, bq bl) {
+ ae::bj(bk, bl);
+}
+template < class ai > using bs = decltype(at(ai()));
+struct bt;
+template < int ac = 1 > class bu {
+public:
+ template < typename i > void operator()(i) {
+ah< i, ac > d;
+bt()(i(), d);
+ }
+};
+struct bt {
+ template < typename bv, class bf > void operator()(bv, bf bw) {
+using bx = bv;
+ak< bf > by;
+k< bf > bz;
+using bq = bs< decltype(by) >;
+using bp = bs< decltype(bw) >;
+bp cb;
+ab< bx >();
+for (;;) {
+ bp cc;
+ bq bl = aw(by, be(bz, cc));
+ br(by, cb, bl);
+}
+ }
+};
+void d() { bu()(b()); }
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base
Re: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its constraints [PR114714]
LGTM. THANKS
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 17:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li; Kito Cheng
Subject: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its
constraints [PR114714]
From: Pan Li
We have one ICE when RVV register overlap is enabled. We reverted this
feature as it is in stage 4 and there is no much time to figure a better
solution for this. Thus, for now add the related test cases which will
trigger ICE when register overlap enabled.
This will gate the RVV register overlap support in GCC-15.
PR target/114714
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr114714-1.C: New test.
* g++.target/riscv/rvv/base/pr114714-2.C: New test.
Signed-off-by: Pan Li
Co-Authored-by: Kito Cheng
---
.../g++.target/riscv/rvv/base/pr114714-1.C| 85 +++
.../g++.target/riscv/rvv/base/pr114714-2.C| 85 +++
2 files changed, 170 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
new file mode 100644
index 000..d3230f7f23e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
@@ -0,0 +1,85 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -std=c++17" } */
+
+typedef int a;
+typedef short b;
+typedef unsigned c;
+template < typename > using e = unsigned;
+template < typename > void ab();
+#pragma riscv intrinsic "vector"
+template < typename f, int, int ac > struct g {
+ using i = f;
+ template < typename m > using j = g< m, 0, ac >;
+ using k = g< i, 1, ac - 1 >;
+ using ad = g< i, 1, ac + 1 >;
+};
+namespace ae {
+struct af {
+ using h = g< short, 6, 0 < 3 >;
+};
+struct ag {
+ using h = af::h;
+};
+} template < typename, int > using ah = ae::ag::h;
+template < class ai > using aj = typename ai::i;
+template < class i, class ai > using j = typename ai::j< i >;
+template < class ai > using ak = j< e< ai >, ai >;
+template < class ai > using k = typename ai::k;
+template < class ai > using ad = typename ai::ad;
+template < a ap > vuint16m1_t ar(g< b, ap, 0 >, b);
+template < a ap > vuint16m2_t ar(g< b, ap, 1 >, b);
+template < a ap > vuint32m2_t ar(g< c, ap, 1 >, c);
+template < a ap > vuint32m4_t ar(g< c, ap, 2 >, c);
+template < class ai > using as = decltype(ar(ai(), aj< ai >()));
+template < class ai > as< ai > at(ai);
+namespace ae {
+template < int ap > vuint32m4_t au(g< c, ap, 1 + 1 >, vuint32m2_t l) {
+ return __riscv_vlmul_ext_v_u32m2_u32m4(l);
+}
+} template < int ap > vuint32m2_t aw(g< c, ap, 1 >, vuint16m1_t l) {
+ return __riscv_vzext_vf2_u32m2(l, 0);
+}
+namespace ae {
+vuint32m4_t ax(vuint32m4_t, vuint32m4_t, a);
+}
+template < class ay, class an > as< ay > az(ay ba, an bc) {
+ an bb;
+ return ae::ax(ae::au(ba, bc), ae::au(ba, bb), 2);
+}
+template < class bd > as< bd > be(bd, as< ad< bd > >);
+namespace ae {
+template < class bh, class bi > void bj(bh bk, bi bl) {
+ ad< decltype(bk) > bn;
+ az(bn, bl);
+}
+} template < int ap, int ac, class bp, class bq >
+void br(g< c, ap, ac > bk, bp, bq bl) {
+ ae::bj(bk, bl);
+}
+template < class ai > using bs = decltype(at(ai()));
+struct bt;
+template < int ac = 1 > class bu {
+public:
+ template < typename i > void operator()(i) {
+ah< i, ac > d;
+bt()(i(), d);
+ }
+};
+struct bt {
+ template < typename bv, class bf > void operator()(bv, bf bw) {
+using bx = bv;
+ak< bf > by;
+k< bf > bz;
+using bq = bs< decltype(by) >;
+using bp = bs< decltype(bw) >;
+bp cb;
+ab< bx >();
+for (;;) {
+ bp cc;
+ bq bl = aw(by, be(bz, cc));
+ br(by, cb, bl);
+}
+ }
+};
+void d() { bu()(b()); }
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C
new file mode 100644
index 000..55621e98fee
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C
@@ -0,0 +1,85 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -std=c++17" } */
+
+typedef int a;
+typedef short b;
+typedef unsigned c;
+template < typename > using e = unsigned;
+template < typename > void ab();
+#pragma riscv intrinsic "vector"
+template < typename f, int, int ac > struct g {
+ using i = f;
+ template < typename m > using j = g< m, 0, ac &g
[PATCH v1] RISC-V: Add test cases for insn does not satisfy its constraints [PR114714]
From: Pan Li
We have one ICE when RVV register overlap is enabled. We reverted this
feature as it is in stage 4 and there is no much time to figure a better
solution for this. Thus, for now add the related test cases which will
trigger ICE when register overlap enabled.
This will gate the RVV register overlap support in GCC-15.
PR target/114714
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr114714-1.C: New test.
* g++.target/riscv/rvv/base/pr114714-2.C: New test.
Signed-off-by: Pan Li
Co-Authored-by: Kito Cheng
---
.../g++.target/riscv/rvv/base/pr114714-1.C| 85 +++
.../g++.target/riscv/rvv/base/pr114714-2.C| 85 +++
2 files changed, 170 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
new file mode 100644
index 000..d3230f7f23e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C
@@ -0,0 +1,85 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -std=c++17" } */
+
+typedef int a;
+typedef short b;
+typedef unsigned c;
+template < typename > using e = unsigned;
+template < typename > void ab();
+#pragma riscv intrinsic "vector"
+template < typename f, int, int ac > struct g {
+ using i = f;
+ template < typename m > using j = g< m, 0, ac >;
+ using k = g< i, 1, ac - 1 >;
+ using ad = g< i, 1, ac + 1 >;
+};
+namespace ae {
+struct af {
+ using h = g< short, 6, 0 < 3 >;
+};
+struct ag {
+ using h = af::h;
+};
+} template < typename, int > using ah = ae::ag::h;
+template < class ai > using aj = typename ai::i;
+template < class i, class ai > using j = typename ai::j< i >;
+template < class ai > using ak = j< e< ai >, ai >;
+template < class ai > using k = typename ai::k;
+template < class ai > using ad = typename ai::ad;
+template < a ap > vuint16m1_t ar(g< b, ap, 0 >, b);
+template < a ap > vuint16m2_t ar(g< b, ap, 1 >, b);
+template < a ap > vuint32m2_t ar(g< c, ap, 1 >, c);
+template < a ap > vuint32m4_t ar(g< c, ap, 2 >, c);
+template < class ai > using as = decltype(ar(ai(), aj< ai >()));
+template < class ai > as< ai > at(ai);
+namespace ae {
+template < int ap > vuint32m4_t au(g< c, ap, 1 + 1 >, vuint32m2_t l) {
+ return __riscv_vlmul_ext_v_u32m2_u32m4(l);
+}
+} template < int ap > vuint32m2_t aw(g< c, ap, 1 >, vuint16m1_t l) {
+ return __riscv_vzext_vf2_u32m2(l, 0);
+}
+namespace ae {
+vuint32m4_t ax(vuint32m4_t, vuint32m4_t, a);
+}
+template < class ay, class an > as< ay > az(ay ba, an bc) {
+ an bb;
+ return ae::ax(ae::au(ba, bc), ae::au(ba, bb), 2);
+}
+template < class bd > as< bd > be(bd, as< ad< bd > >);
+namespace ae {
+template < class bh, class bi > void bj(bh bk, bi bl) {
+ ad< decltype(bk) > bn;
+ az(bn, bl);
+}
+} template < int ap, int ac, class bp, class bq >
+void br(g< c, ap, ac > bk, bp, bq bl) {
+ ae::bj(bk, bl);
+}
+template < class ai > using bs = decltype(at(ai()));
+struct bt;
+template < int ac = 1 > class bu {
+public:
+ template < typename i > void operator()(i) {
+ah< i, ac > d;
+bt()(i(), d);
+ }
+};
+struct bt {
+ template < typename bv, class bf > void operator()(bv, bf bw) {
+using bx = bv;
+ak< bf > by;
+k< bf > bz;
+using bq = bs< decltype(by) >;
+using bp = bs< decltype(bw) >;
+bp cb;
+ab< bx >();
+for (;;) {
+ bp cc;
+ bq bl = aw(by, be(bz, cc));
+ br(by, cb, bl);
+}
+ }
+};
+void d() { bu()(b()); }
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C
new file mode 100644
index 000..55621e98fee
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C
@@ -0,0 +1,85 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -std=c++17" } */
+
+typedef int a;
+typedef short b;
+typedef unsigned c;
+template < typename > using e = unsigned;
+template < typename > void ab();
+#pragma riscv intrinsic "vector"
+template < typename f, int, int ac > struct g {
+ using i = f;
+ template < typename m > using j = g< m, 0, ac >;
+ using k = g< i, 1, ac - 1 >;
+ using ad = g< i, 1, ac + 1 >;
+};
+namespace ae {
+struct af {
+ using h = g< short, 6, 0 < 3 >;
+};
+struct ag {
+ using h = af::h;
+};
+} template < typename, int > using ah = ae::ag::h;
+template < class ai > using aj = typename ai::i;
+template < class i, class ai > using j = typename ai::j< i >;
+template < class ai > using ak = j< e< ai >, ai >;
+template < class ai > using k = typename ai::k;
+template < class ai > using ad = typename ai::ad;
+template < a ap > vuint16mf2_t ar(g< b, ap, 0 >, b);
+template < a ap > vuint16m1_t ar(g< b, ap, 1 >, b);
+template < a ap >
