Thanks Kito, will send v2 for this change.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, March 21, 2024 8:39 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for __attribute__((target("ar
> +
> + /* Make sure the implied or combined extension is included after add
> + a new std extension to subset list. For exmaple as below,
> +
> + void __attribute__((target("arch=+v"))) func () with -march=rv64gc.
> +
> + The implied zvl128b and zve64d of the std v should be
I can't review this stuff. Let kito review this.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-03-18 14:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))
From: Pan Li
This p
From: Pan Li
This patch would like to fix one ICE for __attribute__((target("arch=+v"))
and likewise extension(s). Given we have sample code as below:
void __attribute__((target("arch=+v")))
test_2 (int *a, int *b, int *out, unsigned count)
{
unsigned i;
for (i = 0; i < count; i++)
