subject:"\[PATCH v1\] RISC\-V\: Support FP l\/ll round and rint HF mode autovec"

Re: [PATCH v1] RISC-V: Support FP l/ll round and rint HF mode autovec

2023-11-12 Thread juzhe.zh...@rivai.ai

LGTM.

juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-11-12 21:47
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP l/ll round and rint HF mode autovec
From: Pan Li 

This patch would like to support the FP below API auto vectorization
with different type size

++---+--+
| API| RV64  | RV32 |
++---+--+
| lrintf16   | HF => DI  | HF => SI |
| llrintf16  | HF => DI  | HF => DI |
| lroundf16  | HF => DI  | HF => SI |
| llroundf16 | HF => DI  | HF => DI |
++---+--+

Given below code:
void
test_lrintf16 (long *out, _Float16 *in, int count)
{
  for (unsigned i = 0; i < count; i++)
out[i] = __builtin_lrintf16 (in[i]);
}

Before this patch:
.L3:
  lhu a5,0(s0)
  addis0,s0,2
  addis1,s1,8
  fmv.s.x fa0,a5
  calllrintf16
  sd  a0,-8(s1)
  bne s0,s2,.L3

After this patch:
.L3:
  vsetvli a5,a2,e16,mf4,ta,ma
  vle16.v v1,0(a1)
  vfwcvt.f.f.vv2,v1
  vsetvli zero,zero,e32,mf2,ta,ma
  vfwcvt.x.f.vv1,v2
  vse64.v v1,0(a0)
  sllia4,a5,1
  add a1,a1,a4
  sllia4,a5,3
  add a0,a0,a4
  sub a2,a2,a5
  bne a2,zero,.L3

gcc/ChangeLog:

* config/riscv/autovec.md: Add bridge mode to lrint and lround
pattern.
* config/riscv/riscv-protos.h (expand_vec_lrint): Add new arg
bridge machine mode.
(expand_vec_lround): Ditto.
* config/riscv/riscv-v.cc (emit_vec_widden_cvt_f_f): New helper
func impl to emit vfwcvt.f.f.
(emit_vec_rounding_to_integer): Handle the HF to DI rounding
with the bridge mode.
(expand_vec_lrint): Reorder the args.
(expand_vec_lround): Ditto.
(expand_vec_lceil): Ditto.
(expand_vec_lfloor): Ditto.
* config/riscv/vector-iterators.md: Add vector HFmode and bridge
mode for converting to DI.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/unop/math-llrintf16-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-llroundf16-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lrintf16-rv32-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lrintf16-rv64-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv32-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c: New test.

Signed-off-by: Pan Li 
---
gcc/config/riscv/autovec.md   | 17 ++--
gcc/config/riscv/riscv-protos.h   |  4 +-
gcc/config/riscv/riscv-v.cc   | 51 
gcc/config/riscv/vector-iterators.md  | 82 ++-
.../riscv/rvv/autovec/unop/math-llrintf16-0.c | 14 
.../rvv/autovec/unop/math-llroundf16-0.c  | 21 +
.../rvv/autovec/unop/math-lrintf16-rv32-0.c   | 13 +++
.../rvv/autovec/unop/math-lrintf16-rv64-0.c   | 15 
.../rvv/autovec/unop/math-lroundf16-rv32-0.c  | 18 
.../rvv/autovec/unop/math-lroundf16-rv64-0.c  | 20 +
.../riscv/rvv/autovec/vls/math-llrintf16-0.c  | 28 +++
.../riscv/rvv/autovec/vls/math-llroundf16-0.c | 28 +++
.../rvv/autovec/vls/math-lrintf16-rv32-0.c| 27 ++
.../rvv/autovec/vls/math-lrintf16-rv64-0.c| 28 +++
.../rvv/autovec/vls/math-lroundf16-rv32-0.c   | 27 ++
.../rvv/autovec/vls/math-lroundf16-rv64-0.c   | 28 +++
16 files changed, 397 insertions(+), 24 deletions(-)
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrintf16-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llroundf16-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrintf16-rv32-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrintf16-rv64-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv32-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 868b47c8af7..80e41af6334 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2455,14

[PATCH v1] RISC-V: Support FP l/ll round and rint HF mode autovec

2023-11-12 Thread pan2 . li

From: Pan Li 

This patch would like to support the FP below API auto vectorization
with different type size

++---+--+
| API| RV64  | RV32 |
++---+--+
| lrintf16   | HF => DI  | HF => SI |
| llrintf16  | HF => DI  | HF => DI |
| lroundf16  | HF => DI  | HF => SI |
| llroundf16 | HF => DI  | HF => DI |
++---+--+

Given below code:
void
test_lrintf16 (long *out, _Float16 *in, int count)
{
  for (unsigned i = 0; i < count; i++)
out[i] = __builtin_lrintf16 (in[i]);
}

Before this patch:
.L3:
  lhu a5,0(s0)
  addis0,s0,2
  addis1,s1,8
  fmv.s.x fa0,a5
  calllrintf16
  sd  a0,-8(s1)
  bne s0,s2,.L3

After this patch:
.L3:
  vsetvli a5,a2,e16,mf4,ta,ma
  vle16.v v1,0(a1)
  vfwcvt.f.f.vv2,v1
  vsetvli zero,zero,e32,mf2,ta,ma
  vfwcvt.x.f.vv1,v2
  vse64.v v1,0(a0)
  sllia4,a5,1
  add a1,a1,a4
  sllia4,a5,3
  add a0,a0,a4
  sub a2,a2,a5
  bne a2,zero,.L3

gcc/ChangeLog:

* config/riscv/autovec.md: Add bridge mode to lrint and lround
pattern.
* config/riscv/riscv-protos.h (expand_vec_lrint): Add new arg
bridge machine mode.
(expand_vec_lround): Ditto.
* config/riscv/riscv-v.cc (emit_vec_widden_cvt_f_f): New helper
func impl to emit vfwcvt.f.f.
(emit_vec_rounding_to_integer): Handle the HF to DI rounding
with the bridge mode.
(expand_vec_lrint): Reorder the args.
(expand_vec_lround): Ditto.
(expand_vec_lceil): Ditto.
(expand_vec_lfloor): Ditto.
* config/riscv/vector-iterators.md: Add vector HFmode and bridge
mode for converting to DI.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/unop/math-llrintf16-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-llroundf16-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lrintf16-rv32-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lrintf16-rv64-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv32-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c: New test.

Signed-off-by: Pan Li 
---
 gcc/config/riscv/autovec.md   | 17 ++--
 gcc/config/riscv/riscv-protos.h   |  4 +-
 gcc/config/riscv/riscv-v.cc   | 51 
 gcc/config/riscv/vector-iterators.md  | 82 ++-
 .../riscv/rvv/autovec/unop/math-llrintf16-0.c | 14 
 .../rvv/autovec/unop/math-llroundf16-0.c  | 21 +
 .../rvv/autovec/unop/math-lrintf16-rv32-0.c   | 13 +++
 .../rvv/autovec/unop/math-lrintf16-rv64-0.c   | 15 
 .../rvv/autovec/unop/math-lroundf16-rv32-0.c  | 18 
 .../rvv/autovec/unop/math-lroundf16-rv64-0.c  | 20 +
 .../riscv/rvv/autovec/vls/math-llrintf16-0.c  | 28 +++
 .../riscv/rvv/autovec/vls/math-llroundf16-0.c | 28 +++
 .../rvv/autovec/vls/math-lrintf16-rv32-0.c| 27 ++
 .../rvv/autovec/vls/math-lrintf16-rv64-0.c| 28 +++
 .../rvv/autovec/vls/math-lroundf16-rv32-0.c   | 27 ++
 .../rvv/autovec/vls/math-lroundf16-rv64-0.c   | 28 +++
 16 files changed, 397 insertions(+), 24 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrintf16-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llroundf16-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrintf16-rv32-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrintf16-rv64-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv32-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 868b47c8af7..80e41af6334 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2455,14 +2455,13 @@

Re: [PATCH v1] RISC-V: Support FP l/ll round and rint HF mode autovec

[PATCH v1] RISC-V: Support FP l/ll round and rint HF mode autovec

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