Committed, thanks Jeff and Juzhe.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Jeff Law via Gcc-patches
Sent: Tuesday, June 20, 2023 10:12 PM
To: juzhe.zh...@rivai.ai; Li Xu ; gcc-patches
Cc: kito.cheng ; palmer
Subject: Re: [PATCH v2] RISC-V: Set the natural size
On 6/20/23 00:47, juzhe.zh...@rivai.ai wrote:
LGTM. Thanks!
OK for the trunk, of course.
jeff
LGTM. Thanks!
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-06-20 14:46
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH v2] RISC-V: Set the natural size of constant vector mask modes
to one RVV data vector.
If reinterpret vnx2bi as vnx16qi, vnx16qi must occupy
If reinterpret vnx2bi as vnx16qi, vnx16qi must occupy no more of the underlying
registers than vnx2bi.
Consider this following case:
void test_vreinterpret_v_b64_i8m1 (uint8_t *in, int8_t *out)
{
vbool64_t vmask = __riscv_vlm_v_b64 (in, 2);
vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1
