Ping!
Siddhesh
On 4 November 2016 at 21:17, Siddhesh Poyarekar
<siddhesh.poyare...@linaro.org> wrote:
> This adds an mcpu option for the upcoming Qualcomm Falkor core. This
> is identical to the qdf24xx part that was added earlier and hence
> retains the same tuning structure and continues to have the a57
> pipeline for now. The part number has also been changed and this
> patch fixes this for both qdf24xx and falkor options.
>
> Tested with aarch64 and armhf.
>
> Siddhesh
>
> * gcc/config/aarch64/aarch64-cores.def (qdf24xx): Update part
> number.
> (falkor): New core.
> * gcc/config/aarch64/aarch64-tune.md: Regenerated.
> * gcc/config/arm/arm-cores.def (falkor): New core.
> * gcc/config/arm/arm-tables.opt: Regenerated.
> * gcc/config/arm/arm-tune.md: Regenerated.
> * gcc/config/arm/bpabi.h (BE8_LINK_SPEC): Add falkor support.
> * gcc/config/arm/t-aprofile (MULTILIB_MATCHES): Add falkor
> support.
> * gcc/doc/invoke.texi (AArch64 Options/-mtune): Add falkor.
> (ARM Options/-mtune): Add falkor.
>
> ---
> gcc/config/aarch64/aarch64-cores.def | 3 ++-
> gcc/config/aarch64/aarch64-tune.md | 2 +-
> gcc/config/arm/arm-cores.def | 1 +
> gcc/config/arm/arm-tables.opt | 3 +++
> gcc/config/arm/arm-tune.md | 2 +-
> gcc/config/arm/bpabi.h | 2 ++
> gcc/config/arm/t-aprofile | 1 +
> gcc/doc/invoke.texi | 9 +++++----
> 8 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-cores.def
> b/gcc/config/aarch64/aarch64-cores.def
> index f9b7552..4b00f3f 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -54,7 +54,8 @@ AARCH64_CORE("cortex-a73", cortexa73, cortexa57, 8A,
> AARCH64_FL_FOR_ARCH8 | AA
> AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001)
>
> /* Qualcomm ('Q') cores. */
> -AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0x800)
> +AARCH64_CORE("falkor", falkor, cortexa57, 8A, AARCH64_FL_FOR_ARCH8
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00)
> +AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00)
>
> /* Cavium ('C') cores. */
> AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a1)
> diff --git a/gcc/config/aarch64/aarch64-tune.md
> b/gcc/config/aarch64/aarch64-tune.md
> index 022b131..29afcdf 100644
> --- a/gcc/config/aarch64/aarch64-tune.md
> +++ b/gcc/config/aarch64/aarch64-tune.md
> @@ -1,5 +1,5 @@
> ;; -*- buffer-read-only: t -*-
> ;; Generated automatically by gentune.sh from aarch64-cores.def
> (define_attr "tune"
> -
> "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,qdf24xx,thunderx,xgene1,vulcan,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53"
> +
> "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,falkor,qdf24xx,thunderx,xgene1,vulcan,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53"
> (const (symbol_ref "((enum attr_tune) aarch64_tune)")))
> diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
> index 2072e1e..1bfec9c 100644
> --- a/gcc/config/arm/arm-cores.def
> +++ b/gcc/config/arm/arm-cores.def
> @@ -173,6 +173,7 @@ ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A,
> ARM_FSET_MAKE_CPU1 (FL_LDSCHED
> ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1
> (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
> ARM_CORE("cortex-a73", cortexa73, cortexa57, 8A, ARM_FSET_MAKE_CPU1
> (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
> ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1
> (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
> +ARM_CORE("falkor", falkor, cortexa57, 8A, ARM_FSET_MAKE_CPU1
> (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
> ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1
> (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
> ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1
> (FL_LDSCHED | FL_FOR_ARCH8A), xgene1)
>
> diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
> index ee9e3bb..7b15c8c 100644
> --- a/gcc/config/arm/arm-tables.opt
> +++ b/gcc/config/arm/arm-tables.opt
> @@ -328,6 +328,9 @@ EnumValue
> Enum(processor_type) String(exynos-m1) Value(exynosm1)
>
> EnumValue
> +Enum(processor_type) String(falkor) Value(falkor)
> +
> +EnumValue
> Enum(processor_type) String(qdf24xx) Value(qdf24xx)
>
> EnumValue
> diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
> index 594ce9d..867da26 100644
> --- a/gcc/config/arm/arm-tune.md
> +++ b/gcc/config/arm/arm-tune.md
> @@ -34,7 +34,7 @@
> cortexm3,marvell_pj4,cortexa15cortexa7,
> cortexa17cortexa7,cortexa32,cortexa35,
> cortexa53,cortexa57,cortexa72,
> - cortexa73,exynosm1,qdf24xx,
> + cortexa73,exynosm1,falkor,qdf24xx,
> xgene1,cortexa57cortexa53,cortexa72cortexa53,
> cortexa73cortexa35,cortexa73cortexa53"
> (const (symbol_ref "((enum attr_tune) arm_tune)")))
> diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
> index 0da98fb..dd4f122 100644
> --- a/gcc/config/arm/bpabi.h
> +++ b/gcc/config/arm/bpabi.h
> @@ -79,6 +79,7 @@
> |mcpu=cortex-a73.cortex-a35 \
> |mcpu=cortex-a73.cortex-a53 \
> |mcpu=exynos-m1 \
> + |mcpu=falkor \
> |mcpu=qdf24xx \
> |mcpu=xgene1 \
> |mcpu=cortex-m1.small-multiply \
> @@ -117,6 +118,7 @@
> |mcpu=cortex-a73.cortex-a35 \
> |mcpu=cortex-a73.cortex-a53 \
> |mcpu=exynos-m1 \
> + |mcpu=falkor \
> |mcpu=qdf24xx \
> |mcpu=xgene1 \
> |mcpu=cortex-m1.small-multiply \
> diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile
> index f852ecd..8b591ba 100644
> --- a/gcc/config/arm/t-aprofile
> +++ b/gcc/config/arm/t-aprofile
> @@ -92,6 +92,7 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73
> MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a35
> MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a53
> MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1
> +MULTILIB_MATCHES += march?armv8-a=mcpu?falkor
> MULTILIB_MATCHES += march?armv8-a=mcpu?qdf24xx
> MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index ad9304f..e3998d6 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -13845,10 +13845,10 @@ processors implementing the target architecture.
> Specify the name of the target processor for which GCC should tune the
> performance of the code. Permissible values for this option are:
> @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
> -@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{qdf24xx},
> -@samp{thunderx}, @samp{xgene1}, @samp{vulcan}, @samp{cortex-a57.cortex-a53},
> -@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},
> -@samp{cortex-a73.cortex-a53}, @samp{native}.
> +@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{falkor},
> +@samp{qdf24xx}, @samp{thunderx}, @samp{xgene1}, @samp{vulcan},
> +@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
> +@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}, @samp{native}.
>
> The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
> @samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}
> @@ -14935,6 +14935,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
> @samp{cortex-m0.small-multiply},
> @samp{cortex-m0plus.small-multiply},
> @samp{exynos-m1},
> +@samp{falkor},
> @samp{qdf24xx},
> @samp{marvell-pj4},
> @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
> --
> 2.7.4
>
