On Wed, May 20, 2015 at 02:58:09PM +0100, Ramana Radhakrishnan wrote:
Hi,
Someone privately pointed out that the ARM and AArch64 ports do not
define TARGET_RELAXED_ORDERING given that the architecture(s) mandates a
weak memory model. This patch fixes it for AArch64, the ARM patch
On Thu, May 21, 2015 at 09:54:19AM +0100, Ramana Radhakrishnan wrote:
And here's an additional patch for the testsuite which was missed in the
original posting.
This is a testism that's testing code generation as per
TARGET_RELAXED_ORDERING being false and therefore needs to be adjusted
And here's an additional patch for the testsuite which was missed in the
original posting.
This is a testism that's testing code generation as per
TARGET_RELAXED_ORDERING being false and therefore needs to be adjusted
as attached.
Ramana
PR target/66200
* g++.dg/abi/aarch64_guard1.C:
Hi,
Someone privately pointed out that the ARM and AArch64 ports do not
define TARGET_RELAXED_ORDERING given that the architecture(s) mandates a
weak memory model. This patch fixes it for AArch64, the ARM patch
follows in due course after appropriate testing.
I will also note that we can
