On Fri, Oct 03, 2014 at 04:39:08PM +0200, Jakub Jelinek wrote:
Just to stress the new testcases some more, I've enabled the
vec_perm_const{32hi,64qi} patterns.
Got several ICEs in expand_vec_perm_broadcast_1,
on the final gcc_unreachable () in the function. That function
is only called if it
Hello Jakub,
On 03 Oct 16:39, Jakub Jelinek wrote:
--- gcc/config/i386/sse.md.jj 2014-09-26 10:33:18.0 +0200
+++ gcc/config/i386/sse.md2014-10-03 15:03:44.170446452 +0200
@@ -10386,7 +10386,8 @@ (define_mode_iterator VEC_PERM_CONST
(V8SI TARGET_AVX) (V4DI TARGET_AVX)
On 06 Oct 09:08, Jakub Jelinek wrote:
On Fri, Oct 03, 2014 at 04:39:08PM +0200, Jakub Jelinek wrote:
Just to stress the new testcases some more, I've enabled the
vec_perm_const{32hi,64qi} patterns.
Got several ICEs in expand_vec_perm_broadcast_1,
on the final gcc_unreachable () in the
On Mon, Oct 06, 2014 at 06:09:07PM +0400, Ilya Tocar wrote:
Speaking of -mavx512{bw,vl,f}, there apparently is a full 2 operand shuffle
for V32HI, V16S[IF], V8D[IF], so the only one instruction full
2 operand shuffle we are missing is V64QI, right?
What would be best worst case sequence
Hi!
Just to stress the new testcases some more, I've enabled the
vec_perm_const{32hi,64qi} patterns.
Got several ICEs in expand_vec_perm_broadcast_1,
on the final gcc_unreachable () in the function. That function
is only called if it couldn't be broadcasted in a single insn,
which I believe for
