Re: [RS6000] Adjust testcases for power10 instructions
On Thu, Jul 01, 2021 at 04:47:21PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Jul 01, 2021 at 10:59:15PM +0930, Alan Modra wrote:
> > * lib/target-supports.exp (check_effective_target_has_arch_pwr10): New.
>
> Mike added this already, please make sure to not add it twice :-)
Yup, rebasing took it out of my patch and a little edit took it out of
my changelog.
> [...]
> > gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
>
> (It still allows older as well, so "Also match" maybe?)
OK.
> Did you make sure all of these are correct and expected?
Yes, they still are. I checked that there was a corresponding
testsuite regression fix for each change too.
> Are the
> testcases still strict enough.
I think so.
, or should you add -mno-pcrel to the
> options, instead? Or maybe test both -mpcrel and -mno-pcrel? Etc.
I think adding -mno-pcrel would be a bad idea, since it would reduce
power10 code coverage, and you'll get both by simply running the
testsuite on power10 and say, power9.
>
> > * gcc.target/powerpc/lvsl-lvsr.c: Avoid file name match.
>
> You also add a "p?", is that expected? Should be in the changelog
> then :-)
It was in the changelog.. I mentioned lvsl-lvsr.c twice (which I
suppose might fall foul of the changelog commit checking). Changing
to
* gcc.target/powerpc/lvsl-lvsr.c: Likewise. Avoid file name match.
> > -/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 2 } } */
> > +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mp?lxv\M} 2 } } */
>
>
> > @@ -1,12 +1,12 @@
> > /* Test expected code generation for lvsl and lvsr on little endian.
> > - Note that lvsl and lvsr are each produced once, but the filename
> > - causes them to appear twice in the file. */
> > + Note that \s is used in the lvsl/lvsr matches so we don't match
> > + on '.file "lvsl-lvsr.c"'. */
>
> Even better is to not put the instruction names in the filename, but
> heh, maybe that would be too simple ;-)
>
>
> Segher
--
Alan Modra
Australia Development Lab, IBM
Re: [RS6000] Adjust testcases for power10 instructions
Hi!
On Thu, Jul 01, 2021 at 10:59:15PM +0930, Alan Modra wrote:
> * lib/target-supports.exp (check_effective_target_has_arch_pwr10): New.
Mike added this already, please make sure to not add it twice :-)
[...]
> gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
(It still allows older as well, so "Also match" maybe?)
Did you make sure all of these are correct and expected? Are the
testcases still strict enough, or should you add -mno-pcrel to the
options, instead? Or maybe test both -mpcrel and -mno-pcrel? Etc.
> * gcc.target/powerpc/lvsl-lvsr.c: Avoid file name match.
You also add a "p?", is that expected? Should be in the changelog
then :-)
> -/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 2 } } */
> +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mp?lxv\M} 2 } } */
> @@ -1,12 +1,12 @@
> /* Test expected code generation for lvsl and lvsr on little endian.
> - Note that lvsl and lvsr are each produced once, but the filename
> - causes them to appear twice in the file. */
> + Note that \s is used in the lvsl/lvsr matches so we don't match
> + on '.file "lvsl-lvsr.c"'. */
Even better is to not put the instruction names in the filename, but
heh, maybe that would be too simple ;-)
Segher
[RS6000] Adjust testcases for power10 instructions
Bootstrapped and regression tested powerpc64le-linux power9 and
power10. OK for mainline?
* lib/target-supports.exp (check_effective_target_has_arch_pwr10): New.
* gcc.dg/pr56727-2.c,
gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c,
gcc.target/powerpc/fold-vec-load-vec_xl-char.c,
gcc.target/powerpc/fold-vec-load-vec_xl-double.c,
gcc.target/powerpc/fold-vec-load-vec_xl-float.c,
gcc.target/powerpc/fold-vec-load-vec_xl-int.c,
gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c,
gcc.target/powerpc/fold-vec-load-vec_xl-short.c,
gcc.target/powerpc/fold-vec-splat-floatdouble.c,
gcc.target/powerpc/fold-vec-splat-longlong.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c,
gcc.target/powerpc/fold-vec-store-vec_xst-char.c,
gcc.target/powerpc/fold-vec-store-vec_xst-double.c,
gcc.target/powerpc/fold-vec-store-vec_xst-float.c,
gcc.target/powerpc/fold-vec-store-vec_xst-int.c,
gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c,
gcc.target/powerpc/fold-vec-store-vec_xst-short.c,
gcc.target/powerpc/lvsl-lvsr.c,
gcc.target/powerpc/ppc-eq0-1.c,
gcc.target/powerpc/ppc-ne0-1.c,
gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
* gcc.target/powerpc/lvsl-lvsr.c: Avoid file name match.
diff --git a/gcc/testsuite/gcc.dg/pr56727-2.c b/gcc/testsuite/gcc.dg/pr56727-2.c
index c54369ed25e..f055116772a 100644
--- a/gcc/testsuite/gcc.dg/pr56727-2.c
+++ b/gcc/testsuite/gcc.dg/pr56727-2.c
@@ -18,4 +18,4 @@ void h ()
/* { dg-final { scan-assembler "@(PLT|plt)" { target i?86-*-* x86_64-*-* } } }
*/
/* { dg-final { scan-assembler "@(PLT|plt)" { target { powerpc*-*-linux* &&
ilp32 } } } } */
-/* { dg-final { scan-assembler "bl f\n\\s*nop" { target { powerpc*-*-linux* &&
lp64 } } } } */
+/* { dg-final { scan-assembler {bl f(\n\s*nop|@notoc\n)} { target {
powerpc*-*-linux* && lp64 } } } } */
diff --git
a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
index 246f38fa6d1..1cff4550f28 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
@@ -25,6 +25,6 @@ main1 (void)
with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
-/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
+/* { dg-final { scan-assembler "\t(lvx|p?lxv|lvsr|p?stxv)" } } */
/* { dg-final { scan-assembler-not "\tlwz?u?x? " { xfail { powerpc-ibm-aix* }
} } } */
/* { dg-final { scan-assembler-not "\tstwu?x? " } } */
diff --git
a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
index 9b199c219bf..104710700c8 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long
long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned
char);
BUILD_CST_TEST( test12, vector unsigned char, 8, vector unsigned char);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M}
12 } } */
+/* { dg-final { scan-assembler-times
{\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
Re: [RS6000] Adjust testcases for power10 instructions V3
Ping.
On Tue, Jan 12, 2021 at 02:03:18PM +1030, Alan Modra wrote:
> Ping
> https://gcc.gnu.org/pipermail/gcc-patches/2020-October/557587.html
>
> On Fri, Oct 30, 2020 at 07:00:14PM +1030, Alan Modra wrote:
> > And now waking up to what you meant by the lvsl-lvsr.c \s comment,
> > plus a revised ppc-ne0-1.c scan-assembler.
> >
> > I think this covers all previous review corrections. Regression tested
> > powerpc64-linux power7 and powerpc64le-linux power10. OK?
> >
> > * lib/target-supports.exp (check_effective_target_has_arch_pwr10): New.
> > * gcc.dg/pr56727-2.c,
> > gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c,
> > gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c,
> > gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c,
> > gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c,
> > gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c,
> > gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c,
> > gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c,
> > gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c,
> > gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c,
> > gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c,
> > gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c,
> > gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c,
> > gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c,
> > gcc.target/powerpc/fold-vec-load-vec_xl-char.c,
> > gcc.target/powerpc/fold-vec-load-vec_xl-double.c,
> > gcc.target/powerpc/fold-vec-load-vec_xl-float.c,
> > gcc.target/powerpc/fold-vec-load-vec_xl-int.c,
> > gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c,
> > gcc.target/powerpc/fold-vec-load-vec_xl-short.c,
> > gcc.target/powerpc/fold-vec-splat-floatdouble.c,
> > gcc.target/powerpc/fold-vec-splat-longlong.c,
> > gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c,
> > gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c,
> > gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c,
> > gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c,
> > gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c,
> > gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c,
> > gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c,
> > gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c,
> > gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c,
> > gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c,
> > gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c,
> > gcc.target/powerpc/fold-vec-store-vec_xst-char.c,
> > gcc.target/powerpc/fold-vec-store-vec_xst-double.c,
> > gcc.target/powerpc/fold-vec-store-vec_xst-float.c,
> > gcc.target/powerpc/fold-vec-store-vec_xst-int.c,
> > gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c,
> > gcc.target/powerpc/fold-vec-store-vec_xst-short.c,
> > gcc.target/powerpc/lvsl-lvsr.c,
> > gcc.target/powerpc/ppc-eq0-1.c,
> > gcc.target/powerpc/ppc-ne0-1.c,
> > gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
> > * gcc.target/powerpc/lvsl-lvsr.c: Avoid file name match.
> >
> > diff --git a/gcc/testsuite/gcc.dg/pr56727-2.c
> > b/gcc/testsuite/gcc.dg/pr56727-2.c
> > index c54369ed25e..f055116772a 100644
> > --- a/gcc/testsuite/gcc.dg/pr56727-2.c
> > +++ b/gcc/testsuite/gcc.dg/pr56727-2.c
> > @@ -18,4 +18,4 @@ void h ()
> >
> > /* { dg-final { scan-assembler "@(PLT|plt)" { target i?86-*-* x86_64-*-* }
> > } } */
> > /* { dg-final { scan-assembler "@(PLT|plt)" { target { powerpc*-*-linux*
> > && ilp32 } } } } */
> > -/* { dg-final { scan-assembler "bl f\n\\s*nop" { target {
> > powerpc*-*-linux* && lp64 } } } } */
> > +/* { dg-final { scan-assembler {bl f(\n\s*nop|@notoc\n)} { target {
> > powerpc*-*-linux* && lp64 } } } } */
> > diff --git
> > a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
> > b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
> > index 246f38fa6d1..1cff4550f28 100644
> > --- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
> > +++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
> > @@ -25,6 +25,6 @@ main1 (void)
> > with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
> > or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
> >
> > -/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
> > +/* { dg-final { scan-assembler "\t(lvx|p?lxv|lvsr|p?stxv)" } } */
> > /* { dg-final { scan-assembler-not "\tlwz?u?x? " { xfail {
> > powerpc-ibm-aix* } } } } */
> > /* { dg-final { scan-assembler-not "\tstwu?x? " } } */
> > diff --git
> > a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
> > b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
> > index 9b199c219bf..104710700c8 100644
> > ---
[RS6000] Adjust testcases for power10 instructions V3
And now waking up to what you meant by the lvsl-lvsr.c \s comment,
plus a revised ppc-ne0-1.c scan-assembler.
I think this covers all previous review corrections. Regression tested
powerpc64-linux power7 and powerpc64le-linux power10. OK?
* lib/target-supports.exp (check_effective_target_has_arch_pwr10): New.
* gcc.dg/pr56727-2.c,
gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c,
gcc.target/powerpc/fold-vec-load-vec_xl-char.c,
gcc.target/powerpc/fold-vec-load-vec_xl-double.c,
gcc.target/powerpc/fold-vec-load-vec_xl-float.c,
gcc.target/powerpc/fold-vec-load-vec_xl-int.c,
gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c,
gcc.target/powerpc/fold-vec-load-vec_xl-short.c,
gcc.target/powerpc/fold-vec-splat-floatdouble.c,
gcc.target/powerpc/fold-vec-splat-longlong.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c,
gcc.target/powerpc/fold-vec-store-vec_xst-char.c,
gcc.target/powerpc/fold-vec-store-vec_xst-double.c,
gcc.target/powerpc/fold-vec-store-vec_xst-float.c,
gcc.target/powerpc/fold-vec-store-vec_xst-int.c,
gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c,
gcc.target/powerpc/fold-vec-store-vec_xst-short.c,
gcc.target/powerpc/lvsl-lvsr.c,
gcc.target/powerpc/ppc-eq0-1.c,
gcc.target/powerpc/ppc-ne0-1.c,
gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
* gcc.target/powerpc/lvsl-lvsr.c: Avoid file name match.
diff --git a/gcc/testsuite/gcc.dg/pr56727-2.c b/gcc/testsuite/gcc.dg/pr56727-2.c
index c54369ed25e..f055116772a 100644
--- a/gcc/testsuite/gcc.dg/pr56727-2.c
+++ b/gcc/testsuite/gcc.dg/pr56727-2.c
@@ -18,4 +18,4 @@ void h ()
/* { dg-final { scan-assembler "@(PLT|plt)" { target i?86-*-* x86_64-*-* } } }
*/
/* { dg-final { scan-assembler "@(PLT|plt)" { target { powerpc*-*-linux* &&
ilp32 } } } } */
-/* { dg-final { scan-assembler "bl f\n\\s*nop" { target { powerpc*-*-linux* &&
lp64 } } } } */
+/* { dg-final { scan-assembler {bl f(\n\s*nop|@notoc\n)} { target {
powerpc*-*-linux* && lp64 } } } } */
diff --git
a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
index 246f38fa6d1..1cff4550f28 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
@@ -25,6 +25,6 @@ main1 (void)
with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
-/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
+/* { dg-final { scan-assembler "\t(lvx|p?lxv|lvsr|p?stxv)" } } */
/* { dg-final { scan-assembler-not "\tlwz?u?x? " { xfail { powerpc-ibm-aix* }
} } } */
/* { dg-final { scan-assembler-not "\tstwu?x? " } } */
diff --git
a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
index 9b199c219bf..104710700c8 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long
long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned
char);
BUILD_CST_TEST( test12, vector unsigned char, 8, vector unsigned char);
-/* { dg-final { scan-assembler-times
[RS6000] Adjust testcases for power10 instructions V2
Revised version.
* gcc.dg/pr56727-2.c,
gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c,
gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c,
gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c,
gcc.target/powerpc/fold-vec-load-vec_xl-char.c,
gcc.target/powerpc/fold-vec-load-vec_xl-double.c,
gcc.target/powerpc/fold-vec-load-vec_xl-float.c,
gcc.target/powerpc/fold-vec-load-vec_xl-int.c,
gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c,
gcc.target/powerpc/fold-vec-load-vec_xl-short.c,
gcc.target/powerpc/fold-vec-splat-floatdouble.c,
gcc.target/powerpc/fold-vec-splat-longlong.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c,
gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c,
gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c,
gcc.target/powerpc/fold-vec-store-vec_xst-char.c,
gcc.target/powerpc/fold-vec-store-vec_xst-double.c,
gcc.target/powerpc/fold-vec-store-vec_xst-float.c,
gcc.target/powerpc/fold-vec-store-vec_xst-int.c,
gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c,
gcc.target/powerpc/fold-vec-store-vec_xst-short.c,
gcc.target/powerpc/lvsl-lvsr.c,
gcc.target/powerpc/ppc-eq0-1.c,
gcc.target/powerpc/ppc-ne0-1.c,
gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
* gcc.target/powerpc/lvsl-lvsr.c: Avoid file name match.
diff --git a/gcc/testsuite/gcc.dg/pr56727-2.c b/gcc/testsuite/gcc.dg/pr56727-2.c
index c54369ed25e..f055116772a 100644
--- a/gcc/testsuite/gcc.dg/pr56727-2.c
+++ b/gcc/testsuite/gcc.dg/pr56727-2.c
@@ -18,4 +18,4 @@ void h ()
/* { dg-final { scan-assembler "@(PLT|plt)" { target i?86-*-* x86_64-*-* } } }
*/
/* { dg-final { scan-assembler "@(PLT|plt)" { target { powerpc*-*-linux* &&
ilp32 } } } } */
-/* { dg-final { scan-assembler "bl f\n\\s*nop" { target { powerpc*-*-linux* &&
lp64 } } } } */
+/* { dg-final { scan-assembler {bl f(\n\s*nop|@notoc\n)} { target {
powerpc*-*-linux* && lp64 } } } } */
diff --git
a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
index 246f38fa6d1..1cff4550f28 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
@@ -25,6 +25,6 @@ main1 (void)
with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
-/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
+/* { dg-final { scan-assembler "\t(lvx|p?lxv|lvsr|p?stxv)" } } */
/* { dg-final { scan-assembler-not "\tlwz?u?x? " { xfail { powerpc-ibm-aix* }
} } } */
/* { dg-final { scan-assembler-not "\tstwu?x? " } } */
diff --git
a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
index 9b199c219bf..104710700c8 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long
long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned
char);
BUILD_CST_TEST( test12, vector unsigned char, 8, vector unsigned char);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M}
12 } } */
+/* { dg-final { scan-assembler-times
{\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git
a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c
Re: [RS6000] Adjust testcases for power10 instructions
On Fri, Oct 23, 2020 at 01:22:31PM -0500, Segher Boessenkool wrote:
> On Fri, Oct 23, 2020 at 04:45:29PM +1030, Alan Modra wrote:
> > Revised patch, removing changes to
> > gcc.target/powerpc/fold-vec-st-double.c,
> > gcc.target/powerpc/fold-vec-st-longlong.c,
> > gcc.target/powerpc/fold-vec-st-pixel.c. Fixing fails on those three
> > tests will be the subject of another patch.
>
> Okido.
>
> > Most of these changes are fairly obvious. Duplicated setbcr in
> > +/* { dg-final { scan-assembler-times {\maddic\M|\msetbcr\M} 4 } } */
> > +/* { dg-final { scan-assembler-times {\msubfe\M|\msetbcr\M} 1 } } */
> > is due to addic;subfe being replaced in one function with setbcr.
>
> But that won't really work. If there is more than one addic replaced by
> setbcr, that second scan fails (because it matches at least two times
> then).
Sure it works. I did test the patch! If future code gen changes, the
test will need updating at that point. scan-assembler tests require
maintenance..
> > * gcc.dg/pr56727-2.c,
> ...
> > * gcc.target/powerpc/ppc-eq0-1.c,
> > * gcc.target/powerpc/ppc-ne0-1.c,
> > * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
>
> This should all be behind only one "*" (so delete it on all but the
> first line here).
Huh, ok.
> > --- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
> > +++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
> > @@ -25,6 +25,6 @@ main1 (void)
> > with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
> > or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
> >
> > -/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
> > +/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv|plxv|pstxv)" } } */
>
> /* { dg-final { scan-assembler "\t(lvx|p?lxv|lvsr|p?stxv)" } } */
> might be more readable/maintainable/extensible?
OK.
> > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
> > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
> > @@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long
> > long, vector unsigned
> > BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned
> > char);
> > BUILD_CST_TEST( test12, vector unsigned char, 8, vector unsigned char);
> >
> > -/* { dg-final { scan-assembler-times
> > {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
> > +/* { dg-final { scan-assembler-times
> > {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
>
> Here, it did not allow lxv before. Should it?
>
> (in many files)
We don't generate lxv due to the insn only supporting DQ offsets. For
example, on power9 test3_cst from this test is
li 9,2
lxvx 34,3,9
blr
On power10
plxv 34,2(3)
blr
> Have you verified the p10 code generation actually makes sense?
Yes, I did.
> > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
> > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
> > @@ -25,7 +25,7 @@ vector signed long long test_sll () { const vector signed
> > long long y = {34, 45}
> > vector unsigned long long test_ull () { const vector unsigned long long y
> > = {56, 67}; return vec_splat (y, 0b00010); }
> >
> > /* Assorted load instructions for the initialization with known constants.
> > */
> > -/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 3 } } */
> > +/* { dg-final { scan-assembler-times
> > {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mplxv\M|\mplxv\M} 3 } } */
>
> You have plxv twice here.
Oops.
> > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c
> > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c
> > @@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed
> > long long, vector unsigned
> > BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned
> > char );
> > BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char );
> >
> > -/* { dg-final { scan-assembler-times
> > {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
> > +/* { dg-final { scan-assembler-times
> > {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
>
> Similarly, should it have plain stxv as well?
No. Same reason as to why lxv isn't generated.
> > --- a/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
> > +++ b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
> > @@ -1,12 +1,10 @@
> > -/* Test expected code generation for lvsl and lvsr on little endian.
> > - Note that lvsl and lvsr are each produced once, but the filename
> > - causes them to appear twice in the file. */
> > +/* Test expected code generation for lvsl and lvsr on little endian. */
> >
> > /* { dg-do compile { target { powerpc64le-*-* } } } */
> > /* { dg-options "-O0 -Wno-deprecated" } */
> > -/* { dg-final { scan-assembler-times "lvsl" 2 } } */
> > -/* { dg-final {
Re: [RS6000] Adjust testcases for power10 instructions
On Fri, Oct 23, 2020 at 04:45:29PM +1030, Alan Modra wrote:
> Revised patch, removing changes to
> gcc.target/powerpc/fold-vec-st-double.c,
> gcc.target/powerpc/fold-vec-st-longlong.c,
> gcc.target/powerpc/fold-vec-st-pixel.c. Fixing fails on those three
> tests will be the subject of another patch.
Okido.
> Most of these changes are fairly obvious. Duplicated setbcr in
> +/* { dg-final { scan-assembler-times {\maddic\M|\msetbcr\M} 4 } } */
> +/* { dg-final { scan-assembler-times {\msubfe\M|\msetbcr\M} 1 } } */
> is due to addic;subfe being replaced in one function with setbcr.
But that won't really work. If there is more than one addic replaced by
setbcr, that second scan fails (because it matches at least two times
then).
> * gcc.dg/pr56727-2.c,
...
> * gcc.target/powerpc/ppc-eq0-1.c,
> * gcc.target/powerpc/ppc-ne0-1.c,
> * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
This should all be behind only one "*" (so delete it on all but the
first line here).
> --- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
> +++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
> @@ -25,6 +25,6 @@ main1 (void)
> with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
> or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
>
> -/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
> +/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv|plxv|pstxv)" } } */
/* { dg-final { scan-assembler "\t(lvx|p?lxv|lvsr|p?stxv)" } } */
might be more readable/maintainable/extensible?
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
> @@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long
> long, vector unsigned
> BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned
> char);
> BUILD_CST_TEST( test12, vector unsigned char, 8, vector unsigned char);
>
> -/* { dg-final { scan-assembler-times
> {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
> +/* { dg-final { scan-assembler-times
> {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
Here, it did not allow lxv before. Should it?
(in many files)
Have you verified the p10 code generation actually makes sense?
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
> @@ -25,7 +25,7 @@ vector signed long long test_sll () { const vector signed
> long long y = {34, 45}
> vector unsigned long long test_ull () { const vector unsigned long long y =
> {56, 67}; return vec_splat (y, 0b00010); }
>
> /* Assorted load instructions for the initialization with known constants. */
> -/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 3 } } */
> +/* { dg-final { scan-assembler-times
> {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mplxv\M|\mplxv\M} 3 } } */
You have plxv twice here.
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c
> @@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long
> long, vector unsigned
> BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned
> char );
> BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char );
>
> -/* { dg-final { scan-assembler-times
> {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
> +/* { dg-final { scan-assembler-times
> {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
Similarly, should it have plain stxv as well?
> --- a/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
> +++ b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
> @@ -1,12 +1,10 @@
> -/* Test expected code generation for lvsl and lvsr on little endian.
> - Note that lvsl and lvsr are each produced once, but the filename
> - causes them to appear twice in the file. */
> +/* Test expected code generation for lvsl and lvsr on little endian. */
>
> /* { dg-do compile { target { powerpc64le-*-* } } } */
> /* { dg-options "-O0 -Wno-deprecated" } */
> -/* { dg-final { scan-assembler-times "lvsl" 2 } } */
> -/* { dg-final { scan-assembler-times "lvsr" 2 } } */
> -/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 2 } } */
> +/* { dg-final { scan-assembler-times {\slvsl\s} 1 } } */
> +/* { dg-final { scan-assembler-times {\slvsr\s} 1 } } */
This could use a comment (we normally use \m \M).
Better is to just rename the file, of course :-)
> +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mplxv\M} 2 } } */
\mp?lxv\M
> --- a/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
> @@ -7,4 +7,4 @@ int foo(int x)
>return x == 0;
> }
>
> -/* { dg-final { scan-assembler "cntlzw|isel" } } */
> +/* { dg-final { scan-assembler {\mcntlzw\M|\misel\M|\msetbc\M}
Re: [RS6000] Adjust testcases for power10 instructions
On Thu, Oct 22, 2020 at 11:25:09PM +1030, Alan Modra wrote:
> Some of these are wrong, sorry. I need to go over and check them
> thoroughly. Please consider the patch withdrawn.
Revised patch, removing changes to
gcc.target/powerpc/fold-vec-st-double.c,
gcc.target/powerpc/fold-vec-st-longlong.c,
gcc.target/powerpc/fold-vec-st-pixel.c. Fixing fails on those three
tests will be the subject of another patch.
Most of these changes are fairly obvious. Duplicated setbcr in
+/* { dg-final { scan-assembler-times {\maddic\M|\msetbcr\M} 4 } } */
+/* { dg-final { scan-assembler-times {\msubfe\M|\msetbcr\M} 1 } } */
is due to addic;subfe being replaced in one function with setbcr.
* gcc.dg/pr56727-2.c,
* gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-char.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-double.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-float.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-int.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-short.c,
* gcc.target/powerpc/fold-vec-splat-floatdouble.c,
* gcc.target/powerpc/fold-vec-splat-longlong.c,
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c,
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c,
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c,
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c,
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-char.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-double.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-float.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-int.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-short.c,
* gcc.target/powerpc/lvsl-lvsr.c,
* gcc.target/powerpc/ppc-eq0-1.c,
* gcc.target/powerpc/ppc-ne0-1.c,
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
* gcc.target/powerpc/lvsl-lvsr.c: Avoid file name match.
diff --git a/gcc/testsuite/gcc.dg/pr56727-2.c b/gcc/testsuite/gcc.dg/pr56727-2.c
index c54369ed25e..f055116772a 100644
--- a/gcc/testsuite/gcc.dg/pr56727-2.c
+++ b/gcc/testsuite/gcc.dg/pr56727-2.c
@@ -18,4 +18,4 @@ void h ()
/* { dg-final { scan-assembler "@(PLT|plt)" { target i?86-*-* x86_64-*-* } } }
*/
/* { dg-final { scan-assembler "@(PLT|plt)" { target { powerpc*-*-linux* &&
ilp32 } } } } */
-/* { dg-final { scan-assembler "bl f\n\\s*nop" { target { powerpc*-*-linux* &&
lp64 } } } } */
+/* { dg-final { scan-assembler {bl f(\n\s*nop|@notoc\n)} { target {
powerpc*-*-linux* && lp64 } } } } */
diff --git
a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
index 246f38fa6d1..d9f173b521e 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
@@ -25,6 +25,6 @@ main1 (void)
with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
-/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
+/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv|plxv|pstxv)" } } */
/* { dg-final { scan-assembler-not "\tlwz?u?x? " { xfail { powerpc-ibm-aix* }
} } } */
/* { dg-final { scan-assembler-not "\tstwu?x? " } } */
diff --git
a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
index 9b199c219bf..104710700c8
Re: [RS6000] Adjust testcases for power10 instructions
On Thu, Oct 22, 2020 at 05:33:46PM +1030, Alan Modra wrote:
> * gcc.dg/pr56727-2.c,
> * gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c,
> * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c,
> * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c,
> * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c,
> * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c,
> * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c,
> * gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c,
> * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c,
> * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c,
> * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c,
> * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c,
> * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c,
> * gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c,
> * gcc.target/powerpc/fold-vec-load-vec_xl-char.c,
> * gcc.target/powerpc/fold-vec-load-vec_xl-double.c,
> * gcc.target/powerpc/fold-vec-load-vec_xl-float.c,
> * gcc.target/powerpc/fold-vec-load-vec_xl-int.c,
> * gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c,
> * gcc.target/powerpc/fold-vec-load-vec_xl-short.c,
> * gcc.target/powerpc/fold-vec-splat-floatdouble.c,
> * gcc.target/powerpc/fold-vec-splat-longlong.c,
> * gcc.target/powerpc/fold-vec-st-double.c,
> * gcc.target/powerpc/fold-vec-st-longlong.c,
> * gcc.target/powerpc/fold-vec-st-pixel.c,
> * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c,
> * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c,
> * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c,
> * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c,
> * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c,
> * gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c,
> * gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c,
> * gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c,
> * gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c,
> * gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c,
> * gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c,
> * gcc.target/powerpc/fold-vec-store-vec_xst-char.c,
> * gcc.target/powerpc/fold-vec-store-vec_xst-double.c,
> * gcc.target/powerpc/fold-vec-store-vec_xst-float.c,
> * gcc.target/powerpc/fold-vec-store-vec_xst-int.c,
> * gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c,
> * gcc.target/powerpc/fold-vec-store-vec_xst-short.c,
> * gcc.target/powerpc/lvsl-lvsr.c,
> * gcc.target/powerpc/ppc-eq0-1.c,
> * gcc.target/powerpc/ppc-ne0-1.c,
> * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
> * gcc.target/powerpc/lvsl-lvsr.c: Avoid file name match.
>
> Regstrapped powerpc64le-linux power10 and power8. OK?
Some of these are wrong, sorry. I need to go over and check them
thoroughly. Please consider the patch withdrawn.
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-st-pixel.c
> b/gcc/testsuite/gcc.target/powerpc/fold-vec-st-pixel.c
> index 5b95cc73d8d..0a3aaec6d8d 100644
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-st-pixel.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-st-pixel.c
> @@ -19,4 +19,4 @@ testst_cst1 (vector pixel vp1, int i1, vector pixel * vpp)
> return vec_st(vp1, 12, vpp);
> }
>
> -/* { dg-final { scan-assembler-times {\mstvx\M} 2 } } */
> +/* { dg-final { scan-assembler-times {\mstvx\M|\mpstxv\M} 2 } } */
For example, this one. We don't get two stvx insns here on power10,
as we should, but we do need altivec style addressing (ie. & -16). So
pstxv should not be a pass.
--
Alan Modra
Australia Development Lab, IBM
[RS6000] Adjust testcases for power10 instructions
* gcc.dg/pr56727-2.c,
* gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c,
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c,
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-char.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-double.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-float.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-int.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c,
* gcc.target/powerpc/fold-vec-load-vec_xl-short.c,
* gcc.target/powerpc/fold-vec-splat-floatdouble.c,
* gcc.target/powerpc/fold-vec-splat-longlong.c,
* gcc.target/powerpc/fold-vec-st-double.c,
* gcc.target/powerpc/fold-vec-st-longlong.c,
* gcc.target/powerpc/fold-vec-st-pixel.c,
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c,
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c,
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c,
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c,
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c,
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-char.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-double.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-float.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-int.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c,
* gcc.target/powerpc/fold-vec-store-vec_xst-short.c,
* gcc.target/powerpc/lvsl-lvsr.c,
* gcc.target/powerpc/ppc-eq0-1.c,
* gcc.target/powerpc/ppc-ne0-1.c,
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Match power10 insns.
* gcc.target/powerpc/lvsl-lvsr.c: Avoid file name match.
Regstrapped powerpc64le-linux power10 and power8. OK?
diff --git a/gcc/testsuite/gcc.dg/pr56727-2.c b/gcc/testsuite/gcc.dg/pr56727-2.c
index c54369ed25e..f055116772a 100644
--- a/gcc/testsuite/gcc.dg/pr56727-2.c
+++ b/gcc/testsuite/gcc.dg/pr56727-2.c
@@ -18,4 +18,4 @@ void h ()
/* { dg-final { scan-assembler "@(PLT|plt)" { target i?86-*-* x86_64-*-* } } }
*/
/* { dg-final { scan-assembler "@(PLT|plt)" { target { powerpc*-*-linux* &&
ilp32 } } } } */
-/* { dg-final { scan-assembler "bl f\n\\s*nop" { target { powerpc*-*-linux* &&
lp64 } } } } */
+/* { dg-final { scan-assembler {bl f(\n\s*nop|@notoc\n)} { target {
powerpc*-*-linux* && lp64 } } } } */
diff --git
a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
index 246f38fa6d1..d9f173b521e 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
@@ -25,6 +25,6 @@ main1 (void)
with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
-/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
+/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv|plxv|pstxv)" } } */
/* { dg-final { scan-assembler-not "\tlwz?u?x? " { xfail { powerpc-ibm-aix* }
} } } */
/* { dg-final { scan-assembler-not "\tstwu?x? " } } */
diff --git
a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
index 9b199c219bf..104710700c8 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long
long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned
char);
BUILD_CST_TEST( test12, vector unsigned char, 8, vector unsigned char);
-/* { dg-final { scan-assembler-times
