We probably want to do some nop'ish thing here which will yield the
cpu thread on Niagara cpus, I'd recommend something along the lines of
rd %ccr, %g0 or rd %y, %g0
libgomp has its own idea about cpu_relax:
static inline void
cpu_relax (void)
{
#if defined __arch64__ || defined __sparc_v9__
From: Eric Botcazou ebotca...@adacore.com
Date: Mon, 27 Feb 2012 10:42:17 +0100
We probably want to do some nop'ish thing here which will yield the
cpu thread on Niagara cpus, I'd recommend something along the lines of
rd %ccr, %g0 or rd %y, %g0
libgomp has its own idea about cpu_relax:
We need a reliable way to test for v9/v8plus/whatever properly because
nobody is testing current gcc with real 32-bit pre-v9 sparc hardware and
not providing atomics and proper cpu_relax implementations is just silly.
Both libgomp and libitm already force -mcpu=v9 though (and simply aren't
From: Eric Botcazou ebotca...@adacore.com
Date: Mon, 27 Feb 2012 21:41:23 +0100
I think the issue is just how we unify the two cpu_relax implementations:
static inline void
cpu_relax (void)
{
#if defined __arch64__ || defined __sparc_v9__
__asm volatile (membar #LoadLoad : : : memory);
I'm not sure, because I'm pretty sure this type of membar acts as a
NOP on basically every sparc v9 chip ever made.
OK, I was inferring from the libgomp implementation that the #LoadLoad variant
might also have yielding properties.
I would prefer to see the rd %%ccr used in both places if
I think you really need to put the proper value into the %fp register
atomically here.
If an interrupt comes in before you STACK_BIAS adjust the %fp, a
debugger or similar could see a corrupt frame pointer.
OK, I'm going to make the change.
--
Eric Botcazou
We probably want to do some nop'ish thing here which will yield the
cpu thread on Niagara cpus, I'd recommend something along the lines of
rd %ccr, %g0 or rd %y, %g0
I'm going for the former, thanks.
--
Eric Botcazou
On 02/12/2012 12:15 PM, Eric Botcazou wrote:
2012-02-12 Eric Botcazou ebotca...@adacore.com
* configure.tgt (target_cpu): Handle sparc and sparc64 sparcv9.
* config/sparc/cacheline.h: New file.
* config/sparc/target.h: Likewise.
* config/sparc/sjlj.S: Likewise.
From: Eric Botcazou ebotca...@adacore.com
Date: Sun, 12 Feb 2012 21:15:26 +0100
+ load[%o1 + OFFSET (JB_CFA)], %fp
+ cfi_def_cfa(%fp, 0)
+#if STACK_BIAS
+ sub %fp, STACK_BIAS, %fp
+ cfi_def_cfa_offset(STACK_BIAS)
+#endif
I think you really need to put the proper
From: Eric Botcazou ebotca...@adacore.com
Date: Sun, 12 Feb 2012 21:15:26 +0100
+static inline void
+cpu_relax (void)
+{
+ __asm volatile ( : : : memory);
+}
We probably want to do some nop'ish thing here which will yield the
cpu thread on Niagara cpus, I'd recommend something along the
Hi,
this adds a SPARC (V9 only) port to the library. Straightforward, except that
the unusual setup of _ITM_beginTransaction's frame consistently crashes GDB if
it is fully described in the CFI. Since backtracing through that frame isn't
very likely to happen in real life, I have left it
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