Hi Martin,
> -Original Message-
> From: Martin Liška
> Sent: 20 May 2020 11:51
> To: Srinath Parvathaneni ; Christophe Lyon
>
> Cc: Richard Earnshaw ; gcc Patches patc...@gcc.gnu.org>
> Subject: Re: [GCC][PATCH][ARM]: Fix the wrong code-gen generated by
Hi.
You forgot to install testsuite/ChangeLog entries. Please do it so that
comparison of future gcc-changelog won't miss these entries.
Martin
MVE
> vector load/store intrinsics (PR94959).
>
> Hi,
>
> > -Original Message-
> > From: Christophe Lyon
> > Sent: 13 May 2020 12:57
> > To: Srinath Parvathaneni
> > Cc: gcc Patches ; Richard Earnshaw
> >
> > Subject: Re: [GCC][PATCH][AR
On Wed, 13 May 2020 at 13:45, Srinath Parvathaneni
wrote:
>
> Hi,
>
> > -Original Message-
> > From: Christophe Lyon
> > Sent: 13 May 2020 11:20
> > To: Srinath Parvathaneni
> > Cc: gcc Patches ; Richard Earnshaw
> >
> > Subject: Re:
Hi,
> -Original Message-
> From: Christophe Lyon
> Sent: 13 May 2020 11:20
> To: Srinath Parvathaneni
> Cc: gcc Patches ; Richard Earnshaw
>
> Subject: Re: [GCC][PATCH][ARM]: Fix the wrong code-gen generated by MVE
> vector load/store intrinsics (PR94959).
>
Hi,
On Wed, 13 May 2020 at 11:47, Srinath Parvathaneni
wrote:
>
> Hello,
>
> Few MVE intrinsics like vldrbq_s32, vldrhq_s32 etc., the assembler
> instructions generated by current compiler are wrong.
> eg: vldrbq_s32 generates an assembly instructions `vldrb.s32 q0,[ip]`.
> But as per Arm-arm
