Re: RFC: GCC Aarch64 SIMD vectorization question involving libmvec

2019-06-28 Thread Szabolcs Nagy
On 27/06/2019 20:54, Steve Ellcey wrote: > I am testing the latest GCC with not-yet-submitted GLIBC changes that > implement libmvec on Aarch64. > > While trying to run SPEC 2017 (specifically 521.wrf_r) I ran into a > case where GCC was generating a call to _ZGVnN2vv_powf, that is a > vectorized

Re: RFC: GCC Aarch64 SIMD vectorization question involving libmvec

2019-06-28 Thread Richard Sandiford
Steve Ellcey writes: > I am testing the latest GCC with not-yet-submitted GLIBC changes that > implement libmvec on Aarch64. > > While trying to run SPEC 2017 (specifically 521.wrf_r) I ran into a > case where GCC was generating a call to _ZGVnN2vv_powf, that is a > vectorized powf call for 2

RFC: GCC Aarch64 SIMD vectorization question involving libmvec

2019-06-27 Thread Steve Ellcey
I am testing the latest GCC with not-yet-submitted GLIBC changes that implement libmvec on Aarch64. While trying to run SPEC 2017 (specifically 521.wrf_r) I ran into a case where GCC was generating a call to _ZGVnN2vv_powf, that is a vectorized powf call for 2 (not 4) elements. This was a