Re: Reject out-of-range bit pos in bit-fields insns operating on a register.

On Nov 10 2016, Jeff Law wrote: > On 11/09/2016 03:40 AM, Andreas Schwab wrote: >> As seen by the testcase in PR77822, combine can generate out-of-range >> bit pos in a bit-field insn, unless the pattern explicitly rejects it. >> This only makes a difference for expressions that

Re: Reject out-of-range bit pos in bit-fields insns operating on a register.

On 11/09/2016 03:40 AM, Andreas Schwab wrote: As seen by the testcase in PR77822, combine can generate out-of-range bit pos in a bit-field insn, unless the pattern explicitly rejects it. This only makes a difference for expressions that are undefined at runtime. Without that we would either

Reject out-of-range bit pos in bit-fields insns operating on a register.

As seen by the testcase in PR77822, combine can generate out-of-range bit pos in a bit-field insn, unless the pattern explicitly rejects it. This only makes a difference for expressions that are undefined at runtime. Without that we would either generate bad assembler or ICE in output_btst.