Re: [Patch] [arm] Fix 88714, Arm LDRD/STRD peepholes

On Mon, Feb 11, 2019 at 12:08:32PM +0100, Jakub Jelinek wrote: > So like the patch below (though, I have only limited possibilities to test > this, can throw it in armv7hl-linux-gnueabi distro build). Actually, that patch was bad, I misread the CORE_REGS vs. GENERAL_REGS hardregset difference, it

Re: [PATCH 27/42] i386: Make _mm_empty () as NOP when MMX is disabled

On Sat, Feb 16, 2019 at 12:58 AM Uros Bizjak wrote: > > On 2/16/19, H.J. Lu wrote: > > With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP > > when MMX is disabled. > > > > PR target/89021 > > * config/i386/mmx.md (mmx_): Renamed to ... > > (mmx__1): This.

[PATCH] i386: Correct *vec_extractv2si_zext_mem

The second and third alternatives in *vec_extractv2si_zext_mem don't require MMX. But the second one requires SSE2. * config/i386/mmx.md (*vec_extractv2si_zext_mem): Doesn't require MMX. Add isa attribute. --- gcc/config/i386/mmx.md | 5 +++-- 1 file changed, 3 insertions(+), 2

Re: [PATCH] Fix up norm2 simplification (PR middle-end/88074)

Hi Jakub, I checked the patch together with Richard's (by which I assume you mean https://gcc.gnu.org/bugzilla/attachment.cgi?id=45052 ), and thinks looked good. So, the Fortran part of this is OK. However, we should really also do power-of-two scaling for the runtime method. Also, we seem to

Re: [PATCH] i386: Correct *vec_extractv2si_zext_mem

On 2/16/19, H.J. Lu wrote: > The second and third alternatives in *vec_extractv2si_zext_mem don't > require MMX. But the second one requires SSE2. > > * config/i386/mmx.md (*vec_extractv2si_zext_mem): Doesn't require > MMX. Add isa attribute. OK. Thanks, Uros. > --- >

[PATCH 24/41] i386: Emulate MMX mmx_psadbw with SSE

Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_psadbw): Add SSE emulation. --- gcc/config/i386/mmx.md | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git

[PATCH 32/41] i386: Emulate MMX pshufb with SSE version

Emulate MMX version of pshufb with SSE version by masking out the bit 3 of the shuffle control byte. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pshufbv8qi3): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE.

[PATCH 34/41] i386: Emulate MMX ssse3_palignrdi with SSE

Emulate MMX version of palignrq with SSE version by concatenating 2 64-bit MMX operands into a single 128-bit SSE operand, followed by SSE psrldq. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_palignrdi): Changed to

[PATCH 36/41] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE

From: Uros Bizjak 2019-02-14 Uroš Bizjak PR target/89021 * config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute. * config/i386/sse.md (*vec_concatv2sf_sse4_1): Ditto. (*vec_concatv2sf_sse): Ditto. (*vec_concatv2si_sse4_1): Ditto.

[PATCH 39/41] i386: Allow MMX intrinsic emulation with SSE

Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA by default with TARGET_MMX_WITH_SSE. For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit mode since MMX intrinsics can be emulated wit SSE. gcc/ PR target/89021 *

[PATCH 18/41] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE

Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_v8qi3): Likewise. (smaxmin:v4hi3): New.

[PATCH 35/41] i386: Emulate MMX abs2 with SSE

Emulate MMX abs2 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (abs2): Add SSE emulation. --- gcc/config/i386/sse.md | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386/sse.md

[PATCH 29/41] i386: Emulate MMX ssse3_phdv2si3 with SSE

Emulate MMX ssse3_phdv2si3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phdv2si3): Changed to define_insn_and_split to support SSE emulation. ---

[PATCH 38/41] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE

PR target/89021 * config/i386/i386.c (ix86_expand_vector_init_duplicate): Set mmx_ok to true if TARGET_MMX_WITH_SSE is true. (ix86_expand_vector_init_one_nonzero): Likewise. (ix86_expand_vector_init_one_var): Likewise.

[PATCH 26/41] i386: Emulate MMX umulv1siv1di3 with SSE2

Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation support. (*sse2_umulv1siv1di3): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 26

[PATCH 30/41] i386: Emulate MMX ssse3_pmaddubsw with SSE

Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation. --- gcc/config/i386/sse.md | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git

Re: [RS6000] Fix _ and tf_ splitters

On Sat, Feb 16, 2019 at 11:14:11AM -0600, Segher Boessenkool wrote: > Okay, thanks! For trunk as well as backports. Applied to trunk. gcc-8 is frozen until after the 8.3 release so I'll have to wait a while for backports. There is some chance we'll hit ICEs on 8.3 like we occasionally did when

Re: C++ PATCH for c++/89217 - ICE with list-initialization in range-based for loop

On 2/16/19 8:23 PM, Marek Polacek wrote: On Fri, Feb 15, 2019 at 01:59:10PM -1000, Jason Merrill wrote: On 2/11/19 6:03 PM, Marek Polacek wrote: On Mon, Feb 11, 2019 at 01:43:36PM -0500, Jason Merrill wrote: On 2/7/19 6:02 PM, Marek Polacek wrote: Since r268321 we can call digest_init even

Re: C++ PATCH for c++/89217 - ICE with list-initialization in range-based for loop

On Fri, Feb 15, 2019 at 01:59:10PM -1000, Jason Merrill wrote: > On 2/11/19 6:03 PM, Marek Polacek wrote: > > On Mon, Feb 11, 2019 at 01:43:36PM -0500, Jason Merrill wrote: > > > On 2/7/19 6:02 PM, Marek Polacek wrote: > > > > Since r268321 we can call digest_init even in a template, when the > >

[PATCH] Fix *rsbg_sidi_srl pattern (PR target/89369)

Hi! The following patch fixes wrong-code on the following testcase extracted from pseudo-RNG with e.g. -march=zEC12 -O2. The problem is in the instruction emitted by the *rsbg_sidi_srl patterns. We have in *.final correct: (insn 67 65 68 (parallel [ (set (reg:SI 1 %r1 [189])

Re: libgo patch committed: Add S/390 support to internal/cpu package

On Sat, Feb 16, 2019 at 08:42:11AM +0100, Jakub Jelinek wrote: > On Fri, Feb 15, 2019 at 08:59:29PM +0100, Matthias Klose wrote: > > On 15.02.19 15:52, Ian Lance Taylor wrote: > > > This patch by Robin Dapp adds S/390 support to the internal/cpu > > > package. This partially addresses PR 89123.

[libgo] Fix alignment issue in persistent allocator

This gets rid of a bunch of Go failures on SPARC. Tested on x86-64/Linux, SPARC/Solaris and SPARC64/Linux. 2019-02-16 Eric Botcazou * go/runtime/malloc.go (persistentalloc1): Always align the offset. -- Eric BotcazouIndex: go/runtime/malloc.go

Re: [PATCH] i386: Add ssse3_pmulhrswv4hi3 expander

On 2/16/19, H.J. Lu wrote: > There is no V4HI pmulhrsw in AVX512BW and V4HI/V8HI pmulhrsw don't require > AVX2. But ssse3_pmulhrswv4hi3 requires MMX. > > PR target/89372 > * config/i386/sse.md (ssedoublemode): Remove V4HI. > (PMULHRSW): Likewise. > (_pmulhrsw3): Require

Re: [PATCH] i386: Add ssse3_pmulhrswv4hi3 expander

On Sat, Feb 16, 2019 at 10:45:11PM +0100, Uros Bizjak wrote: > On 2/16/19, H.J. Lu wrote: > > There is no V4HI pmulhrsw in AVX512BW and V4HI/V8HI pmulhrsw don't require > > AVX2. But ssse3_pmulhrswv4hi3 requires MMX. > > > > PR target/89372 > > * config/i386/sse.md (ssedoublemode):

[PATCH 17/41] i386: Emulate MMX mmx_pinsrw with SSE

Emulate MMX mmx_pinsrw with SSE. Only SSE register destination operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_pinsrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 33

[PATCH 15/41] i386: Emulate MMX sse_cvtpi2ps with SSE

Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of destination XMM register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (sse_cvtpi2ps): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add

[PATCH 16/41] i386: Emulate MMX mmx_pextrw with SSE

Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git

[PATCH 12/41] i386: Emulate MMX vec_dupv2si with SSE

Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow broadcast from integer register for AVX512BW with TARGET_AVX512VL. Only SSE register source operand is allowed. PR target/89021 * config/i386/constraints.md (Yw): New constraint. * config/i386/mmx.md

[PATCH 14/41] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE

Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE. PR target/89021 * config/i386/sse.md (sse_cvtps2pi): Add SSE emulation. (sse_cvttps2pi): Likewise. --- gcc/config/i386/sse.md | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff

[PATCH 33/41] i386: Emulate MMX ssse3_psign3 with SSE

Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_psign3): Add SSE emulation. --- gcc/config/i386/sse.md | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git

[PATCH 11/41] i386: Emulate MMX mmx_eq/mmx_gt3 with SSE

Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_eq3): Also allow TARGET_MMX_WITH_SSE. (*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. (mmx_gt3): Likewise. ---

C++ PATCH to fix eb82.C

I noticed this test fails in c++2a since the implementation of P0846 landed in r265734. Since it's in g++.old-deja/, I never noticted the fail (but I don't see any others). This patch tweaks a dg-error in order to make it pass in c++2a also. Tested on x86_64-linux, ok for trunk? 2019-02-16

[PATCH 20/41] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE

Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_umulv4hi3_highpart): Add SSE emulation. ---

[PATCH 19/41] i386: Emulate MMX mmx_pmovmskb with SSE

Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb from QImode to SImode. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmovmskb): Changed to define_insn_and_split to support SSE emulation. ---

[PATCH 25/41] i386: Emulate MMX movntq with SSE2 movntidi

Emulate MMX movntq with SSE2 movntidi. Only register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse_movntq): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git

[PATCH 28/41] i386: Emulate MMX ssse3_phwv4hi3 with SSE

Emulate MMX ssse3_phwv4hi3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phwv4hi3): Changed to define_insn_and_split to support SSE emulation. ---

[PATCH 13/41] i386: Emulate MMX pshufw with SSE

Emulate MMX pshufw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_pshufw_1): Add SSE emulation. (*vec_dupv4hi): Changed to define_insn_and_split

[PATCH 27/41] i386: Make _mm_empty () as NOP for TARGET_MMX_WITH_SSE

With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP for TARGET_MMX_WITH_SSE. PR target/89021 * config/i386/mmx.md (mmx_): Renamed to ... (*mmx_): This. (mmx_): New expander. --- gcc/config/i386/mmx.md | 30 +- 1

[PATCH 40/41] i386: Enable TM MMX intrinsics with SSE2

This pach enables TM MMX intrinsics with SSE2 when MMX is disabled. PR target/89021 * config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with SSE2. --- gcc/config/i386/i386.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git

[PATCH 31/41] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE

Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pmulhrswv4hi3): Require TARGET_MMX or TARGET_MMX_WITH_SSE. (*ssse3_pmulhrswv4hi3): Add SSE emulation. --- gcc/config/i386/sse.md |

[PATCH] i386: Add ssse3_pmulhrswv4hi3 expander

There is no V4HI pmulhrsw in AVX512BW and V4HI/V8HI pmulhrsw don't require AVX2. But ssse3_pmulhrswv4hi3 requires MMX. PR target/89372 * config/i386/sse.md (ssedoublemode): Remove V4HI. (PMULHRSW): Likewise. (_pmulhrsw3): Require TARGET_SSSE3, not

Re: [C++ PATCH] Fix cxx_eval_store_expression (PR c++/89336)

On 2/13/19 6:02 PM, Jakub Jelinek wrote: As the following testcases shows, cxx_eval_store_expression mishandles the case when constexpr evaluation of the rhs (init) modifies part of the ctor that the store stores into. Except for unions (see below) I believe it is fine the way the outer refs are

New French PO file for 'gcc' (version 9.1-b20190203)

Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'gcc' has been submitted by the French team of translators. The file is available at: https://translationproject.org/latest/gcc/fr.po (This file, 'gcc-9.1-b20190203.fr.po',

Re: [PATCH 17/42] i386: Emulate MMX mmx_pinsrw with SSE

On Sat, Feb 16, 2019 at 1:08 AM Uros Bizjak wrote: > > On 2/16/19, H.J. Lu wrote: > > Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is > > allowed. > > Here we allow general register and memory operands in both cases,, so > the above sentence is misleading. Changed to

[PATCH] s390.md fixes for 32-bit host

Hi! While looking into PR89369, I've noticed various spots in s390.md using 1ul or 1UL which might not work properly if the host is e.g. ilp32, even even instead of using ULL constants it is better to use HOST_WIDE_INT_* macros for HOST_WIDE_INT contexts. Bootstrapped/regtested on s390x-linux,

[PATCH 21/41] i386: Emulate MMX maskmovq with SSE2 maskmovdqu

Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by zero-extending source and mask operands to 128 bits. Handle unmapped bits 64:127 at memory address by adjusting source and mask operands together with memory address. PR target/89021 * config/i386/xmmintrin.h:

[PATCH 37/41] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE

PR target/89021 * config/i386/mmx.md (MMXMODE:mov): Also allow TARGET_MMX_WITH_SSE. (MMXMODE:*mov_internal): Likewise. (MMXMODE:movmisalign): Likewise. --- gcc/config/i386/mmx.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCH 22/41] i386: Emulate MMX mmx_uavgv8qi3 with SSE

Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv8qi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 25

[PATCH 23/41] i386: Emulate MMX mmx_uavgv4hi3 with SSE

Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv4hi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 26

Re: [testsuite] Tweak gcc.target/sparc/struct-ret-check-1.c

> It cannot pass in PIE mode. Likewise for the 3 c-c++-common/patchable_function_entry-*.c on SPARC. Tested on x86-64/Linux and SPARC64/Linux, applied on mainline and 8 branch. 2019-02-16 Eric Botcazou * c-c++-common/patchable_function_entry-decl.c: Add -fno-pie on SPARC. *

V2 [PATCH] i386: Insert ENDBR for NOTE_INSN_DELETED_LABEL only if needed

On Thu, Feb 14, 2019 at 08:13:32PM -0800, H.J. Lu wrote: > NOTE_INSN_DELETED_LABEL is used to mark what used to be a 'code_label', > but was not used for other purposes than taking its address and was > transformed to mark that no code jumps to it. NOTE_INSN_DELETED_LABEL > is generated only in 3

Re: [PATCH] Fix up norm2 simplification (PR middle-end/88074)

On Sat, Feb 16, 2019 at 05:23:58PM +0100, Thomas Koenig wrote: > > Also, we seem to have a lot of issues with IEEE flags > when calculating NORM2, this would also need to be > addressed. > Which IEEE flags and are you referring using the Fortran modules or -ffpe-trap? -- Steve

Re: *ping* [patch, fortran] Fix part of PR 71066

On Sat, Feb 16, 2019 at 3:34 PM Thomas Koenig wrote: > Am 10.02.19 um 12:13 schrieb Thomas Koenig: > > Hello world, > > > > this patch fixes the coarray part of PR 71066 - handling of data > > statements for coarrays. The PR itself is marked as a 7/8/9 > > regression. > > > > Regression-tested.

Re: [RS6000] Fix _ and tf_ splitters

Hi Alan, On Sat, Feb 16, 2019 at 10:40:24PM +1030, Alan Modra wrote: > This patch fixes a bug that can result in "insn does not satisfy its > constraints" if these splitters fire due to not getting ctr for the > jump insn. Since the jump insn can have any of r,m,d,wi,c,l as the > decremented

[PATCH] Fix s390 backend with old binutils (PR target/89361)

Hi! If S390_USE_TARGET_ATTRIBUTE is 0 (e.g. because of configuring against old binutils or even with no binutils at all), then indirect jumps are emitted unconditionally, no matter what is selected on the command line, including the default options. The problem is that

Re: [PATCH 27/42] i386: Make _mm_empty () as NOP when MMX is disabled

On 2/16/19, H.J. Lu wrote: > On Sat, Feb 16, 2019 at 12:58 AM Uros Bizjak wrote: >> >> On 2/16/19, H.J. Lu wrote: >> > With SSE emulation of MMX intrinsics, we should make _mm_empty () as >> > NOP >> > when MMX is disabled. >> > >> > PR target/89021 >> > * config/i386/mmx.md (mmx_):

[PATCH 05/41] i386: Emulate MMX mulv4hi3 with SSE

Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. (mulv4hi3): New. (*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. ---

[PATCH 00/41] V8: Emulate MMX intrinsics with SSE

On x86-64, since __m64 is returned and passed in XMM registers, we can emulate MMX intrinsics with SSE instructions. To support it, we added #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) ;; Define instruction set of MMX instructions (define_attr "mmx_isa"

[PATCH 07/41] i386: Emulate MMX mmx_pmaddwd with SSE

Emulate MMX pmaddwd with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. (*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 25

[PATCH 06/41] i386: Emulate MMX smulv4hi3_highpart with SSE

Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. (*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add SSE support. ---

[PATCH 02/41] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2

Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. 2019-02-08 H.J. Lu Uros Bizjak PR target/89021 * config/i386/i386-protos.h

[PATCH 03/41] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX

Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX, move bits 64:127 to bits 0:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/i386-protos.h (ix86_split_mmx_punpck): New prototype. *

[PATCH 01/41] i386: Allow MMX register modes in SSE registers

In 64-bit mode, SSE2 can be used to emulate MMX instructions without 3DNOW. We can use SSE2 to support MMX register modes. PR target/89021 * config/i386/i386-c.c (ix86_target_macros_internal): Define __MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE. * config/i386/i386.c

[PATCH 04/41] i386: Emulate MMX plusminus/sat_plusminus with SSE

Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI. (plusminus:mmx_3): Check TARGET_MMX_WITH_SSE. (sat_plusminus:mmx_3): Likewise.

[PATCH 08/41] i386: Emulate MMX ashr3/3 with SSE

Emulate MMX ashr3/3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_ashr3): Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. (mmx_3): Likewise. (ashr3): New. (3): Likewise. ---

[PATCH 10/41] i386: Emulate MMX mmx_andnot3 with SSE

Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_andnot3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 18 +++--- 1 file changed, 11 insertions(+), 7

[PATCH 09/41] i386: Emulate MMX 3 with SSE

Emulate MMX 3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (any_logic:mmx_3): Also allow TARGET_MMX_WITH_SSE. (any_logic:3): New. (any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE. Add SSE support.

[PR 89209] Avoid segfault in a peculiar corner case in SRA

Hi, PR 89209 takes place because SRA on trunk encounters an assignment into an SSA_NAME from a V_C_E of a structure load which however cannot contain any useful data because (it is not addressable and) there is no store to that portion of the aggregate in the entire function. In such

Re: [PATCH] Teach evrp that main's argc argument is always non-negative for C family (PR tree-optimization/89350)

On February 16, 2019 8:12:34 AM GMT+01:00, Jakub Jelinek wrote: >Hi! > >Both the C and C++ standard guarantee that the argc argument to main is >non-negative, the following patch sets (or adjusts) the corresponding >SSA_NAME_RANGE_INFO. While main is just one, with IPA VRP it can also

Re: [PATCH] Improve mem = STRING_CST expansion (PR rtl-optimization/66152)

On February 16, 2019 8:19:06 AM GMT+01:00, Jakub Jelinek wrote: >Hi! > >On the following testcase, we've regressed in bar since 8.x, in 8.x >store merging came up with mem = 64-bit constant, but starting with the >change to transform {0,1,2,3,4,5,6,7} char initializers into >STRING_CSTs, >we

Re: [PR 89209] Avoid segfault in a peculiar corner case in SRA

On February 16, 2019 11:56:13 AM GMT+01:00, Martin Jambor wrote: >Hi, > >PR 89209 takes place because SRA on trunk encounters an assignment into >an SSA_NAME from a V_C_E of a structure load which however cannot >contain any useful data because (it is not addressable and) there is no >store to

Re: [PATCH] Teach evrp that main's argc argument is always non-negative for C family (PR tree-optimization/89350)

On Sat, Feb 16, 2019 at 12:10:22PM +0100, Richard Biener wrote: > On February 16, 2019 8:12:34 AM GMT+01:00, Jakub Jelinek > wrote: > >Both the C and C++ standard guarantee that the argc argument to main is > >non-negative, the following patch sets (or adjusts) the corresponding >

Re: [PATCH 17/42] i386: Emulate MMX mmx_pinsrw with SSE

On 2/16/19, H.J. Lu wrote: > Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is > allowed. Here we allow general register and memory operands in both cases,, so the above sentence is misleading. Uros. > > PR target/89021 > * config/i386/mmx.md (mmx_pinsrw): Also

Re: [PATCH 36/42] i386: Correct _pmulhrsw3[_mask]

On 2/16/19, H.J. Lu wrote: > There is no V4HI pmulhrsw in AVX512BW and V4HI/V8HI pmulhrsw don't require > AVX2. To support TARGET_MMX_WITH_SSE, replace nonimmediate_operand with > register_pmulhrswmem_operand in _pmulhrsw3. > > PR target/89372 > * config/i386/predicates.md

Re: [PATCH 39/42] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE

On 2/16/19, H.J. Lu wrote: > PR target/89021 > * config/i386/i386.c (ix86_expand_vector_init_duplicate): Set > mmx_ok to true if TARGET_MMX_WITH_SSE is true. > (ix86_expand_vector_init_one_nonzero): Likewise. > (ix86_expand_vector_init_one_var): Likewise. >

Re: [PATCH] Decrease {i386,sse}.md global state by 12KB

On 2/16/19, Jakub Jelinek wrote: > Hi! > > This is something I've noticed in a s390 change I'll post soon (where it > was > even completely unnecessary), but it applies to i386 backend too. > Seems we have lots of .bss global state, 66x 64-byte and 61x 128-byte long > static buffers. Instead of

Re: [PATCH 27/42] i386: Make _mm_empty () as NOP when MMX is disabled

On 2/16/19, H.J. Lu wrote: > With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP > when MMX is disabled. > > PR target/89021 > * config/i386/mmx.md (mmx_): Renamed to ... > (mmx__1): This. > (mmx_): New expander. > --- > gcc/config/i386/mmx.md | 29

[RS6000] Fix _ and tf_ splitters

This patch fixes a bug that can result in "insn does not satisfy its constraints" if these splitters fire due to not getting ctr for the jump insn. Since the jump insn can have any of r,m,d,wi,c,l as the decremented count output, it's not sufficient to check for gpc_reg_operand (which matches VSX

Re: [PATCH] Add target-zlib to top-level configure, use zlib from libphobos

On 12.02.19 21:54, Iain Buclaw wrote: > On Tue, 12 Feb 2019 at 10:40, Richard Biener > wrote: >> >> On Sat, Feb 9, 2019 at 10:37 AM Iain Buclaw wrote: >>> >>> On Mon, 28 Jan 2019 at 13:10, Richard Biener >>> wrote: On Mon, Jan 21, 2019 at 7:35 PM Iain Buclaw wrote: > > Hi,

Re: [PATCH, RFC] Avoid the -D option which is not available install-sh

On 2/9/19 7:21 PM, Bernd Edlinger wrote: > On 2/9/19 7:18 PM, Jakub Jelinek wrote: >> On Sat, Feb 09, 2019 at 06:11:00PM +, Bernd Edlinger wrote: >>> --- libphobos/libdruntime/Makefile.am (revision 268614) >>> +++ libphobos/libdruntime/Makefile.am (working copy) >>> @@ -140,10

*ping* [patch, fortran] Fix part of PR 71066

Am 10.02.19 um 12:13 schrieb Thomas Koenig: Hello world, this patch fixes the coarray part of PR 71066 - handling of data statements for coarrays.  The PR itself is marked as a 7/8/9 regression. Regression-tested.  OK for trunk and for backporting? Ping? Regards Thomas