On 19/06/14 16:05, Marat Zakirov wrote:
Hi all,
Here's a patch for PR 61561
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61561).
It fixes ICE.
Reg. tested on arm15.
--Marat
arm.md.diff.diff
gcc/ChangeLog:
2014-06-19 Marat Zakirov m.zaki...@samsung.com
*
On 23/06/14 07:57, Zhenqiang Chen wrote:
Hi,
The patch makes several functions global, which will be used when
expanding ccmp instructions.
The other change in this patch is to check CCMP when turning code into
jumpy sequence.
OK for trunk?
This isn't a complete review. In
On 23/06/14 07:58, Zhenqiang Chen wrote:
Hi,
Swapping operands in a ccmp will lead to illegal instructions. So the
patch disables it in simplify_while_replacing.
The patch is separated from
https://gcc.gnu.org/ml/gcc-patches/2014-02/msg01407.html.
To make it clean. The patch adds two
On 23/06/14 07:59, Zhenqiang Chen wrote:
Hi,
This patch includes the main logic to expand ccmp instructions.
In the patch,
* ccmp_candidate_p is used to identify the CCMP candidate
* expand_ccmp_expr is the main entry, which calls expand_ccmp_expr_1
to expand CCMP.
*
On 30/06/14 13:53, Charles Baylis wrote:
On 18 June 2014 00:02, Ramana Radhakrishnan ramana@googlemail.com wrote:
Interesting workaround but can we investigate further how to fix this
at the source rather than working around in the backend in this form.
It's still a kludge that we carry
On 02/07/14 08:52, Tom de Vries wrote:
On 01-07-14 21:47, Jeff Law wrote:
On 07/01/14 13:27, Tom de Vries wrote:
So my question is: is the combination of '' and '+' supported ? If so,
what is the exact semantics ? If not, should we warn or give an error ?
I don't think we can define any
On 02/07/14 13:05, Charles Baylis wrote:
On 30 June 2014 14:26, Richard Earnshaw rearn...@arm.com wrote:
On 30/06/14 13:53, Charles Baylis wrote:
I see two options to fix it - one is to teach the back-end to
successfully generate code for this insn, and the other is to teach
the back-end
level is ARMv6 or higher or the
VFP sub-architecture level is VFPv3 or higher; if either of these are
true then the code cannot run on an affected part.
2014-07-03 Richard Earnshaw rearn...@arm.com
* arm.md (arch): Add armv6_or_vfpv3.
(arch_enabled): Add test for the above
On 04/07/14 10:36, Bin.Cheng wrote:
On Wed, Jun 18, 2014 at 10:16 AM, Terry Guo terry@arm.com wrote:
-Original Message-
From: Richard Earnshaw
Sent: Wednesday, June 18, 2014 4:31 PM
To: Terry Guo
Cc: gcc-patches@gcc.gnu.org; Ramana Radhakrishnan
Subject: Re: [Patch, GCC/Thumb
On 04/07/14 05:59, lin zuojian wrote:
Hi,
This crash is due to fail to consider the exception situation that
the insn variable may not be a insn at all.
arm.c (thumb1_reorg): if the
selected insn is not a insn, continue to next bb.
---
gcc/config/arm/arm.c | 2 +-
1 file
I noticed that although configure on aarch64 handles --with-arch and
--with-cpu, they aren't passed on to the compilation -- instead you just
get whatever the internal default is in the compiler back-end. This
patch fixes that by wiring up the missing logic.
2014-07-04 Richard Earnshaw rearn
On 04/07/14 17:24, Kyrill Tkachov wrote:
Hi all,
-mwords-little-endian was deprecated in GCC 4.7. This patch removes the
option and associated machinery and documentation.
Tested armeb-none-eabi and saw no regressions.
Ok for trunk?
Thanks,
Kyrill
2014-07-04 Kyrylo Tkachov
On 07/07/14 12:01, Kyrill Tkachov wrote:
Hi all,
This patch adds the rtx costs table for the Cortex-A5 core.
Tested arm-none-eabi and looked at the codegen for various codebases to
make sure there's no regression in code quality.
Ok for trunk?
Thanks,
Kyrill
2014-07-07 Kyrylo
First of all, the recognized interval between pings is a week; please
don't ping more often than that.
On 04/07/14 11:57, Gopalasubramanian, Ganesh wrote:
Hi,
Attached is a patch that implements
* Prefetch with immediate offset in the range 0 to 32760 (multiple of 8).
Added a predicate
On 10/07/14 08:46, Terry Guo wrote:
Hi there,
Currently the insn type of DSP-kind instructions like QSUB8 is alu_reg which
is same as other normal instructions like SUB. In order to distinguish those
DSP-kind instructions, this patch intends to replace current alu_reg with
two sub
On 10/07/14 09:06, Terry Guo wrote:
Hi there,
As the second and final patch in this series, it intends to update alu_reg
and alus_reg types for AArch64 port. With this change, the gcc can be
successfully built for AArch64. Is it OK to trunk?
BR,
Terry
2014-07-10 Terry Guo
On 10/07/14 11:12, Marcus Shawcroft wrote:
On 1 July 2014 11:05, Christophe Lyon christophe.l...@linaro.org wrote:
* documentation (README)
* dejanu driver (neon-intrinsics.exp)
* support macros (arm-neon-ref.h, compute-ref-data.h)
* Tests for 3 intrinsics: vaba, vld1, vshl
Hi, The
On 19/06/14 21:19, Yuri Gribov wrote:
Thirdly, we also need to fix movhi_bytes (for pre-v4) thumb2_movhi_insn
(for thumb2) and, quite possibly, thumb1_movhi_insn (for thumb1). There
may well be additional changes for movqi variants as well.
A general question: how should one test ARM
On 14/07/14 11:04, Kyrill Tkachov wrote:
Hi all,
I noticed that we don't have scheduling information for the clz and rbit
instructions in any of the arm pipeline
models except the Cortex-A8 one.
This patch adds those insn types to the relevant models. They're treated
as simple ALU
Noticed while browsing the code. The add_losym_mode instruction takes
an immediate field as the third operand. Hence it's type is alu_imm,
not alu_reg.
Probably doesn't have any major effect on current pipeline models, but
could do one day...
Committed to trunk.
2014-07-14 Richard Earnshaw
On 22/07/14 15:52, Jiong Wang wrote:
currently we are generating sub-optimal epilogue when there
is frame pointer and there is outgoing area.
take gcc.target/aarch64/test_frame_12.c for example:
the epilogue for test_12 is:
.L12:
sub sp, x29, #16
On 02/07/14 09:15, Sebastian Huber wrote:
This change is necessary to support Cortex-R based chips in RTEMS.
This patch should be applied to GCC 4.8, 4.9 and mainline. I do not
have write access, so in case this gets approved, please commit it for
me.
gcc/ChangeLog
2014-07-02 Sebastian
On 29/07/14 20:53, Charles Baylis wrote:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61948
The lshrdi3_neon,ashrdi3_neon,ashldi3_neon patterns can call
gen_arm_shiftdi3_1bit without checking that the register allocation
constraints of the resulting insn are satisfied. This results in an
On 27/10/14 09:21, Yangfei (Felix) wrote:
+/* Handle pragmas for compatibility with Intel's compilers. */
+#define REGISTER_TARGET_PRAGMAS() do {
\
+ c_register_pragma (0, long_calls, aarch64_pr_long_calls);
\
+ c_register_pragma (0,
On 13/11/14 17:05, Ramana Radhakrishnan wrote:
On Thu, Nov 13, 2014 at 4:55 PM, Sandra Loosemore
san...@codesourcery.com wrote:
This patch to the AArch64 back end adds a couple of additional bics patterns
to match code of the form
if ((x y) == x) ...;
This is testing whether the bits
On 13/11/14 17:42, Sandra Loosemore wrote:
On 11/13/2014 10:27 AM, Richard Earnshaw wrote:
On 13/11/14 17:05, Ramana Radhakrishnan wrote:
On Thu, Nov 13, 2014 at 4:55 PM, Sandra Loosemore
san...@codesourcery.com wrote:
This patch to the AArch64 back end adds a couple of additional bics
On 13/11/14 22:44, Sandra Loosemore wrote:
On 11/13/2014 10:47 AM, Andrew Pinski wrote:
On Thu, Nov 13, 2014 at 9:42 AM, Sandra Loosemore
san...@codesourcery.com wrote:
On 11/13/2014 10:27 AM, Richard Earnshaw wrote:
On 13/11/14 17:05, Ramana Radhakrishnan wrote:
On Thu, Nov 13, 2014 at 4
On 18/11/14 09:38, Kyrill Tkachov wrote:
On 17/11/14 16:59, Ramana Radhakrishnan wrote:
On Mon, Nov 17, 2014 at 2:48 PM, Kyrill Tkachov kyrylo.tkac...@arm.com
wrote:
Hi all,
Some configurations of Cortex-A53 and Cortex-A57 don't ship with crypto,
so enabling it by default for
On 18/11/14 10:34, Kyrill Tkachov wrote:
Hi all,
This is a rebase of Andrews' CMP+BRANCH fusion patch on top of my macro
fusion patches.
I've assigned the number 14 to AARCH64_FUSE_CMP_BRANCH.
I've given it a test on top of my fusion patches.
Ok for trunk together with the rest?
On 18/11/14 11:30, Mantas Mikaitis wrote:
Incorrect predefinitions for certain target architectures. E.g. arm7-m
does not contain NEON but the defintion __ARM_NEON_FP was switched on.
Similarly with armv6 and even armv2.
This patch fixes the predefines for each of the different chips
On 19/11/14 18:22, Sandra Loosemore wrote:
On 11/13/2014 10:47 AM, Andrew Pinski wrote:
On Thu, Nov 13, 2014 at 9:42 AM, Sandra Loosemore
san...@codesourcery.com wrote:
On 11/13/2014 10:27 AM, Richard Earnshaw wrote:
On 13/11/14 17:05, Ramana Radhakrishnan wrote:
On Thu, Nov 13, 2014 at 4
On 20/11/14 15:31, Kyrill Tkachov wrote:
Hi all,
As Joseph reminded, new -mcpu options should be documented in
invoke.texi. This adds the documentation for the cortex-a17 and
cortex-a17.cortex-a7 values.
Ok to go in if the corresponding support patches posted earlier are
accepted?
On 21/11/14 11:16, Renlin Li wrote:
Hi,
This patch is to add myself into Write After Approval section of
MAINTAINERS file.
Is it Okay to commit?
Regards,
Renlin Li
ChangeLog:
2014-11-21 Renlin Li renlin...@arm.com
* MAINTAINERS (Write After Approval): Add myself.
On 30/09/14 12:51, Andreas Schwab wrote:
Richard Sandiford richard.sandif...@arm.com writes:
Andreas Schwab sch...@suse.de writes:
Richard Sandiford richard.sandif...@arm.com writes:
@@ -315,7 +318,7 @@ struct ira_allocno
number (0, ...) - 2. Value -1 is used for allocnos spilled by
On 29/09/14 19:32, Richard Henderson wrote:
On 09/29/2014 11:12 AM, Jiong Wang wrote:
+inline rtx single_set_no_clobber_use (const rtx_insn *insn)
+{
+ if (!INSN_P (insn))
+return NULL_RTX;
+
+ if (GET_CODE (PATTERN (insn)) == SET)
+return PATTERN (insn);
+
+ /* Defer to the
On 30/09/14 17:45, Jeff Law wrote:
On 09/30/14 08:15, Richard Earnshaw wrote:
I think part of the problem is in the naming of single_set(). From the
name it's not entirely obvious to users that this includes insns that
clobber registers or which write other registers that are unused after
On 30/09/14 21:30, Eric Christopher wrote:
On Tue, Sep 30, 2014 at 5:57 AM, Marcus Shawcroft
marcus.shawcr...@gmail.com wrote:
On 22 September 2014 19:41, Carrot Wei car...@google.com wrote:
Hi
The extended register width in add/adds/sub/subs/cmp instructions is
not always the same as
On 30/09/14 20:33, Mike Stump wrote:
On Sep 30, 2014, at 9:15 AM, Joseph S. Myers jos...@codesourcery.com wrote:
On Tue, 30 Sep 2014, Richard Earnshaw wrote:
GCC is written in C++ these days, so technically, you need the C++
standard :-)
And, while C++14 requires plain int bit-fields
On 02/09/14 16:34, Kyrill Tkachov wrote:
Hi all,
The store_minmaxsi produces a cmp + ite + 2 conditional stores and is
thus inappropriate when the ARMv8-A IT block rules are in place.
Previously we had disabled it for speed optimisations, but it should be
disabled completely when
On 09/10/14 12:35, Christian Bruel wrote:
On 10/08/2014 06:56 PM, Ramana Radhakrishnan wrote:
Hi Christian,
snipped agreed stuf
3) about inlining
I dislike inlining different modes, From a conceptual use, a user
might want to switch mode only when changing a function's hotness.
On 10/10/14 15:22, Kyrill Tkachov wrote:
On 10/10/14 15:18, Richard Earnshaw wrote:
On 10/10/14 11:53, Kyrill Tkachov wrote:
Hi all,
Some early revisions of the Cortex-A53 have an erratum (835769) whereby
it is possible for a 64-bit multiply-accumulate instruction in
AArch64 state
On 10/10/14 15:18, Christian Bruel wrote:
On 10/09/2014 04:11 PM, Richard Earnshaw wrote:
On 09/10/14 12:35, Christian Bruel wrote:
On 10/08/2014 06:56 PM, Ramana Radhakrishnan wrote:
Hi Christian,
snipped agreed stuf
3) about inlining
I dislike inlining different modes, From
On 13/10/14 15:21, Renlin Li wrote:
Hi all,
This is a simple patch to remove unused variables and marco.
Is it Okay to commit?
gcc/ChangeLog:
2014-10-13 Renlin Li renlin...@arm.com
* config/aarch64/aarch64.h (ARM_DEFAULT_PCS, arm_pcs_variant): Delete.
OK.
R.
Regards,
On 15/10/14 14:35, Renlin Li wrote:
Hi all,
This patch is part of a series of patches that implement ACLE 2.0
predefined macro support for AArch64.
aarch64-none-elf target has been tested on the model, no regression.
Is it Okay to commit?
Kind regards!
Renlin Li
gcc/ChangeLog:
On 15/10/14 14:39, Renlin Li wrote:
Hi all,
This patch is part of a series of patches that implement ACLE 2.0
predefined macros support for AArch64.
aarch64-none-elf target has been tested on the model, no regression.
Is it Okay to commit?
Kind regards!
Renlin Li
gcc/ChangeLog:
On 15/10/14 14:44, Renlin Li wrote:
Hi all,
This patch is part of a series of patches that implement ACLE 2.0
predefined macros support for AArch64.
aarch64-none-elf target has been tested on the model, no regression.
Is it Okay to commit?
Kind regards!
Renlin Li
gcc/ChangeLog:
AArch64 currently does not have a legitimize address hook to find better
solutions for loading from addresses that are not valid. The current
approach 'gets away with it' much of the time because we currently split
constants during expand. We might change that soon, since it is
inhibits other
This patch fixes an issue where only some rotate immediate operations
are merged with logical operations during combine. The problem is due
to canonicalization. The architecture only has a rotate-right
operation, so rotate-left has to be converted into rotate-right. To
avoid fighting the
On 13/04/14 15:30, Gerald Pfeifer wrote:
On Fri, 11 Apr 2014, Yufeng Zhang wrote:
Ping~
Originally posted here:
http://gcc.gnu.org/ml/gcc-patches/2014-03/msg01282.html
Looks okay to me, that I'd prefer it to be approved by a target
maintainer -- AArch64 here.
Gerald
This is fine by
On 15/04/14 11:56, Kyrill Tkachov wrote:
Hi all,
This patch relates to PR60663 where cse got confused due to asm statements
being given a cost of zero in the arm backend. Jakub already put in a fix to
cse for 4.9.0 (http://gcc.gnu.org/ml/gcc-patches/2014-04/msg00512.html) but
we should
On 15/04/14 02:59, Joey Ye wrote:
If-converstion is harmful to optimized debugging as it generates conditional
execution instructions with line number information, which resulted in a
dillusion to developers that both then-else branches are executed.
For example:
test.c:
1: unsigned
On 16/04/14 10:30, Richard Biener wrote:
On Wed, Apr 16, 2014 at 9:46 AM, Joey Ye joey...@arm.com wrote:
-Original Message-
From: Joey Ye [mailto:joey...@arm.com]
Sent: Tuesday, April 15, 2014 6:37 PM
To: 'Richard Biener'
Cc: GCC Patches
Subject: RE: [patch] Disable if_conversion2
On 16/04/14 11:02, Joey Ye wrote:
-Original Message-
From: Richard Earnshaw
Sent: Wednesday, April 16, 2014 5:44 PM
To: Joey Ye
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [patch] Disable if_conversion2 for Og
Arguably, this is a bug in gdb. The debugger should understand when
On 16/04/14 11:17, Joey Ye wrote:
-Original Message-
From: Richard Earnshaw
Sent: Wednesday, April 16, 2014 6:04 PM
To: Joey Ye
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [patch] Disable if_conversion2 for Og
On 16/04/14 11:02, Joey Ye wrote:
-Original Message-
From
On 16/04/14 11:30, Joey Ye wrote:
-Original Message-
From: Richard Earnshaw
Sent: Wednesday, April 16, 2014 6:21 PM
To: Joey Ye
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [patch] Disable if_conversion2 for Og
On 16/04/14 11:17, Joey Ye wrote:
-Original Message-
From
patterns?
But, if the maintainer is fine with that, so am I.
Richard Earnshaw,
are you ok with adding the IP0_REGNUM/IP1_REGNUM clobbers to all the call
patterns in the Aarch64 target?
The alternatives are:
- rewrite the call expansions not to use the rtl templates, and add
On 17/04/14 17:49, Kyrill Tkachov wrote:
Hi all,
While configuring libgfortran I'm getting this message:
libgfortran/configure: line 25938: test: =: unary operator expected
The script doesn't fail and continues afterwards, but I don't think it's
supposed to give that warning.
This patch
On 26/04/14 14:25, Eric Botcazou wrote:
2014-03-21 James Greenhalgh james.greenha...@arm.com
* calls.c (initialize_argument_information): Always treat
PUSH_ARGS_REVERSED as 1, simplify code accordingly.
(expand_call): Likewise.
(emit_library_call_calue_1): Likewise.
*
On 23/04/14 16:20, Alan Lawrence wrote:
This patch is a small tidy of a more-complicated expression that just flips a
single bit and can thus be a simple XOR.
No regressions on aarch64-none-elf or aarch64_be-none-elf. (I've verified
code
is indeed exercised by dg-torture.exp vshuf-v*.c).
On 29/04/14 11:47, dw wrote:
While I'm waiting to hear back from Gerald about my responses to his
other corrections, I have answered one question:
How does the user know what is dialect #0? Same for the others?
When I originally wrote that section, I didn't know the answer (which
is why
On 29/04/14 04:02, bin.cheng wrote:
Hi,
Function output_move_neon now generates vld1.64 for memory ref like dx -
[r1:SI], this is bogus because it requires at least 64-bit alignment for
32-bit aligned memory ref. It works now because GCC doesn't generate such
insns in the first place, but
On 27/02/14 16:38, Charles Baylis wrote:
[resending as text/plain]
Hi
These patches optimise 64 bit division by removing the use of the
__gnu_[u]ldivmod_helper functions and hence avoiding the redundant
calculation of the remainder in those functions.
Bootstrapped, tested and checked
On 24/03/14 17:21, Kyrill Tkachov wrote:
Hi all,
I noticed that we don't handle simple reg-to-reg arithmetic operations in the
arm rtx cost functions. We should be adding the cost of alu.arith to the
costs
of the operands. This patch does that. Since we don't have any cost tables
yet
On 02/05/14 11:28, James Greenhalgh wrote:
On Fri, May 02, 2014 at 10:29:06AM +0100, pins...@gmail.com wrote:
On May 2, 2014, at 2:21 AM, James Greenhalgh james.greenha...@arm.com
wrote:
On Fri, May 02, 2014 at 10:00:15AM +0100, Andrew Pinski wrote:
On Fri, May 2, 2014 at 1:48 AM, James
On 30/04/14 03:52, bin.cheng wrote:
Hi,
This patch expands small memset calls into direct memory set instructions by
introducing setmemsi pattern. For processors without NEON support, it
expands memset using general store instruction. For example, strd for
4-bytes aligned addresses. For
On 05/05/14 09:04, Richard Biener wrote:
On Fri, May 2, 2014 at 12:39 PM, Richard Earnshaw rearn...@arm.com wrote:
On 02/05/14 11:28, James Greenhalgh wrote:
On Fri, May 02, 2014 at 10:29:06AM +0100, pins...@gmail.com wrote:
On May 2, 2014, at 2:21 AM, James Greenhalgh james.greenha
On 07/05/14 11:32, Richard Biener wrote:
On Wed, May 7, 2014 at 12:30 PM, Richard Earnshaw rearn...@arm.com wrote:
On 05/05/14 09:04, Richard Biener wrote:
On Fri, May 2, 2014 at 12:39 PM, Richard Earnshaw rearn...@arm.com wrote:
On 02/05/14 11:28, James Greenhalgh wrote:
On Fri, May 02, 2014
On 28/04/14 14:01, Ramana Radhakrishnan wrote:
On Mon, Apr 28, 2014 at 12:44 PM, Julian Brown jul...@codesourcery.com
wrote:
On Mon, 28 Apr 2014 11:44:01 +0100
Ramana Radhakrishnan ramra...@arm.com wrote:
I've special cased the ffast-math case for the _f32 intrinsics to
prevent
On 08/05/14 19:31, Richard Sandiford wrote:
Joseph S. Myers jos...@codesourcery.com writes:
On Thu, 8 May 2014, Ramana Radhakrishnan wrote:
DATE Ramana Radhakrishnan ramana.radhakrish...@arm.com
* wide-int.cc (UTItype): Define.
(UDWtype): Define for appropriate W_TYPE_SIZE.
On 12/05/14 17:30, Ian Bolton wrote:
Currently, on AArch64, when a caller-save register is saved/restored,
GCC is accessing the maximum size of the hard register.
So an SImode integer (4 bytes) value is being stored as DImode (8 bytes)
because the int registers are 8 bytes wide, and an
On 25/03/14 08:13, Zhenqiang Chen wrote:
Hi
The patch enables shrink-wrap for apcs frame.
Bootstrap and no make check regression in ARM, THUMB1 and THUMB2 modes.
No make check regression with -g/-mapcs/-marm.
Build linux-3.14-rc7 without error.
Is it OK for next stage1?
Thanks!
On 08/05/14 18:36, Ian Bolton wrote:
Hi,
It currently takes 4 instructions to generate certain immediates on
AArch64 (unless we put them in the constant pool).
For example ...
long long
beefcafebabe ()
{
return 0xBEEFCAFEBABEll;
}
leads to ...
mov x0,
A fault in thumb1_reorg means we can try to get the insn_code of
something that isn't an insn. This appears to be a latent problem
that's suddenly started to bite on trunk. The code in question appears
to go back to gcc-4.8.
RTL checking would probably have found this quickly, but that's very
On 16/05/14 14:56, Alexey Merzlyakov wrote:
On 07.05.2014 13:28, Ramana Radhakrishnan wrote:
On 05/07/14 09:19, Yury Gribov wrote:
Original Message
Subject: [PING] [PATCH] Fix for PR libstdc++/60758
Date: Thu, 17 Apr 2014 17:48:12 +0400
From: Alexey Merzlyakov
On 20/05/14 08:57, Richard Biener wrote:
On Tue, 20 May 2014, Maciej W. Rozycki wrote:
Ian,
On Sat, 17 May 2014, Richard Biener wrote:
On May 17, 2014 12:22:23 AM CEST, Maciej W. Rozycki
ma...@codesourcery.com wrote:
On Fri, 16 May 2014, Joseph S. Myers wrote:
2014-05-16 Maciej W.
On 15/05/14 09:47, Kyrill Tkachov wrote:
Hi all,
Shifted arithmetic operations can never be encoded in 16-bits in and
therefore
can not appear in Thumb2 IT blocks under ARMv8-A rules (and the -mrestrict-it
rules). This patch adjusts the relevant pattern for that purpose.
Tested and
On 20/05/14 14:12, Ramana Radhakrishnan wrote:
The following PR is opened for this problem:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61223
Thumb1 failure was also detected and reported in pr60758.
I've proposed a thumb1 bugfix there. Regtest for the fix currently is in
progress.
PR 61208 is a wrong code bug in Thumb2 where we can generate out of
range branches due to incorrect instruction size calculations. It's
mostly gone latent on 4.9 and trunk (though could still happen at -O0
where splitting is done during final instruction generation).
Complicating things slightly
On 21/05/14 16:21, Marcus Shawcroft wrote:
On 15 May 2014 06:54, Kugan kugan.vivekanandara...@linaro.org wrote:
Hi All,
In AArch64 back-end, BASE_REG_CLASS is defined to be POINTER_REGS.
Shouldn’t this be GENERAL_REGS?
Hi Kugan,
Are you aware of any problem caused by BASE_REG_CLASS
On 22/05/14 00:44, Kugan wrote:
Compiling some applications with -mgeneral-regs-only produces better
code (runs faster) compared to not using it. The difference here is that
when -mgeneral-regs-only is not used, floating point register are also
used in register allocation. Then IRA/LRA has to
One of the things that worries me about all the static tuning tables we
have in the compiler is that it is easy to get the order of elements
wrong, especially when adding a lot of new fields to existing
descriptions. This patch attempts to improve the static checking in
this area by making use of
On 27/05/14 15:08, Richard Sandiford wrote:
Hmm, is this because of insn_enabled? If so, how did that work before
the patch? LRA already assumed that the enabled attribute didn't depend
on the operands.
Huh! enabled can be applied to each alternative. Alternatives are
selected based on the
On 27/05/14 15:31, Maciej W. Rozycki wrote:
On Tue, 13 Aug 2013, Kyrylo Tkachov wrote:
On 08/09/13 11:01, Julian Brown wrote:
On Thu, 8 Aug 2013 15:44:17 +0100
Kyrylo Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
The recently added gcc.target/arm/pr58041.c test exposed a bug in the
On 27/05/14 16:27, Jakub Jelinek wrote:
On Tue, May 27, 2014 at 04:15:47PM +0100, Richard Earnshaw wrote:
On 27/05/14 15:08, Richard Sandiford wrote:
Hmm, is this because of insn_enabled? If so, how did that work before
the patch? LRA already assumed that the enabled attribute didn't depend
On 27/05/14 16:50, Jakub Jelinek wrote:
On Tue, May 27, 2014 at 04:40:13PM +0100, Richard Earnshaw wrote:
quote
The @code{enabled} insn attribute may be used to disable certain insn
alternatives for machine-specific reasons.
quote
The rest of the text just says what happens when
On 27/05/14 17:09, Richard Sandiford wrote:
Richard Earnshaw rearn...@arm.com writes:
On 27/05/14 16:27, Jakub Jelinek wrote:
On Tue, May 27, 2014 at 04:15:47PM +0100, Richard Earnshaw wrote:
On 27/05/14 15:08, Richard Sandiford wrote:
Hmm, is this because of insn_enabled? If so, how did
Ah, light dawns (maybe).
I guess the problems stem from the attempts to combine Neon with ARMv5.
Neon shouldn't be used with anything prior to ARMv7, since that's the
earliest version of the architecture that can support it.
I guess that what is happening is that we see we have Neon, so start
On 28/05/14 09:03, Matthew Fortune wrote:
You shouldn't need to declare __builtin_* functions anyway. And if a
function can be represented directly with GNU C vector extensions, it's
preferred to implement it that way inline in the header rather than having
built-in functions duplicating
On 27/05/14 17:31, Richard Sandiford wrote:
Richard Earnshaw rearn...@arm.com writes:
On 27/05/14 17:09, Richard Sandiford wrote:
Richard Earnshaw rearn...@arm.com writes:
On 27/05/14 16:27, Jakub Jelinek wrote:
On Tue, May 27, 2014 at 04:15:47PM +0100, Richard Earnshaw wrote:
On 27/05/14 15
wart still to be handled, though. 'rotate' can only
take an immediate operand, not a register. We can currently deal with
this, but it's not clean in terms of constraint handling. I'll see if I
can fix this up sometime, but not today.
R.
2014-05-29 Richard Earnshaw rearn...@arm.com
On 30/05/14 19:43, Sandra Loosemore wrote:
This execution test specifies -mcpu=cortex-a8 but there is no
corresponding check to make sure that the hardware/simulator being used
to run the test can run cortex-a8 code. (The specific case we tripped
over was in combination with a -mbig-endian
On 05/06/14 14:25, Richard Biener wrote:
The following makes genmatch annotate gimple-match.c with (commented
for now) line directives, similar to other generator programs.
This should help associating generated code with parts in match.pd.
I've often found these annotations more of a
On 04/06/14 07:56, Tony Wang wrote:
Hi there,
In libgcc the file ieee754-sf.S and ieee754-df.S have some function
pairs which will be bundled into one .o file and sharing the same
.text section. For example, the fmul and fdiv, the libgcc makefile
will build them into one .o file and
On 06/06/14 09:50, James Greenhalgh wrote:
Hi,
The move_by_pieces infrastructure performs a copy by repeatedly trying
the largest safe copy it can make. So for a 15-byte copy we might see:
offset amount bytes copied
08 0-7
84 8-11
12 2 12-13
On 06/06/14 16:25, Ramana Radhakrishnan wrote:
On Fri, Jun 6, 2014 at 3:16 PM, Marc Glisse marc.gli...@inria.fr wrote:
Hello,
here is a new try on adding __float128 typeinfo to libsupc++. The front-end
part is based on the discussion with Jason yesterday. The libstdc++ part is
copied from:
On 09/06/14 11:06, Kyrill Tkachov wrote:
Hi all,
The ACLE intrinsics documentation for arm can be improved a bit.
Since there are potentially other ACLE intrinsics besides the CRC32 ones
in the future, I moved the comment about their availability into the
CRC32 intrinsics subsection.
On 11/06/14 10:30, Charles Baylis wrote:
ping?
Sorry, can you resend this as a series of mails, with one patch per mail.
R.
On 22 May 2014 11:08, Charles Baylis charles.bay...@linaro.org wrote:
On 1 May 2014 16:41, Richard Earnshaw rearn...@arm.com wrote:
I think really, you've got three
On 11/06/14 11:19, Charles Baylis wrote:
2014-05-22 Charles Baylis charles.bay...@linaro.org
* config/arm/bpabi.S (__aeabi_uldivmod): Fix whitespace.
(__aeabi_ldivmod): Fix whitespace.
This is OK, but please wait until the others are ready to go in.
R.
---
On 11/06/14 11:19, Charles Baylis wrote:
2014-05-22 Charles Baylis charles.bay...@linaro.org
* config/arm/bpabi.S (__aeabi_uldivmod, __aeabi_ldivmod): Add comment
describing register usage on function entry and exit.
OK.
R.
---
libgcc/config/arm/bpabi.S | 16
On 18/06/14 06:19, Richard Henderson wrote:
Trivial fix for missing clobber of the flags over the tlsdesc call.
Ok for all branches?
OK.
R.
r~
* config/aarch64/aarch64.md (tlsdesc_small_PTR): Clobber CC_REGNUM.
z
diff --git a/gcc/config/aarch64/aarch64.md
1 - 100 of 2570 matches
Mail list logo
