Re: [PATCH][MIPS] Enable load-load/store-store bonding

2014-06-21 Thread Richard Sandiford
Hi Sameera, Thanks for the patch. Sameera Deshpande sameera.deshpa...@imgtec.com writes: diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index b5b5ba7..9804ef2 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -18813,6 +18813,9 @@ mips_option_override (void)

[MIPS, committed] Fix some mips.c warnings

2014-06-22 Thread Richard Sandiford
Fixes unused mode and in_p argument names. Neither mips_move_to_gpr_cost nor mips_move_from_gpr_cost care about the mode now, so I just removed it. Thanks, Richard gcc/ * config/mips/mips.c (mips_move_to_gpr_cost): Remove mode argument. (mips_move_from_gpr_cost): Likewise.

Re: [PATCH][MIPS] Enable load-load/store-store bonding

2014-06-23 Thread Richard Sandiford
Sameera Deshpande sameera.deshpa...@imgtec.com writes: + if (TARGET_FIX_24K TUNE_P5600) +error (unsupported combination: %s, -mtune=p5600 -mfix-24k); + /* Save the base compression state and process flags as though we were generating uncompressed code. */

Re: [patch, mips] delete bit-rotten ADJUST_REG_ALLOC_ORDER definition

2014-06-24 Thread Richard Sandiford
Sandra Loosemore san...@codesourcery.com writes: On 05/14/2014 12:49 PM, Richard Sandiford wrote: Jeff Law l...@redhat.com writes: On 05/13/14 14:11, Sandra Loosemore wrote: 2014-05-13 Catherine Moore c...@codesourcery.com Sandra Loosemore san...@codesourcery.com gcc

Re: [PATCH,MIPS] MIPS64r6 support

2014-06-24 Thread Richard Sandiford
Matthew Fortune matthew.fort...@imgtec.com writes: I suppose we'll need a way of specifying an isa_rev range, say isa_rev=2-5. That should be a fairly localised change though. There appear to be about 9 tests that are not fixed by educating mips.exp about flags which are not supported on R6.

Re: Instructions vs Expressions in the backend (was Re: RFA: Rework FOR_BB_INSNS iterators)

2014-06-25 Thread Richard Sandiford
David Malcolm dmalc...@redhat.com writes: On Mon, 2014-06-09 at 20:32 +0100, Richard Sandiford wrote: Steven Bosscher stevenb@gmail.com writes: On Sat, Jun 7, 2014 at 7:54 PM, Richard Sandiford wrote: The two parts of the loop condition are really handling two different kinds of block

Re: Instructions vs Expressions in the backend (was Re: RFA: Rework FOR_BB_INSNS iterators)

2014-06-25 Thread Richard Sandiford
Oleg Endo oleg.e...@t-online.de writes: Personally, I'd like to see usage of standard STL-like iterator usage. I've proposed something for edge_iterator a while ago, but people don't seem very fond of it. See also https://gcc.gnu.org/ml/gcc-patches/2013-12/msg01129.html Have you also

Re: [PATCH] Fix high handling in wi::mul_internal (PR tree-optimization/61682)

2014-07-03 Thread Richard Sandiford
Jakub Jelinek ja...@redhat.com writes: @@ -1302,12 +1310,28 @@ wi::mul_internal (HOST_WIDE_INT *val, co /* Handle multiplications by 1. */ if (op1 == 1) { + if (high) + { + if (sgn == SIGNED wi::neg_p (op2)) + val[0] = -1; + else + val[0]

Re: Simplify gcc.target/mips/fuse-caller-save*.c

2014-07-09 Thread Richard Sandiford
Tom de Vries tom_devr...@mentor.com writes: Richard, during testing the gcc.target/mips/fuse-caller-save*.c test-cases with more combinations of -march, -mabi, -fpic etc, I found that the checks for amount of stores are rather fragile, so I removed them in this patch. Which combinations

Re: Simplify gcc.target/mips/fuse-caller-save*.c

2014-07-10 Thread Richard Sandiford
Tom de Vries tom_devr...@mentor.com writes: The mips16e save/restore enabling is controlled by this code in mips.h: ... /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */ #define GENERATE_MIPS16E(TARGET_MIPS16 mips_isa = 32) /* Generate mips16e register

Re: [MIPS r5900] libgcc floating point fixes

2014-07-14 Thread Richard Sandiford
J├╝rgen Urban juergenur...@gmx.de writes: The problem happens with the r5900 hard float configurations, e.g.: configure --target=mipsel-linux-gnu --with-float=hard --with-fpu=single --with-arch=r5900 I created the attached patch which fixes this problem for r5900 and another problem explained

Re: Delay RTL initialization until it is really needed

2014-07-16 Thread Richard Sandiford
Jan Hubicka hubi...@ucw.cz writes: Hi, IRA initialization shows high in profiles even when building lto objects. This patch simply delays RTL backend initialization until we really decide to output a function. In some cases this avoids the initialization completely (like in the case of LTO

Re: Delay RTL initialization until it is really needed

2014-07-16 Thread Richard Sandiford
Jan Hubicka hubi...@ucw.cz writes: Index: gcc/toplev.c === --- gcc/toplev.c 2014-07-11 11:54:41.604838961 +0100 +++ gcc/toplev.c 2014-07-16 08:22:36.226034738 +0100 @@ -1604,6 +1604,10 @@ backend_init_target (void)

PR61629 (was Re: Delay RTL initialization until it is really needed)

2014-07-17 Thread Richard Sandiford
Richard Sandiford rdsandif...@googlemail.com writes: Jan Hubicka hubi...@ucw.cz writes: Hi, IRA initialization shows high in profiles even when building lto objects. This patch simply delays RTL backend initialization until we really decide to output a function. In some cases this avoids

[committed] Fix umips-lwp-*.c tests

2014-07-17 Thread Richard Sandiford
umips-lwp-[1234].c test that two loads from consecutive memory locations to consecutive registers ($5 and $6) can use LWP. The idea was to have 2 tests where $5 was loaded first before $6 and 2 tests that were the other way around (at least when scheduling is enabled). I'd tried to force that by

[committed] Fix MIPS p5600 scheduler

2014-07-17 Thread Richard Sandiford
The p5600 scheduler wasn't restricting itself to -mtune=p5600 and so was being used for other CPUs too. This showed up as a failure in various tests, including gcc.target/mips/octeon-pipe-1.c. (Thinking about it, it was probably also why umips-lwp-*.c started failing, although the patch I just

PR 61628: Invalid sharing of DECL_INCOMING_RTL

2014-07-18 Thread Richard Sandiford
My patch to reduce the amount of rtx garbage created: 2014-05-17 Richard Sandiford rdsandif...@googlemail.com * emit-rtl.h (replace_equiv_address, replace_equiv_address_nv): Add an inplace argument. Store the new address in the original MEM when true. * emit-rtl.c

Re: [PATCH, rs6000] Fix PR61542 - V4SF vector extract for little endian

2014-07-18 Thread Richard Sandiford
Bill Schmidt wschm...@linux.vnet.ibm.com writes: Bernd, thanks. At this point I think I will avoid opening this can of worms and not worry about backporting the test case. Sorry for the late answer (catching up on a big backlog), but the testcase was originally added for an optimisation rather

RFA: Tweak RA cost calculation for -O0

2014-07-19 Thread Richard Sandiford
IRA (like the old allocators) calculates a best class and an alternative class for each allocno. The best class is the one with the lowest cost while the alternative class is the biggest class whose cost is smaller than the cost of spilling. When optimising we adjust the costs so that the best

Ping: PR61629 (was Re: Delay RTL initialization until it is really needed)

2014-07-24 Thread Richard Sandiford
Ping. Originaly message was here: https://gcc.gnu.org/ml/gcc-patches/2014-07/msg01113.html Richard Sandiford rdsandif...@googlemail.com writes: Richard Sandiford rdsandif...@googlemail.com writes: Jan Hubicka hubi...@ucw.cz writes: Hi, IRA initialization shows high in profiles even when

Re: PR 61628: Invalid sharing of DECL_INCOMING_RTL

2014-07-24 Thread Richard Sandiford
Ping. Original message was here: https://gcc.gnu.org/ml/gcc-patches/2014-07/msg01267.html Richard Sandiford rdsandif...@googlemail.com writes: My patch to reduce the amount of rtx garbage created: 2014-05-17 Richard Sandiford rdsandif...@googlemail.com * emit-rtl.h

RFA: Add a common tls_referenced_p function

2014-07-24 Thread Richard Sandiford
Three targets had the same for_each_rtx function to check for a TLS symbol. This patch adds a generic version instead. Some other targets have a variation that checks for target-specific UNSPEC sequences too so I've left those alone. They're all prefixed by the target name so there's no name

[MIPS, committed] Reverse argument order in const-anchor tests

2014-07-27 Thread Richard Sandiford
gcc.target/mips/const-anchor-[12].c started failing after: 2014-04-29 James Greenhalgh james.greenha...@arm.com * calls.c (initialize_argument_information): Always treat PUSH_ARGS_REVERSED as 1, simplify code accordingly. (expand_call): Likewise.

PR61919: Invalid rtx sharing in tree-outof-ssa.c

2014-07-27 Thread Richard Sandiford
PR 61919 is another ripple from the patch to take advantage of rtx sharing rules when instantiating virtual registers. In this case the invalid sharing is coming from tree-outof-ssa.c, where the same MEM rtx is being used in several moves. (Note that despite the name, partition_to_pseudo maps to

[committed] Remove my MIPS maintainer entry

2014-07-27 Thread Richard Sandiford
port Richard Sandiford rdsandif...@googlemail.com mmix port Hans-Peter Nilsson h...@bitrange.com mn10300 port Jeff Lawl...@redhat.com mn10300 port Alexandre Oliva aol...@redhat.com

Re: Warn when returning the address of a temporary (middle-end) v2

2014-07-27 Thread Richard Sandiford
Marc Glisse marc.gli...@inria.fr writes: Hello, I followed the advice in this discussion: https://gcc.gnu.org/ml/gcc-patches/2014-04/msg00269.html and here is a new patch. I made an effort to isolate a path in at least one subcase so it doesn't look too strange that the warning is in this

Remove for_each_rtx

2014-11-11 Thread Richard Sandiford
There are no more callers to for_each_rtx or for_each_rtx_in_insn, so this patch removes the functions. Tested on x86_64-linux-gnu. OK to install? Thanks, Richard gcc/ * rtl.h (rtx_function, for_each_rtx, for_each_rtx_in_insn): Delete. * rtlanal.c (non_rtx_starting_operands,

Re: [PATCH] Fix optimize_range_tests_diff

2014-11-18 Thread Richard Sandiford
Jakub Jelinek ja...@redhat.com writes: On Tue, Oct 14, 2014 at 11:23:22AM -0600, Jeff Law wrote: On 10/14/14 10:02, Jakub Jelinek wrote: When hacking on range reassoc opt, I've noticed we can emit code with undefined behavior even when there wasn't one originally, in particular for: (X -

Re: [PATCH] Fix ICEs in simplify_immed_subreg on OImode/XImode subregs (PR target/63910)

2014-11-19 Thread Richard Sandiford
Jakub Jelinek ja...@redhat.com writes: On Wed, Nov 19, 2014 at 09:59:45AM +0100, Richard Biener wrote: OImode/XImode on i?86/x86_64 are not = MAX_BITSIZE_MODE_ANY_INT, because they are never used for integer arithmetics (and there is no way to represent all their values in RTL if not using

Re: [PATCH] Fix ICEs in simplify_immed_subreg on OImode/XImode subregs (PR target/63910)

2014-11-20 Thread Richard Sandiford
Jakub Jelinek ja...@redhat.com writes: On Wed, Nov 19, 2014 at 02:23:47PM -0800, Mike Stump wrote: On Nov 19, 2014, at 1:57 PM, Jakub Jelinek ja...@redhat.com wrote: Though, following patch is just fine for me too, I don't think it will make a significant difference: This version is fine

Re: [PATCH] If using branch likelies in MIPS sync code fill the delay slot with a nop

2014-11-26 Thread Richard Sandiford
FWIW, I agree this is the right fix, but: Andrew Bennett andrew.benn...@imgtec.com writes: + /* When using branch likely (-mfix-r1), the delay slot instruction + will be annulled on false. The normal delay slot instructions + calculate the overall result of the atomic operation

Re: path fixing PPC bootstrap

2014-11-27 Thread Richard Sandiford
Vladimir Makarov vmaka...@redhat.com writes: Mike Meissner pointed me out that my last patch broke PPC bootstrap. I submitted a quick fix for it and now I am sending the path after bootstrap on ppc is done successfully. Sorry for the inconvinience. 2014-11-25 Vladimir Makarov

Re: RFA: one more version of the patch for PR61360

2014-09-27 Thread Richard Sandiford
Hi Vlad, Vladimir Makarov vmaka...@redhat.com writes: I guess we achieved the consensus about the following patch to fix PR61360 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61360 The patch was successfully bootstrapped and tested (w/wo -march=amdfam10) on x86/x86-64. Is it ok to commit

Re: Fix for FAIL: tmpdir-gcc.dg-struct-layout-1/t028 c_compat_x_tst.o compile, (internal compiler error)

2014-09-30 Thread Richard Sandiford
David Sherwood david.sherw...@arm.com writes: @@ -1859,9 +1861,11 @@ static basic_block curr_bb; /* This recursive function creates allocnos corresponding to pseudo-registers containing in X. True OUTPUT_P means that X is - a lvalue. */ + a lvalue. The 'parent' parameter

Re: Fix for FAIL: tmpdir-gcc.dg-struct-layout-1/t028 c_compat_x_tst.o compile, (internal compiler error)

2014-09-30 Thread Richard Sandiford
Andreas Schwab sch...@suse.de writes: Richard Sandiford richard.sandif...@arm.com writes: @@ -315,7 +318,7 @@ struct ira_allocno number (0, ...) - 2. Value -1 is used for allocnos spilled by the reload (at this point pseudo-register has only one allocno) which did not get

[PATCH 1/2] PR 63340: Avoid harmful union classes in ira-costs.c

2014-09-30 Thread Richard Sandiford
This patch is the first of two to fix PR 63340, which is an ia64 regression caused by: 2014-09-22 Richard Sandiford richard.sandif...@arm.com * hard-reg-set.h: Include hash-table.h. (target_hard_regs): Add a finalize method and a x_simplifiable_subregs field

[PATCH 2/2] PR 63340: Avoid harmful union classes in ira-costs.c

2014-09-30 Thread Richard Sandiford
This part of the patch actually fixes the PR. It takes the reginfo.c invalid mode changes into account when computing the cost classes, rather than when using them. The code in the first patch then ensures that we don't add X_AND_Y_REGS to the cost classes if only X or Y allow the required mode

Re: parallel check output changes?

2014-10-02 Thread Richard Sandiford
Segher Boessenkool seg...@kernel.crashing.org writes: On Wed, Sep 24, 2014 at 10:54:57AM -0400, Andrew MacLeod wrote: Is this suppose to be resolved now? I'm still seeing some issues with a branch cut from mainline from yesterday. Confirmed. The following patch works for me, and Andrew has

Re: Fix for FAIL: tmpdir-gcc.dg-struct-layout-1/t028 c_compat_x_tst.o compile, (internal compiler error)

2014-10-03 Thread Richard Sandiford
David Sherwood david.sherw...@arm.com writes: Hi Andreas, OK, I will fix this. I installed David's patch below as obvious. Tested on x86_64-linux-gnu. Thanks, Richard gcc/ 2014-10-03 David Sherwood david.sherw...@arm.com * ira-int.h (ira_allocno): Mark hard_regno as signed.

Re: parallel check output changes?

2014-10-04 Thread Richard Sandiford
Jakub Jelinek ja...@redhat.com writes: make the result of combining separate .sum files the same as the .sum file you'd get for -j1. As Jakub said upthread, that's a lost cause with the new approach to parallel testing, but I think the comment was valid while matching -j1 was still a goal.

Re: RFA: one more version of the patch for PR61360

2014-10-04 Thread Richard Sandiford
Uros Bizjak ubiz...@gmail.com writes: On Thu, Oct 2, 2014 at 10:13 PM, Vladimir Makarov vmaka...@redhat.com wrote: I guess we achieved the consensus about the following patch to fix PR61360 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61360 The patch was successfully bootstrapped and

Re: RFA: one more version of the patch for PR61360

2014-10-04 Thread Richard Sandiford
Uros Bizjak ubiz...@gmail.com writes: On Sat, Oct 4, 2014 at 12:49 PM, Richard Sandiford rdsandif...@googlemail.com wrote: Uros Bizjak ubiz...@gmail.com writes: On Thu, Oct 2, 2014 at 10:13 PM, Vladimir Makarov vmaka...@redhat.com wrote: I guess we achieved the consensus about the following

Re: [RFC] costs and it's use in assign_reg_parm

2014-10-05 Thread Richard Sandiford
Ramana Radhakrishnan ramana.radhakrish...@arm.com writes: Hi, I've been digging into why on AArch64 we generate pretty bad code for the following testcase. void g2(float, float, float, float, float, float, float, float); void f2a(void) { float x0 = 1.0, x1 = 2.0, x2 = 3.0, x3 =

Re: RFA: Merge definitions of get_some_local_dynamic_name

2014-10-06 Thread Richard Sandiford
Rainer Orth r...@cebitec.uni-bielefeld.de writes: Hi Richard, Rainer Orth r...@cebitec.uni-bielefeld.de writes: Hi Richard, It seems the new get_some_local_dynamic_name implementation in function.c lost the non-NULL check the sparc.c version had. I'm currently testing the following patch:

Re: RFA: Merge definitions of get_some_local_dynamic_name

2014-10-07 Thread Richard Sandiford
Richard Sandiford rdsandif...@googlemail.com writes: Rainer Orth r...@cebitec.uni-bielefeld.de writes: Hi Richard, Rainer Orth r...@cebitec.uni-bielefeld.de writes: Hi Richard, It seems the new get_some_local_dynamic_name implementation in function.c lost the non-NULL check the sparc.c

Re: RFA: Merge definitions of get_some_local_dynamic_name

2014-10-08 Thread Richard Sandiford
Rainer Orth r...@cebitec.uni-bielefeld.de writes: Hi Richard, Does this work for you? I tested it on x86_64-linux-gnu but obviously that's not particularly useful for SEQUENCEs. the patch is fine, as tested on both sparc-sun-solaris2.11 and (for good measure) i386-pc-solaris2.11. OK,

[PATCH 0/5] Add preferred_for_{size,speed} attributes

2014-10-17 Thread Richard Sandiford
This patch implements the approach I suggested in: https://gcc.gnu.org/ml/gcc-patches/2014-10/msg00371.html for fixing PR61360. To recap, the problem is with the use of enabled in the i386.md pattern: (define_insn *floatSWI48:modeMODEF:mode2_sse [(set (match_operand:MODEF 0

[PATCH 1/5] Add recog_constrain_insn

2014-10-17 Thread Richard Sandiford
This patch just adds a new utility function called recog_constrain_insn, to go alongside the existing recog_constrain_insn_cached. Note that the extract_insn in lra.c wasn't used when checking is disabled. The function just moved on to the next instruction straight away. Richard gcc/ *

[PATCH 2/5] Add preferred_for_{size,speed} attributes

2014-10-17 Thread Richard Sandiford
This is the main patch, to add new preferred_for_size and preferred_for_speed attributes that can be used to selectively disable alternatives when optimising for size or speed. As explained in the docs, the new attributes are just optimisation hints and it is possible that size-only alternatives

[PATCH 3/5] Pass an alternative_mask to constrain_operands

2014-10-17 Thread Richard Sandiford
After the previous patch there are cases where we want to constrain operands to any enabled alternative and cases where we want to also take size/speed preferences into account. The former applies when constraining an existing instruction (which might originally have been in a block with a

[PATCH 4/5] Remove recog_data.enabled_alternatives

2014-10-17 Thread Richard Sandiford
After the previous patches, this one gets rid of recog_data.enabled_alternatives and its one remaining use. Richard gcc/ * recog.h (recog_data_d): Remove enabled_alternatives. * recog.c (extract_insn): Don't set it. * reload.c (find_reloads): Call

[PATCH 5/5] Use preferred_for_speed in i386.md

2014-10-17 Thread Richard Sandiford
Undo the original fix for 61630 and use preferred_for_speed in the problematic pattern. I've not written many gcc.target/i386 tests so the markup might need some work. Richard gcc/ * lra.c (lra): Remove call to recog_init. * config/i386/i386.md (preferred_for_speed): New

Re: [PATCH] Account for prologue spills in reg_pressure scheduling

2014-10-20 Thread Richard Sandiford
Maxim Kuvyrkov maxim.kuvyr...@linaro.org writes: [Adding ARM maintainers to CC] On Oct 21, 2014, at 9:44 AM, Sebastian Pop seb...@gmail.com wrote: Hi Maxim, Maxim Kuvyrkov wrote: Thanks, benchmarking results are welcome! AArch64 doesn't use reg_pressure scheduling by default. Use

Re: [PATCH 6/8] Handle SCRATCH in decompose_address

2014-10-21 Thread Richard Sandiford
Maxim Kuvyrkov maxim.kuvyr...@linaro.org writes: This patch is a simple fix to allow decompose_address to handle SCRATCH'es during 2nd scheduler pass. This patch is a prerequisite for a scheduler improvement that relies on decompose_address to parse insns. Bootstrapped and regtested on

Re: [PATCH 8/8] Use rank_for_schedule to as tie-breaker in model_order_p

2014-10-21 Thread Richard Sandiford
Maxim Kuvyrkov maxim.kuvyr...@linaro.org writes: This patch improves model_order_p to use non-reg-pressure version of rank_for_schedule when it needs to break the tie. At the moment it is comparing INSN_PRIORITY by itself, and it seems prudent to outsource that to rank_for_schedule. Do you

Re: [RFA][PATCH][pr target/60648] Fix non-canonical RTL from x86 backend -- P1 regression

2014-03-26 Thread Richard Sandiford
Richard Henderson r...@redhat.com writes: On 03/26/2014 12:40 PM, Jakub Jelinek wrote: On Wed, Mar 26, 2014 at 01:32:44PM -0600, Jeff Law wrote: On 03/26/14 12:28, Jakub Jelinek wrote: (mult:SI (const_int 0) (const_int 4)) is IMHO far from being canonical. And, I'd say it is likely other

Re: [RFC][PATCH][MIPS] Patch to enable LRA for MIPS backend

2014-03-29 Thread Richard Sandiford
First of all, thanks a lot for doing this. Robert Suchanek robert.sucha...@imgtec.com writes: diff --git gcc/config/mips/mips.c gcc/config/mips/mips.c index 143169b..f27a801 100644 --- gcc/config/mips/mips.c +++ gcc/config/mips/mips.c @@ -2255,7 +2255,7 @@ mips_regno_mode_ok_for_base_p (int

Re: [C PATCH] Warn if inline attributes conflict (PR c/18079)

2014-03-30 Thread Richard Sandiford
Marek Polacek pola...@redhat.com writes: @@ -,7 +,16 @@ handle_noinline_attribute (tree *node, tree name, int ARG_UNUSED (flags), bool *no_add_attrs) { if (TREE_CODE (*node) == FUNCTION_DECL) -DECL_UNINLINABLE (*node) = 1; +{ + if

PR 60604: CANNOT_CHANGE_MODE_CLASS being ignored

2014-03-31 Thread Richard Sandiford
PR 60604 shows a case where CANNOT_CHANGE_MODE_CLASS is being ignored for a subreg of a floating-point register, causing it to be replaced with an invalid (reg ...). There are various reasons why MIPS floating-point registers can't change mode, but one important one for big-endian 32-bit targets

Re: Lost __mips_o32 predefine on NetBSD

2014-03-31 Thread Richard Sandiford
Martin Husemann mar...@duskware.de writes: In the mips--netbsdelf target gcc 4.9 lost the pre-definition of __mips_o32, which is heavily used in NetBSD sources. The obvious trivial patch adds it back. Are you sure it was ever in FSF GCC? I went through every revision of netbsd.h in git and

Re: Lost __mips_o32 predefine on NetBSD

2014-04-01 Thread Richard Sandiford
Martin Husemann mar...@duskware.de writes: On Mon, Mar 31, 2014 at 08:35:30PM +0100, Richard Sandiford wrote: Are you sure it was ever in FSF GCC? I went through every revision of netbsd.h in git and couldn't see it. No, I'm not - guess I never tried a pure gcc on mips. I can go ahead

[committed] PR60763: POWER8 fallout from PR60604

2014-04-08 Thread Richard Sandiford
The patch for PR60604 stopped nonimmediate_operand from accepting (subreg:M (reg:N R)) for combinations that are forbidden by REG_CANNOT_CHANGE_MODE_P, to match the existing register_operand behaviour. This stopped rs6000's movdi pattern from accepting such subregs as a destination (they were

Re: [RFC][PATCH][MIPS] Patch to enable LRA for MIPS backend

2014-04-09 Thread Richard Sandiford
Robert Suchanek robert.sucha...@imgtec.com writes: FYI, all other targets that have LRA optionally selectable or deselectable use -mno-lra for this (even when -mlra is the default), it would be better for consistency not to invent new switch names for that. Agreed. -return !strict_p ||

Re: [RFC][PATCH][MIPS] Patch to enable LRA for MIPS backend

2014-04-10 Thread Richard Sandiford
Richard Sandiford rdsandif...@googlemail.com writes: Robert Suchanek robert.sucha...@imgtec.com writes: I'm not particularly happy with this either. This was an attempt to fix an ICE for the following RTL (gcc.dg/torture/asm-subreg-1.c compiled with -mips32r2 -mips16 -O1): (insn 9 8 0 2

Re: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and SB16

2014-04-12 Thread Richard Sandiford
Matthew Fortune matthew.fort...@imgtec.com writes: Hi Catherine/Richard, I think there may be some impact on register move costs by introducing this class. Yeah, I was worried about that too. I'm going to do some code comparison tests for SE and MIPS16 to see what happens. Is it worth

Re: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and SB16

2014-04-12 Thread Richard Sandiford
Richard Sandiford rdsandif...@googlemail.com writes: Matthew Fortune matthew.fort...@imgtec.com writes: Hi Catherine/Richard, I think there may be some impact on register move costs by introducing this class. Yeah, I was worried about that too. I'm going to do some code comparison tests

Re: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and SB16

2014-04-14 Thread Richard Sandiford
Moore, Catherine catherine_mo...@mentor.com writes: Adding a new register class is definitely a bit invasive for this stage of 4.9. OTOH microMIPS is a new feature and it would be good to have it working in 4.9.0. Since the testing suggests that the patch really doesn't affect non- microMIPS

Re: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and SB16

2014-04-15 Thread Richard Sandiford
Maciej W. Rozycki ma...@codesourcery.com writes: On Sat, 12 Apr 2014, Richard Sandiford wrote: I went ahead and applied the adjusted version of the patch to trunk as below (because I wanted to add a testcase too). I believe you need to adjust constraints to ensure constant 0 is known

Re: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and SB16

2014-04-15 Thread Richard Sandiford
Moore, Catherine catherine_mo...@mentor.com writes: -Original Message- From: Moore, Catherine Sent: Tuesday, April 15, 2014 8:49 AM To: Rozycki, Maciej; Richard Sandiford Cc: Matthew Fortune; gcc-patches@gcc.gnu.org; Moore, Catherine Subject: RE: [PATCH] [MIPS] Fix operands

RFA: Tighten checking for 'X' constraints

2014-04-15 Thread Richard Sandiford
As Robert pointed out here: http://gcc.gnu.org/ml/gcc-patches/2014-04/msg00416.html we're a bit too eager when folding stuff into an 'X' constraint. The value at expand time is sensible, but after that asm_operand_ok allows arbitrary rtx expressions, including any number of registers as well

Re: [RFC][PATCH][MIPS] Patch to enable LRA for MIPS backend

2014-04-15 Thread Richard Sandiford
Robert Suchanek robert.sucha...@imgtec.com writes: Hmm, marking them fixed was supposed to be a temporary reload-only thing, until the move to LRA. It should never be worse to spill to these GPRs over spilling to the stack, if the value isn't live across a call. I would say this also affects

Re: [PATCH] pedantic warning behavior when casting void* to ptr-to-func, 4.8 and 4.9

2014-04-15 Thread Richard Sandiford
cc:ing Jason, who's the C++ maintainer. Daniel Gutson daniel.gut...@tallertechnologies.com writes: ping for maintainer. Could this be considered for 4.8.3 please? Thanks, Daniel. On Tue, Apr 1, 2014 at 2:46 PM, Daniel Gutson daniel.gut...@tallertechnologies.com wrote: I just

Re: [PATCH] register CALL_INSN_FUNCTION_USAGE in find_all_hard_reg_sets

2014-04-16 Thread Richard Sandiford
Tom de Vries tom_devr...@mentor.com writes: On 16-01-14 09:13, Richard Sandiford wrote: Tom de Vries tom_devr...@mentor.com writes: * The set of registers which are clobbered during a call by things like the plt - these are not picked up by the use-caller-save optimization. We need

Re: RFA: Tighten checking for 'X' constraints

2014-04-16 Thread Richard Sandiford
Jakub Jelinek ja...@redhat.com writes: On Tue, Apr 15, 2014 at 09:53:16PM +0100, Richard Sandiford wrote: As Robert pointed out here: http://gcc.gnu.org/ml/gcc-patches/2014-04/msg00416.html we're a bit too eager when folding stuff into an 'X' constraint. The value at expand time

Re: RFA: Tighten checking for 'X' constraints

2014-04-16 Thread Richard Sandiford
Andrew Pinski pins...@gmail.com writes: On Tue, Apr 15, 2014 at 1:53 PM, Richard Sandiford rdsandif...@googlemail.com wrote: As Robert pointed out here: http://gcc.gnu.org/ml/gcc-patches/2014-04/msg00416.html we're a bit too eager when folding stuff into an 'X' constraint. The value

Re: [PATCH] register CALL_INSN_FUNCTION_USAGE in find_all_hard_reg_sets

2014-04-16 Thread Richard Sandiford
Jakub Jelinek ja...@redhat.com writes: On Wed, Apr 16, 2014 at 11:46:14AM +0200, Tom de Vries wrote: ...why do we need two different mechanisms to deal with these two? IMO the set recorded for the callee should contain what the callee instructions clobber and nothing else.

Re: [PATCH] register CALL_INSN_FUNCTION_USAGE in find_all_hard_reg_sets

2014-04-16 Thread Richard Sandiford
Tom de Vries tom_devr...@mentor.com writes: On 16/04/14 12:28, Richard Sandiford wrote: This patch introduces a hook that specifies which registers are implicitly clobbered by a call, not including the registers that are clobbered in the called function, and then uses that hook

Re: RFA: Tighten checking for 'X' constraints

2014-04-16 Thread Richard Sandiford
Jakub Jelinek ja...@redhat.com writes: On Wed, Apr 16, 2014 at 11:43:12AM +0100, Richard Sandiford wrote: X was defined against reload, which always reloaded MEM addresses to follow the appropriate base and index register classes. This was done as a first pass before matching against

Re: RFA: Tighten checking for 'X' constraints

2014-04-16 Thread Richard Sandiford
Eric Botcazou ebotca...@adacore.com writes: Anyway, others can have different opinion on what X should mean, CCing Jeff and Eric. I personally think that we should not change it and adjust LRA instead to error out instead of ICEing (even if this means erroring out in a few more cases with

Re: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and SB16

2014-04-16 Thread Richard Sandiford
Moore, Catherine catherine_mo...@mentor.com writes: -Original Message- From: Richard Sandiford [mailto:rdsandif...@googlemail.com] Sent: Tuesday, April 15, 2014 4:32 PM To: Moore, Catherine Cc: Rozycki, Maciej; Matthew Fortune; gcc-patches@gcc.gnu.org Subject: Re: [PATCH] [MIPS] Fix

Re: fuse-caller-save - hook format

2014-04-16 Thread Richard Sandiford
Tom de Vries tom_devr...@mentor.com writes: Vladimir, All patches for the fuse-caller-save optimization have been ok-ed. The only part not approved is the MIPS-specific part. The objection of Richard S. is not so much the patch itself, but more the idea of the hook

Re: fuse-caller-save - hook format

2014-04-17 Thread Richard Sandiford
Vladimir Makarov vmaka...@redhat.com writes: On 2014-04-16, 3:19 PM, Tom de Vries wrote: Vladimir, All patches for the fuse-caller-save optimization have been ok-ed. The only part not approved is the MIPS-specific part. The objection of Richard S. is not so much the patch itself, but

RFA: tweak integer type used for memcpy folding

2014-04-19 Thread Richard Sandiford
wide-int fails to build libitm because of a bad interaction between: /* Keep the OI and XI modes from confusing the compiler into thinking that these modes could actually be used for computation. They are only holders for vectors during data movement. */ #define MAX_BITSIZE_MODE_ANY_INT

Re: RFA: Tighten checking for 'X' constraints

2014-04-19 Thread Richard Sandiford
Jeff Law l...@redhat.com writes: On 04/16/14 07:37, Jakub Jelinek wrote: Creating a (mem (scratch)) too early may pessimize code too much, perhaps it can be used during say sched1 etc. for alias analysis, (mem (scratch)) is considered to alias everything,. Plus, I think at least so far we

Re: [RFC][PATCH][MIPS] Patch to enable LRA for MIPS backend

2014-04-21 Thread Richard Sandiford
Robert Suchanek robert.sucha...@imgtec.com writes: Did you see the failures even after your mips_regno_mode_ok_for_base_p change? LRA should know how to reload a W address. Yes but I realize there is more. It fails because $sp is now included in BASE_REG_CLASS and W is based on it.

Re: RFA: tweak integer type used for memcpy folding

2014-04-22 Thread Richard Sandiford
Richard Sandiford rdsandif...@googlemail.com writes: wide-int fails to build libitm because of a bad interaction between: /* Keep the OI and XI modes from confusing the compiler into thinking that these modes could actually be used for computation. They are only holders for vectors

Re: [PATCH 00/89] Compile-time gimple-checking

2014-04-22 Thread Richard Sandiford
First of all, thanks a lot for doing this. Maybe one day we'll have the same in rtl :-) But... David Malcolm dmalc...@redhat.com writes: In doing the checked downcasts I ran into the verbosity of the as_a API (in our is-a.h). I first tried simplifying them with custom functions e.g.:

Re: [PATCH] Simplify a VEC_SELECT fed by its own inverse

2014-04-22 Thread Richard Sandiford
Marc Glisse marc.gli...@inria.fr writes: On Mon, 21 Apr 2014, Richard Henderson wrote: On 04/21/2014 01:19 PM, Bill Schmidt wrote: + if (GET_CODE (trueop0) == VEC_SELECT + GET_MODE (XEXP (trueop0, 0)) == mode) + { + rtx op0_subop1 = XEXP (trueop0, 1); + gcc_assert

Re: RFA: tweak integer type used for memcpy folding

2014-04-22 Thread Richard Sandiford
Richard Biener richard.guent...@gmail.com writes: On Sat, Apr 19, 2014 at 9:51 AM, Richard Sandiford rdsandif...@googlemail.com wrote: wide-int fails to build libitm because of a bad interaction between: /* Keep the OI and XI modes from confusing the compiler into thinking

Re: RFA: tweak integer type used for memcpy folding

2014-04-22 Thread Richard Sandiford
Richard Biener richard.guent...@gmail.com writes: On Tue, Apr 22, 2014 at 10:43 AM, Richard Sandiford rdsandif...@googlemail.com wrote: Richard Biener richard.guent...@gmail.com writes: On Sat, Apr 19, 2014 at 9:51 AM, Richard Sandiford rdsandif...@googlemail.com wrote: wide-int fails

Re: RFA: tweak integer type used for memcpy folding

2014-04-22 Thread Richard Sandiford
Richard Biener richard.guent...@gmail.com writes: On Tue, Apr 22, 2014 at 11:15 AM, Richard Sandiford rdsandif...@googlemail.com wrote: Richard Biener richard.guent...@gmail.com writes: On Tue, Apr 22, 2014 at 10:43 AM, Richard Sandiford rdsandif...@googlemail.com wrote: Richard Biener

Re: fuse-caller-save - hook format

2014-04-22 Thread Richard Sandiford
Tom de Vries tom_devr...@mentor.com writes: 2. post_expand_call_insn. A utility hook to facilitate adding the clobbers to CALL_INSN_FUNCTION_USAGE. Why is this needed though? Like I say, I think targets should update CALL_INSN_FUNCTION_USAGE when emitting calls as part of the call expander.

Re: [PATCH][RFC][wide-int] Fix some build errors on arm in wide-int branch and report ICE

2014-04-22 Thread Richard Sandiford
Kyrill Tkachov kyrylo.tkac...@arm.com writes: Ping. http://gcc.gnu.org/ml/gcc-patches/2014-04/msg00769.html Any ideas? I recall chatter on IRC that we want to merge wide-int into trunk soon. Bootstrap failure on arm would prevent that... Sorry for the late reply. I hadn't forgotten, but I

Re: fuse-caller-save - hook format

2014-04-22 Thread Richard Sandiford
Tom de Vries tom_devr...@mentor.com writes: On 22-04-14 17:27, Richard Sandiford wrote: Tom de Vries tom_devr...@mentor.com writes: 2. post_expand_call_insn. A utility hook to facilitate adding the clobbers to CALL_INSN_FUNCTION_USAGE. Why is this needed though? Like I say, I think

Re: [PATCH 00/89] Compile-time gimple-checking

2014-04-22 Thread Richard Sandiford
David Malcolm dmalc...@redhat.com writes: Alternatively we could change the is-a.h API to eliminate this discrepancy, and keep the typedefs; giving something like the following: static void dump_gimple_switch (pretty_printer *buffer, gimple_switch gs, int spc, int

[wide-int 1/8] Fix some off-by-one errors and bounds tests

2014-04-22 Thread Richard Sandiford
This is the first of 8 patches from reading through the diff with mainline. Some places had an off-by-one error on an index and some used = 0 instead of = 0. I think we should use MAX_BITSIZE_MODE_ANY_MODE rather than MAX_BITSIZE_MODE_ANY_INT when handling floating-point modes. Two hunks contain

[wide-int 2/8] Fix ubsan internal-fn.c handling

2014-04-22 Thread Richard Sandiford
This code was mixing hprec and hprec*2 wide_ints. The simplest fix seemed to be to introduce a function that gives the minimum precision necessary to represent a function, which also means that no temporary wide_ints are needed. Other places might be able to use this too, but I'd like to look at

[wide-int 3/8] Add and use udiv_ceil

2014-04-22 Thread Richard Sandiford
Just a minor tweak to avoid several calculations when one would do. Since we have a function for rounded-up division, we might as well use it instead of the (X + Y - 1) / Y idiom. Tested on x86_64-linux-gnu. OK to install? Thanks, Richard Index: gcc/dwarf2out.c

[wide-int 4/8] Tweak uses of new API

2014-04-22 Thread Richard Sandiford
This is an assorted bunch of API tweaks: - use neg_p instead of lts_p (..., 0) - use STATIC_ASSERT for things that are known at compile time - avoid unnecessary wide(st)_int temporaries and arithmetic - remove an unnecessary template parameter - use to_short_addr for an offset_int-HOST_WIDE_INT

[wide-int 5/8] Use LOG2_BITS_PER_UNIT

2014-04-22 Thread Richard Sandiford
Looks like a few uses of the old idiom: BITS_PER_UNIT == 8 ? 3 : exact_log2 (BITS_PER_UNIT) have crept in. This patch replaces them with LOG2_BITS_PER_UNIT. Tested on x86_64-linux-gnu. OK to install? Thanks, Richard Index: gcc/expr.c

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