On Fri, Jun 20, 2014 at 10:42 PM, Marc Glisse marc.gli...@inria.fr wrote:
as reported in PR 61503, there seems to be a typo in the shrd pattern. I
think it is quite unlikely to cause any problem, because the pattern is 1
instruction too long for combine to recognize it (by the way, if someone
On Sat, Jun 21, 2014 at 6:32 PM, Marc Glisse marc.gli...@inria.fr wrote:
Er, I am sorry, I don't know what happened, but when testing the backport to
4.9 I got an obvious failure in the testsuite, which I am sure should also
happen on trunk, but somehow I didn't see it (I am almost sure I
On Sat, Jun 21, 2014 at 8:07 PM, Jakub Jelinek ja...@redhat.com wrote:
--- gcc/config/i386/driver-i386.c.jj2014-05-14 14:45:54.0 +0200
+++ gcc/config/i386/driver-i386.c 2014-06-20 18:59:57.805006358 +0200
@@ -745,6 +745,11 @@ const char *host_detect_local_cpu (int a
On Mon, Jun 23, 2014 at 6:29 PM, H.J. Lu hjl.to...@gmail.com wrote:
--- gcc/config/i386/driver-i386.c.jj2014-05-14 14:45:54.0
+0200
+++ gcc/config/i386/driver-i386.c 2014-06-20 18:59:57.805006358
+0200
@@ -745,6 +745,11 @@ const char *host_detect_local_cpu (int a
Hello!
Attached patch handles (barrier) RTXes that can be reached when
__builtin_trap builtin is used.
2014-06-26 Uros Bizjak ubiz...@gmail.com
PR target/61586
* config/alpha/alpha.c (alpha_handle_trap_shadows): Handle BARRIER RTX.
testsuite/ChangeLog:
2014-06-26 Uros Bizjak ubiz
))) NOTE_INSN_CALL_ARG_LOCATION)
(note 216 203 117 0 NOTE_INSN_EH_REGION_END)
(barrier 117 216 202)
...
Previously, both the barrier and the EH_REGION_END note were emitted
above CALL_ARG_LOCATION note.
2014-06-26 Uros Bizjak ubiz...@gmail.com
* except.c (emit_note_eh_region_end): New helper function
and write around. These blockages thus ensure
atomicity of the sequence.
2014-06-27 Uros Bizjak ubiz...@gmail.com
* config/alpha/alpha.md (unspec): Add UNSPEC_MEMORY_BLOCKAGE.
(*memory_blockage): New.
(aligned_store): Wrap the expanded sequence with memory blockages
(unaligned_storemode
On Fri, Jun 27, 2014 at 10:04 PM, Richard Henderson r...@redhat.com wrote:
On 06/27/2014 10:04 AM, Uros Bizjak wrote:
This happened due to the way stores to QImode and HImode locations are
implemented on non-BWX targets. The sequence reads full word, does its
magic to the part and stores
On Fri, Jun 27, 2014 at 9:11 PM, Richard Henderson r...@redhat.com wrote:
On 06/26/2014 02:15 PM, Uros Bizjak wrote:
* except.c (emit_note_eh_region_end): New helper function.
(convert_to_eh_region_ranges): Use emit_note_eh_region_end to
emit EH_REGION_END note.
This bit looks
are not split
away from their call insn anymore.
2014-06-30 Uros Bizjak ubiz...@gmail.com
PR target/56858
* config/alpha/alpha.c: Include tree-pass.h, context.h
and pass_manager.h.
(pass_data_handle_trap_shadows): New pass.
(pass_handle_trap_shadows::gate): New pass gate function
On Mon, Jun 30, 2014 at 5:54 PM, Richard Henderson r...@redhat.com wrote:
On 06/29/2014 11:14 AM, Uros Bizjak wrote:
if (MEM_READONLY_P (x))
+if (GET_CODE (mem_addr) == AND)
+ return 1;
return 0;
Certainly missing braces here. But with that fixed the patch looks plausible
Hello!
Attached patch fixes some fallout from IEEE support and enables -mieee
for alpha. Also, the patch removes -O0 from dg-additiona-options in
IEEE testsuite, as this always override default optimization flag.
libgfortran/ChangeLog:
2014-07-02 Uros Bizjak ubiz...@gmail.com
On Wed, Jul 2, 2014 at 11:16 AM, FX fxcoud...@gmail.com wrote:
Thanks very much for the patch. I have a few questions:
the patch removes -O0 from dg-additiona-options in IEEE testsuite, as this
always override default optimization flag.
That was my purpose: this test can fail with
Hello!
Silvermont processors have penalty for instructions having 4+ bytes of
prefixes (including escape
bytes in opcode). This situation happens when REX prefix is used in SSE4
instructions. This
patch tries to avoid such situation by preferring xmm0-xmm7 usage over
xmm8-xmm15 in
On Thu, Jul 3, 2014 at 11:06 AM, FX fxcoud...@gmail.com wrote:
Hi all,
The attached patch provides support for underflow control in the
IEEE_ARITHMETIC module, for x86/x86_64 targets (our main user base).
Bootstrapped and regtested on x86_64-apple-darwin13. Comes with a testcase.
+int
On Thu, Jul 3, 2014 at 11:25 AM, Uros Bizjak ubiz...@gmail.com wrote:
The attached patch provides support for underflow control in the
IEEE_ARITHMETIC module, for x86/x86_64 targets (our main user base).
Bootstrapped and regtested on x86_64-apple-darwin13. Comes with a testcase.
Index: gcc
On Thu, Jul 3, 2014 at 11:42 AM, FX fxcoud...@gmail.com wrote:
(I don't think -O0 is needed, but have to check with a testsuite run.)
On x86_64-apple-darwin, -O0 or -O1 are needed: at -O2 my “use_real” call is
optimized out anyway, and the division simplified at compile time.
You can mark
On Thu, Jul 3, 2014 at 12:26 PM, FX fxcoud...@gmail.com wrote:
I'd suggest to name this fie ieee_underflow_1.f90 for consistency.
In fact, since the directory is called ieee/, I think I’ll rename the others
so they don’t all start with ieee_
BTW: underflow control also works on alpha,
On Thu, Jul 3, 2014 at 12:45 PM, Ilya Enkovich enkovich@gmail.com wrote:
Silvermont processors have penalty for instructions having 4+ bytes of
prefixes (including escape
bytes in opcode). This situation happens when REX prefix is used in SSE4
instructions. This
patch tries to avoid
Hello!
There is already a higher priority for registers not requiring REX.
My patch affects cases when compiler has to use xmm8-15 and it just
tries to say LRA to assign them for non SSE4 instructions. I doubt it
would have some use for other targets than Silvermont.
When it is just a
On Thu, Jul 3, 2014 at 1:50 PM, Ilya Enkovich enkovich@gmail.com wrote:
I didn't find a nice way to fix peephole2 patterns to take register
constraints into account. Is there any way to do it?
Use REX_SSE_REGNO_P (REGNO (operands[...])) in the insn C constraint.
Also fully restrict
On Thu, Jul 3, 2014 at 2:43 PM, FX fxcoud...@gmail.com wrote:
Here’s an updated patch, providing support for underflow control in the
IEEE_ARITHMETIC module, for x86/x86_64 targets and alpha-glibc.
Bootstrapped and regtested on x86_64-apple-darwin13, tested by Uros on alpha.
The testcase
On Thu, Jul 3, 2014 at 3:02 PM, Uros Bizjak ubiz...@gmail.com wrote:
On Thu, Jul 3, 2014 at 2:43 PM, FX fxcoud...@gmail.com wrote:
Here’s an updated patch, providing support for underflow control in the
IEEE_ARITHMETIC module, for x86/x86_64 targets and alpha-glibc.
Bootstrapped
On Thu, Jul 3, 2014 at 10:57 AM, Evgeny Stupachenko evstu...@gmail.com wrote:
The following patch should fix 61618
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61618
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 8046c67..2cffcef 100644
--- a/gcc/config/i386/i386.c
+++
On Thu, Jul 3, 2014 at 11:53 AM, Evgeny Stupachenko evstu...@gmail.com wrote:
The expand_vec_perm_palignr is similar for SSSE3 and AVX2 cases,
but AVX2 requires more instructions to complete the scheme.
The patch below adds AVX2 support for six instructions, leaving SSSE3 for two.
Is it ok?
On Fri, Jul 4, 2014 at 2:49 PM, Evgeny Stupachenko evstu...@gmail.com wrote:
2014-07-04 Evgeny Stupachenko evstu...@gmail.com
* config/i386/i386.c (expand_vec_perm_pblendv): Disable for AVX.
Please mention PR target/61618 above.
The following patch should fix 61618
Ping.
The patch is at [1].
[1] https://gcc.gnu.org/ml/gcc-patches/2014-06/msg02430.html
Thanks,
Uros.
On Mon, Jun 30, 2014 at 9:59 PM, Uros Bizjak ubiz...@gmail.com wrote:
Hello!
After fixing _.barriers and _.eh_range passes w.r.t. CALL_ARG_LOCATION
notes, we can finaly move handling
On Mon, Jul 7, 2014 at 5:01 PM, Richard Henderson r...@redhat.com wrote:
Early alpha can't store sub-4-byte quantities. Altivec can't store anything
but 16 byte quantities. In order to perform smaller stores, we have to do a
read-modify-write sequence on a larger aligned chunk of memory.
Hello!
The only thing I can see is that libgfortran/config/fpu-sysv.h assumes that
FP_RM and others are macros, checking them with #ifdef FP_RM”. Is that the
reason?
It is.
If so, we might just want to use them unconditionally… unless it creates a
mess on some other SysV target!
FWIW,
Hello!
Ping?
While I added the new define_insn_and_split for vec_merge, a bug is
exposed: in config/i386/sse.md, [ define_expand xop_vmfrczmode2 ]
only takes one input, but the corresponding builtin functions have two
inputs, which are shown in i386.c:
{ OPTION_MASK_ISA_XOP,
On Mon, Jun 30, 2014 at 9:59 PM, Uros Bizjak ubiz...@gmail.com wrote:
After fixing _.barriers and _.eh_range passes w.r.t. CALL_ARG_LOCATION
notes, we can finaly move handling of trap shadows (PR 56858) and insn
alignments into their own passes.
Additionally, the patch skips handling
in time (~30 seconds per invocation).
2014-07-11 Uros Bizjak ubiz...@gmail.com
* config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): New.
(TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
testsuite/ChangeLog:
2014-07-11 Uros Bizjak ubiz...@gmail.com
* lib/target-supports.exp
Hello!
2014-06-10 Kugan Vivekanandarajah kug...@linaro.org
* config/arm/arm.c (arm_atomic_assign_expand_fenv): call
default_atomic_assign_expand_fenv for TARGET_THUMB1.
(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
__builtins_arm_get_fpscr only when
Hello!
Attached patch optimizes ix86_atomic_assign_expand_fenv by using
register form of fnstsw %ax instead of fnstsw mem. This way a
memory RW cycle is removed for a temporary.
2014-07-12 Uros Bizjak ubiz...@gmail.com
* config/i386/i386-builtin-types.def: Add USHORT_FTYPE_VOID
On Mon, Jul 14, 2014 at 10:05 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Attached patch optimizes ix86_atomic_assign_expand_fenv by using
register form of fnstsw %ax instead of fnstsw mem. This way a
memory RW cycle is removed for a temporary.
The patch you attached seems to be the
On Thu, Jul 3, 2014 at 3:38 PM, Ilya Enkovich enkovich@gmail.com wrote:
2014-07-03 16:07 GMT+04:00 Uros Bizjak ubiz...@gmail.com:
On Thu, Jul 3, 2014 at 1:50 PM, Ilya Enkovich enkovich@gmail.com wrote:
I didn't find a nice way to fix peephole2 patterns to take register
constraints
On Tue, Jul 15, 2014 at 10:25 AM, Ilya Enkovich enkovich@gmail.com wrote:
Also fully restrict xmm8-15 does not seem right. It is just costly
but not fully disallowed.
As said earlier, you can try Ya*x as a constraint.
I tried it. It does not seem to affect allocation much. I do not see
On Tue, Jul 15, 2014 at 12:28 PM, Petr Murzin petrmurz...@gmail.com wrote:
Hi,
I've fixed the uninitialized variable problem. Please have a look. Is
it ok for trunk?
2014-07-15 Petr Murzin petr.mur...@intel.com
* gcc.target/i386/avx512f-vbroadcastf64x4-2.c: Fix the uninitialized
variable
On Tue, Jul 15, 2014 at 1:01 PM, Ilya Enkovich enkovich@gmail.com wrote:
On 15 Jul 10:42, Uros Bizjak wrote:
On Tue, Jul 15, 2014 at 10:25 AM, Ilya Enkovich enkovich@gmail.com
wrote:
Also fully restrict xmm8-15 does not seem right. It is just costly
but not fully disallowed
On Sat, Jul 12, 2014 at 12:19 AM, Uros Bizjak ubiz...@gmail.com wrote:
Attached patch implements TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook for
alpha. The implementation is mostly copied from arm/arm.c, where calls
to target builtins are replaced with calls to
__ieee_{get,set}_fp_control function
Hello!
Attached trivial patch renames a couple of files to more consistent
names (as suggested by FX).
The patch also adds -mieee-with-inexact for alpha where needed.
2014-07-15 Uros Bizjak ubiz...@gmail.com
* gfortran.dg/ieee/rounding_1.f90: Rename from ieee_rounding_1.f90
Hello!
The detailed description and examples can be found in pr61662, but in short:
using #ifdef
__x86_64__ to determine the size of a 'long' does not reliably yield the
correct result. This
causes _lrotl and _lrotr to return incorrect results on LLP64 systems (like
Windows).
On Tue, Jul 15, 2014 at 6:15 PM, Uros Bizjak ubiz...@gmail.com wrote:
Attached trivial patch renames a couple of files to more consistent
names (as suggested by FX).
The patch also adds -mieee-with-inexact for alpha where needed.
2014-07-15 Uros Bizjak ubiz...@gmail.com
On Fri, Jun 6, 2014 at 4:31 PM, Jonathan Wakely jwak...@redhat.com wrote:
On 06/06/14 12:40 +0200, Uros Bizjak wrote:
On Fri, Jun 6, 2014 at 11:19 AM, Jonathan Wakely jwak...@redhat.com
wrote:
On 06/06/14 10:27 +0200, Uros Bizjak wrote:
These two tests timeout on alpha-linux-gnu:
FAIL
Hello!
-mfp-trap-mode=sui is needed in addition to -mieee to compile fenv.c
for older alphas to generate inexact exceptions.
2013-07-18 Uros Bizjak ubiz...@gmail.com
* configure.tgt (alpha*): Add -mfp-trap-mode=sui to XCFLAGS.
Tested on alpha-linux-gnu, committed to mainline SVN.
Uros
On Fri, Jul 18, 2014 at 4:05 PM, Petr Murzin petrmurz...@gmail.com wrote:
I've fixed AVX512F tests. These tests failed on Android because they
were using values.h, which seem to be obsolete and is not present in
Android sysroot.
Here is the quote from values.h
/* This interface is obsolete.
Hello!
2014-07-18 Uros Bizjak ubiz...@gmail.com
PR target/61794
* config/i386/sse.md (avx512f_vextractshuffletype32x4_1_maskm):
Fix instruction constraint.
(mask_codeforavx512f_vextractshuffletype32x4_1mask_name): Ditto.
testsuite/ChangeLog:
2014-07-18 Uros Bizjak ubiz
On Sun, Jul 20, 2014 at 12:25 PM, Tom de Vries tom_devr...@mentor.com wrote:
this patch fixes the problems in test-case
gcc.target/i386/fuse-caller-save-xmm.c reported in PR 61827. I've removed
the checks for cfi_def_cfa_offset, which were not robust enough for the
different configurations.
Hello!
2014-07-21 Uros Bizjak ubiz...@gmail.com
PR target/61855
* config/i386/avx512fintrin.h: Move constants for mantissa extraction
out of #ifdef __OPTIMIZE__.
testsuite/ChangeLog:
2014-07-21 Uros Bizjak ubiz...@gmail.com
PR target/61855
* gcc.target/i386/pr61855.c
On Mon, Jul 21, 2014 at 12:34 PM, Tom de Vries tom_devr...@mentor.com wrote:
Dominique noticed that the .LC0 check failed on darwin, since the label LC0
is used. This follow-up patch fixes that (and I see now you already Ok-ed
this change).
Furthermore, I've realized from the comments in the
the default: case, but ffi_closure_osf_inner
aborts with this type of argument.
The patch changes the default case in ffi_closure_osf_inner from abort
to FFI_ASSERT, an this way synchronizes argument handling in both
cases.
2014-07-21 Uros Bizjak ubiz...@gmail.com
* src/alpha/ffi.c: Do not include
Hello!
- Thunk name encodes offset into the structure, which is different
between 32/64bit targete when pointers are involved.
- CCP runs with -O1 only
- Missing dump cleanup
2014-07-22 Uros Bizjak ubiz...@gmail.com
* g++.dg/ipa/imm-devirt-2.C (dg-final): Improve einline dump string
-g
where missing FDE in libc's _wordcopy_fwd_aligned at wordcopy.c broke
unwinding.
2014-07-24 Uros Bizjak ubiz...@gmail.com
* config/alpha/elf.h: Define TARGET_UNWIND_TABLES_DEFAULT.
Patch was bootstrapped and regression tested on alphaev68-pc-linux-gnu.
Patch was committed to mainline
Hello!
Well, I was lucky enough to gain access to an alpha pca56 for a day (I say
lucky, this may not be repeatable!). However I was not able to build the Ada
frontend, due (AFAICT) to the image being too big for relocations. (Moreover,
my understanding is that the default memory model for
Hello!
2014-07-24 Uros Bizjak ubiz...@gmail.com
* go/go-gcc.cc (Gcc_backend::global_variable_set_init): Rename
symtab_get_node to symtab_node::get.
Tested on x86_64-linux-gnu and committed to mainline SVN.
Uros.
Index: go-gcc.cc
Hello!
Attached patch avoids a bunch of:
gcc/fortran/intrinsic.texi:1665: warning: node next `ATOMIC_CAS' in
menu `ATOMIC_FETCH_ADD' and in sectioning `ATOMIC_DEFINE' differ
warnings.
2014-07-24 Uros Bizjak ubiz...@gmail.com
* intrinsic.texi (Intrinsic Procedures) ATOMIC_DEFINE: Move
Hello!
2014-07-25 Uros Bizjak ubiz...@gmail.com
* config/abi/post/alpha-linux-gnu/baseline_symbols.txt: Update.
Tested on alphaev68-linux-gnu and committed to mainline SVN.
Uros.
Index: config/abi/post/alpha-linux-gnu/baseline_symbols.txt
On Mon, Jul 21, 2014 at 8:21 PM, Uros Bizjak ubiz...@gmail.com wrote:
Attached patch fixes libgo reflect test failure with libffi closures.
The gccgo compiler started to use FFI closures recently; the compiler
passes ffi_type_void for structures with zero members.
ffi_call form src/alpha
On Fri, Jul 25, 2014 at 11:01 PM, Paolo Bonzini bonz...@gnu.org wrote:
Well, I was lucky enough to gain access to an alpha pca56 for a day (I say
lucky, this may not be repeatable!). However I was not able to build the Ada
frontend, due (AFAICT) to the image being too big for relocations.
On Mon, May 2, 2011 at 9:21 AM, Uros Bizjak ubiz...@gmail.com wrote:
It looks that GP relative relocations do not fit anymore into GPREL16
reloc, so bootstrap on alpha hosts fail in stage2 with relocation
truncated to fit: GPREL16 against I found no other solution but
to pass --no-relax
On Mon, Jul 28, 2014 at 7:02 PM, Richard Henderson r...@redhat.com wrote:
On 07/26/2014 05:35 AM, Uros Bizjak wrote:
On Mon, May 2, 2011 at 9:21 AM, Uros Bizjak ubiz...@gmail.com wrote:
It looks that GP relative relocations do not fit anymore into GPREL16
reloc, so bootstrap on alpha hosts
On Tue, Jul 29, 2014 at 6:39 PM, Richard Henderson r...@redhat.com wrote:
On 07/29/2014 06:11 AM, Uros Bizjak wrote:
Perhaps even better solution for mainline would be to detect a recent
enough linker and skip the workaround in that case? I guess that 2.25
will have this issue fixed
On Sun, Jul 27, 2014 at 2:50 PM, Kirill Yukhin kirill.yuk...@gmail.com wrote:
With this patch we'd like to start merge process of avx-512vlbwdq
branch into main trunk.
This patch introduces new switch `-mavx512dq'
Bootstrapped.
Is it ok for trunk?
*
On Mon, Nov 10, 2014 at 10:13 PM, Richard Biener
richard.guent...@gmail.com wrote:
On November 10, 2014 9:13:29 PM CET, Uros Bizjak ubiz...@gmail.com wrote:
Hello!
std::swap was recently mentioned in gcc-patches@ mailing list, so I
gave it a try. As can be seen below, a lot of code in config
Hello!
Now that Vlad fixed the real problem of PR 63620 [1], we can remove
the temporary workaround. The patch also adds the testcase from PR.
2014-11-11 Uros Bizjak ubiz...@gmail.com
Revert:
2014-10-31 Uros Bizjak ubiz...@gmail.com
PR target/63620
* config/i386/i386
Hello!
do $subject, and cleanup for always 64 bit hwi.
bootstrapped + regtested x86_64-unknown-linux-gnu, ok?
Ok. Can you please replace remaining HOST_WIDE_INT
vestiges in there with [u]int64_t please?
This patch breaks the build on debian 6.0:
../../gcc/sreal.c: In member function
On Mon, Nov 10, 2014 at 10:51 PM, Marc Glisse marc.gli...@inria.fr wrote:
On Mon, 10 Nov 2014, Richard Biener wrote:
No extra includes required?
utility is already included in wide-int.h and rtl.h, should probably move
those.
Bah, we hit a problem. std::swap has been moved from algorithm
On Tue, Nov 11, 2014 at 9:11 AM, Jakub Jelinek ja...@redhat.com wrote:
do $subject, and cleanup for always 64 bit hwi.
bootstrapped + regtested x86_64-unknown-linux-gnu, ok?
Ok. Can you please replace remaining HOST_WIDE_INT
vestiges in there with [u]int64_t please?
This
On Tue, Nov 11, 2014 at 9:09 AM, Uros Bizjak ubiz...@gmail.com wrote:
On Mon, Nov 10, 2014 at 10:51 PM, Marc Glisse marc.gli...@inria.fr wrote:
On Mon, 10 Nov 2014, Richard Biener wrote:
No extra includes required?
utility is already included in wide-int.h and rtl.h, should probably move
On Tue, Nov 11, 2014 at 12:35 PM, Marc Glisse marc.gli...@inria.fr wrote:
last patch, extending == and to size 256. Regtested as usual.
Is the branch ready to be merged into trunk?
2014-11-10 Marc Glisse marc.gli...@inria.fr
* config/i386/emmintrin.h (_mm_cmpeq_epi8,
Hello!
This patch implements what I understood from Joseph's
https://gcc.gnu.org/ml/gcc/2013-10/msg00280.html
and also adds clang compatible builtins (which implement
small subset of the typegeneric ones).
Besides the clang compatibility builtins, there are 3 new
type-generic builtins,
Hello!
2014-11-11 Uros Bizjak ubiz...@gmail.com
* config/alpha/alpha.c (alpha_emit_conditional_branch): Replace
open-coded swap with std::swap to swap values.
(alpha_emit_setcc): Ditto.
(alpha_emit_conditional_move): Ditto.
(alpha_split_tmode_pair): Ditto.
Bootstrapped
On Tue, Nov 11, 2014 at 4:09 PM, Marc Glisse marc.gli...@inria.fr wrote:
Hello,
here is the combined patch+ChangeLog. I'll run a last regtest just before
committing. Ok for trunk?
2014-11-12 Marc Glisse marc.gli...@inria.fr
gcc/
* config/i386/xmmintrin.h (_mm_add_ps, _mm_sub_ps,
On Wed, Nov 12, 2014 at 2:15 PM, Evgeny Stupachenko evstu...@gmail.com wrote:
To avoid misunderstanding.
I haven't yet committed this obvious fix.
Is it ok?
If it is obvious, then it doesn't need an approval.
So, OK.
Thanks,
Uros.
Hello!
2014-11-12 Uros Bizjak ubiz...@gmail.com
* gcc.target/i386/pr45852.c: Simplify target selector.
* gcc.target/i386/pr63495.c: Ditto.
* gcc.target/i386/pr39496.c: Ditto.
* gcc.target/i386/pr36613.c: Ditto.
Tested on x86_64-linux-gnu {,-m32} and committed.
Uros.
Index
Hello!
It's kind of obvious which targets are processed in gcc.target/i386
directory, so:
-/* { dg-skip-if { i?86-*-* x86_64-*-* } { -march=* } { -march=k8 } } */
+/* { dg-skip-if { *-*-* } { -march=* } { -march=k8 } } */
2014-11-12 Uros Bizjak ubiz...@gmail.com
* gcc.target/i386/387-1
On Wed, Nov 12, 2014 at 9:43 PM, H.J. Lu hongjiu...@intel.com wrote:
Hi,
r216154 exposed an x86 backend bug. For large PIC mode thunk, there
are
if (ix86_cmodel == CM_LARGE_PIC SYMBOLIC_CONST (fnaddr))
fnaddr = legitimize_pic_address (fnaddr,
On Wed, Nov 12, 2014 at 11:00 PM, Jakub Jelinek ja...@redhat.com wrote:
On Wed, Nov 12, 2014 at 01:51:01PM -0800, H.J. Lu wrote:
So, all in all, SET_REGNO sounds inappropriate to me, everywhere else
gen_raw_REG or gen_rtx_REG is used instead, so IMNSHO you should do the
same.
Hello!
Here is one more merge of libsanitizer (last one was in Sept).
Tested on x86_64 Ubuntu 14.04 like this:
rm -rf */{*/,}libsanitizer make -j 50
make -j 40 -C gcc check-g{cc,++}
RUNTESTFLAGS='--target_board=unix\{-m32,-m64\} asan.exp' \
make -j 40 -C gcc check-g{cc,++}
On Fri, Nov 14, 2014 at 12:31 PM, Uros Bizjak ubiz...@gmail.com wrote:
Here is one more merge of libsanitizer (last one was in Sept).
Tested on x86_64 Ubuntu 14.04 like this:
rm -rf */{*/,}libsanitizer make -j 50
make -j 40 -C gcc check-g{cc,++}
RUNTESTFLAGS='--target_board=unix\{-m32,-m64
On Fri, Nov 14, 2014 at 3:38 PM, H.J. Lu hongjiu...@intel.com wrote:
On Thu, Nov 13, 2014 at 09:32:07PM -0800, H.J. Lu wrote:
For i[34567]86-*-linux* and x86_64-*-linux* targets, config.gcc assumes
modern glibc and set default_gnu_indirect_function to yes. That is wrong
for
On Fri, Nov 14, 2014 at 8:51 PM, Konstantin Serebryany
konstantin.s.serebry...@gmail.com wrote:
It is true that we typically don't care about old kernels.
Please note that 2.6.32 is still supported longterm release, not to
mention that CentOS 5.x will be still supported for the next three
Hello!
2014-11-16 Uros Bizjak ubiz...@gmail.com
* config/sh/sh.c: Do not include algorithm.
(sh_emit_scc_to_t): Replace open-coded swap with std::swap
to swap values.
(sh_emit_compare_and_branch): Ditto.
(sh_emit_compare_and_set): Ditto.
* config/sh/sh.md (replacement
Hello!
2014-11-19 Uros Bizjak ubiz...@gmail.com
* testsuite/libgomp.c/examples-4/e.53.5.c: Require
vect_simd_clones effective target.
* testsuite/libgomp.fortran/examples-4/e.53.5.f90: Ditto.
Tested on x86_64-linux-gnu {,-m32} CentOS 5.11.
OK for mainline?
Uros.
Index: testsuite
Hello!
Carry flag checks from overflow tests can propagate into FP cmove
instructions. However, while c and nc suffixes are allowed as
suffixes in integer cmove insns, they are not allowed in FP cmove
insns. Patch generates equivalent b and nb suffixes for FP mode.
2014-11-19 Uros Bizjak ubiz
5.0.
2014-11-19 Uros Bizjak ubiz...@gmail.com
PR target/63966
* lex.c [__i386__ || __x86_64__]: Include system cpuid.h for
GCC_VERSION 5000.
Patch was bootstrapped on x86_64-linux-gnu, Fedora 20. Patch will be
committed to mainline in a day or two, preferably after someone tests
On Wed, Nov 19, 2014 at 6:32 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
Hi,
New revision of Intel ISA reference [1] has new instructions:
Clwb, pcommit and new flavors of AVX512. Patch bellow adds them.
I understand that stage 1 is closed, however those changes shouldn't
affect anything
On Wed, Nov 19, 2014 at 9:59 PM, Uros Bizjak ubiz...@gmail.com wrote:
Hello!
libcpp/lex.c includes ../gcc/config/i386/cpuid.h, and is picked up
by the system compiler during stage1. Recently, cpuid.h was changed to
account for %ebx changes and now uses b asm constraint for i686 even
On Thu, Nov 20, 2014 at 12:36 PM, Evgeny Stupachenko evstu...@gmail.com wrote:
Hi,
The patch expand even/odd permutation using:
and, and, pack in odd case
shift, shift, pack in even case
instead of current pshufb, pshufb, or or big set of unpack insns.
AVX2/CORE bootstrap and make check
On Thu, Nov 20, 2014 at 5:25 PM, Evgeny Stupachenko evstu...@gmail.com wrote:
Bootstrap / make check passed with updated patch.
Is it still ok?
It looks like we don't need expand_vec_perm_vpshufb2_vpermq_even_odd
any more with the patch.
However the clean up will be in the separate patch
On Fri, Nov 21, 2014 at 11:46 AM, Evgeny Stupachenko evstu...@gmail.com wrote:
PING.
200 currently looks optimal for x86.
Let's commit the following:
2014-11-21 Evgeny Stupachenko evstu...@gmail.com
* config/i386/i386.c (ix86_option_override_internal): Increase
On Fri, Nov 21, 2014 at 12:45 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
On 20 Nov 09:43, Uros Bizjak wrote:
On Wed, Nov 19, 2014 at 6:32 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
Hi,
New revision of Intel ISA reference [1] has new instructions:
Clwb, pcommit and new flavors
On Fri, Nov 21, 2014 at 12:50 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
On 20 Nov 09:43, Uros Bizjak wrote:
On Wed, Nov 19, 2014 at 6:32 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
Hi,
New revision of Intel ISA reference [1] has new instructions:
Clwb, pcommit and new flavors
On Fri, Nov 21, 2014 at 12:38 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
On 20 Nov 09:43, Uros Bizjak wrote:
On Wed, Nov 19, 2014 at 6:32 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
Hi,
New revision of Intel ISA reference [1] has new instructions:
Clwb, pcommit and new flavors
On Fri, Nov 21, 2014 at 12:21 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
On 20 Nov 09:43, Uros Bizjak wrote:
On Wed, Nov 19, 2014 at 6:32 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
Hi,
New revision of Intel ISA reference [1] has new instructions:
Clwb, pcommit and new flavors
Hello!
2014-11-22 Uros Bizjak ubiz...@gmail.com
* gcc.target/i386/avx512vl-vpermb-2.c: Require avx512vbmi.
* gcc.target/i386/avx512vl-vpermi2b-2.c: Ditto.
* gcc.target/i386/avx512vl-vpermt2b-2.c: Ditto.
* gcc.target/i386/avx512vl-vpmaddhuq-2.c: Require avx512ifma
On Sat, Nov 22, 2014 at 10:49 AM, Eric Botcazou ebotca...@adacore.com wrote:
OK. Looks like a good performance vs. codesize tradeoff.
Yes, but IMO this should be done in the generic code, unrolling small loops is
profitable on most architectures.
Yeah, but after a couple of pings for a
Hello!
These two tests fix PR target/63847 [1], where x87 excess precision
causes testcase to fail. The problem was triggered by -fpic, please
see the PR for analysis.
The patch adds -ffloat-store for 32bit x86 target, a standard and well
tested solution for this problem.
2014-11-22 Uros
patch:
2014-11-22 Uros Bizjak ubiz...@gmail.com
* params.def (PARAM_MAX_COMPLETELY_PEELED_INSNS): Increase to 200.
* config/i386/i386.c (ix86_option_override_internal): Do not increase
PARAM_MAX_COMPLETELY_PEELED_INSNS.
Bootstrapped on x86_64-linux-gnu.
Uros.
Index: params.def
On Tue, Nov 25, 2014 at 12:25 AM, Jakub Jelinek ja...@redhat.com wrote:
The fallback delegitimization I've added as last option mainly for
debug info purposes, when we don't know if the base is a PIC register
or say a PIC register plus some addend, unfortunately in some tests
broke
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