Re: [arm-embedded] [PATCH, ARM 7/7] Enable ARMv8-M atomic and synchronization support for ARMv8-M Baseline
On 22/09/16 17:43, Thomas Preudhomme wrote: Hi, We've decided to apply the following patch to ARM/embedded-6-branch. Sorry I meant ARM/embedded-5-branch. This has just been applied on ARM/embedded-6-branch as well today. Best regards, Thomas
[arm-embedded] [PATCH, ARM 7/7] Enable ARMv8-M atomic and synchronization support for ARMv8-M Baseline
Hi, We've decided to apply the following patch to ARM/embedded-6-branch. Best regards, Thomas --- Begin Message --- Hi, This patch is part of a patch series to add support for atomic operations on ARMv8-M Baseline targets in GCC. This specific patch enables atomic and synchronization support added in previous patches of the series and adds tests. Enabling is done at the end of the patch series to ensure that no ICE is seen when in the middle of the patch series (eg. while doing a bisect). Enabling is done by enabling the exclusive and atomic loads and stores needed to implement all synchronization and atomic operations. ChangeLog entries are as follow: *** gcc/ChangeLog *** 2016-07-05 Thomas Preud'homme * config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline. (TARGET_HAVE_LDREXBH): Likewise. (TARGET_HAVE_LDACQ): Likewise. *** gcc/testsuite/ChangeLog *** 2016-07-05 Thomas Preud'homme * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test. * gcc.target/arm/atomic-op-acq_rel-3.c: Likewise. * gcc.target/arm/atomic-op-acquire-3.c: Likewise. * gcc.target/arm/atomic-op-char-3.c: Likewise. * gcc.target/arm/atomic-op-consume-3.c: Likewise. * gcc.target/arm/atomic-op-int-3.c: Likewise. * gcc.target/arm/atomic-op-relaxed-3.c: Likewise. * gcc.target/arm/atomic-op-release-3.c: Likewise. * gcc.target/arm/atomic-op-seq_cst-3.c: Likewise. * gcc.target/arm/atomic-op-short-3.c: Likewise. Testing: No code generation difference for ARMv7-A, ARMv7VE and ARMv8-A on all atomic and synchronization testcases in the testsuite [2]. Patchset was also bootstrapped with --enable-itm --enable-gomp on ARMv8-A in ARM and Thumb mode at optimization level -O1 and above [1] without any regression in the testsuite and no code generation difference in libitm and libgomp. Code generation for ARMv8-M Baseline has been manually examined and compared against ARMv8-A Thumb-2 for the following configuration without finding any issue: gcc.dg/atomic-op-2.c at -Os gcc.dg/atomic-compare-exchange-2.c at -Os gcc.dg/atomic-compare-exchange-3.c at -O3 Is this ok for trunk? Best regards, Thomas [1] CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET were set to "-O1 -g", "-O3 -g" and undefined ("-O2 -g") [2] The exact list is: gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c gcc/testsuite/gcc.dg/atomic-exchange-1.c gcc/testsuite/gcc.dg/atomic-exchange-2.c gcc/testsuite/gcc.dg/atomic-exchange-3.c gcc/testsuite/gcc.dg/atomic-fence.c gcc/testsuite/gcc.dg/atomic-flag.c gcc/testsuite/gcc.dg/atomic-generic.c gcc/testsuite/gcc.dg/atomic-generic-aux.c gcc/testsuite/gcc.dg/atomic-invalid-2.c gcc/testsuite/gcc.dg/atomic-load-1.c gcc/testsuite/gcc.dg/atomic-load-2.c gcc/testsuite/gcc.dg/atomic-load-3.c gcc/testsuite/gcc.dg/atomic-lockfree.c gcc/testsuite/gcc.dg/atomic-lockfree-aux.c gcc/testsuite/gcc.dg/atomic-noinline.c gcc/testsuite/gcc.dg/atomic-noinline-aux.c gcc/testsuite/gcc.dg/atomic-op-1.c gcc/testsuite/gcc.dg/atomic-op-2.c gcc/testsuite/gcc.dg/atomic-op-3.c gcc/testsuite/gcc.dg/atomic-op-6.c gcc/testsuite/gcc.dg/atomic-store-1.c gcc/testsuite/gcc.dg/atomic-store-2.c gcc/testsuite/gcc.dg/atomic-store-3.c gcc/testsuite/g++.dg/ext/atomic-1.C gcc/testsuite/g++.dg/ext/atomic-2.C gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c gcc/testsuite/gcc.target/arm/atomic-op-acquire.c gcc/testsuite/gcc.target/arm/atomic-op-char.c gcc/testsuite/gcc.target/arm/atomic-op-consume.c gcc/testsuite/gcc.target/arm/atomic-op-int.c gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c gcc/testsuite/gcc.target/arm/atomic-op-release.c gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c gcc/testsuite/gcc.target/arm/atomic-op-short.c gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c gcc/testsuite/gcc.target/arm/sync-1.c gcc/testsuite/gcc.target/arm/synchronize.c gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c libstdc++-v3/testsuite/29_atomics/atomic/60658.cc libstdc++-v3/testsuite/29_atomics/atomic/62259.cc libstdc++-v3/testsuite/29_atomics/atomic/64658.cc libstdc++-v3/testsuite/29_atomics/atomic/65147.cc libstdc++-v3/testsuite/29_atomics/atomic/65913.cc libstdc++-v3/testsuite/29_atomics/atomic/70766.cc libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc
[PATCH, ARM 7/7] Enable ARMv8-M atomic and synchronization support for ARMv8-M Baseline
Hi, This patch is part of a patch series to add support for atomic operations on ARMv8-M Baseline targets in GCC. This specific patch enables atomic and synchronization support added in previous patches of the series and adds tests. Enabling is done at the end of the patch series to ensure that no ICE is seen when in the middle of the patch series (eg. while doing a bisect). Enabling is done by enabling the exclusive and atomic loads and stores needed to implement all synchronization and atomic operations. ChangeLog entries are as follow: *** gcc/ChangeLog *** 2016-07-05 Thomas Preud'homme * config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline. (TARGET_HAVE_LDREXBH): Likewise. (TARGET_HAVE_LDACQ): Likewise. *** gcc/testsuite/ChangeLog *** 2016-07-05 Thomas Preud'homme * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test. * gcc.target/arm/atomic-op-acq_rel-3.c: Likewise. * gcc.target/arm/atomic-op-acquire-3.c: Likewise. * gcc.target/arm/atomic-op-char-3.c: Likewise. * gcc.target/arm/atomic-op-consume-3.c: Likewise. * gcc.target/arm/atomic-op-int-3.c: Likewise. * gcc.target/arm/atomic-op-relaxed-3.c: Likewise. * gcc.target/arm/atomic-op-release-3.c: Likewise. * gcc.target/arm/atomic-op-seq_cst-3.c: Likewise. * gcc.target/arm/atomic-op-short-3.c: Likewise. Testing: No code generation difference for ARMv7-A, ARMv7VE and ARMv8-A on all atomic and synchronization testcases in the testsuite [2]. Patchset was also bootstrapped with --enable-itm --enable-gomp on ARMv8-A in ARM and Thumb mode at optimization level -O1 and above [1] without any regression in the testsuite and no code generation difference in libitm and libgomp. Code generation for ARMv8-M Baseline has been manually examined and compared against ARMv8-A Thumb-2 for the following configuration without finding any issue: gcc.dg/atomic-op-2.c at -Os gcc.dg/atomic-compare-exchange-2.c at -Os gcc.dg/atomic-compare-exchange-3.c at -O3 Is this ok for trunk? Best regards, Thomas [1] CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET were set to "-O1 -g", "-O3 -g" and undefined ("-O2 -g") [2] The exact list is: gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c gcc/testsuite/gcc.dg/atomic-exchange-1.c gcc/testsuite/gcc.dg/atomic-exchange-2.c gcc/testsuite/gcc.dg/atomic-exchange-3.c gcc/testsuite/gcc.dg/atomic-fence.c gcc/testsuite/gcc.dg/atomic-flag.c gcc/testsuite/gcc.dg/atomic-generic.c gcc/testsuite/gcc.dg/atomic-generic-aux.c gcc/testsuite/gcc.dg/atomic-invalid-2.c gcc/testsuite/gcc.dg/atomic-load-1.c gcc/testsuite/gcc.dg/atomic-load-2.c gcc/testsuite/gcc.dg/atomic-load-3.c gcc/testsuite/gcc.dg/atomic-lockfree.c gcc/testsuite/gcc.dg/atomic-lockfree-aux.c gcc/testsuite/gcc.dg/atomic-noinline.c gcc/testsuite/gcc.dg/atomic-noinline-aux.c gcc/testsuite/gcc.dg/atomic-op-1.c gcc/testsuite/gcc.dg/atomic-op-2.c gcc/testsuite/gcc.dg/atomic-op-3.c gcc/testsuite/gcc.dg/atomic-op-6.c gcc/testsuite/gcc.dg/atomic-store-1.c gcc/testsuite/gcc.dg/atomic-store-2.c gcc/testsuite/gcc.dg/atomic-store-3.c gcc/testsuite/g++.dg/ext/atomic-1.C gcc/testsuite/g++.dg/ext/atomic-2.C gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c gcc/testsuite/gcc.target/arm/atomic-op-acquire.c gcc/testsuite/gcc.target/arm/atomic-op-char.c gcc/testsuite/gcc.target/arm/atomic-op-consume.c gcc/testsuite/gcc.target/arm/atomic-op-int.c gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c gcc/testsuite/gcc.target/arm/atomic-op-release.c gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c gcc/testsuite/gcc.target/arm/atomic-op-short.c gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c gcc/testsuite/gcc.target/arm/sync-1.c gcc/testsuite/gcc.target/arm/synchronize.c gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c libstdc++-v3/testsuite/29_atomics/atomic/60658.cc libstdc++-v3/testsuite/29_atomics/atomic/62259.cc libstdc++-v3/testsuite/29_atomics/atomic/64658.cc libstdc++-v3/testsuite/29_atomics/atomic/65147.cc libstdc++-v3/testsuite/29_atomics/atomic/65913.cc libstdc++-v3/testsuite/29_atomics/atomic/70766.cc libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc libstdc++-v3/testsuite/29_atomics/atomic/cons/constexpr.cc libstdc++-v3/testsuite/29_atomics/atomic/cons/copy_list.cc l