On Tue, May 29, 2012 at 12:01 PM, Igor Zamyatin izamya...@gmail.com wrote:
Hi, Uros!
Sorry, I didn't realize that patch was missed. I attached new version.
Changelog:
2012-05-29 Yuri Rumyantsev yuri.s.rumyant...@intel.com
* config/i386/i386.c (x86_sched_reorder): New function.
Sorry, I didn't realize that patch was missed. I attached new version.
Changelog:
2012-05-29 Yuri Rumyantsev yuri.s.rumyant...@intel.com
* config/i386/i386.c (x86_sched_reorder): New function.
Added new function x86_sched_reorder.
Reading it, you get the impression that
Hi, Uros!
Sorry, I didn't realize that patch was missed. I attached new version.
Changelog:
2012-05-29 Yuri Rumyantsev yuri.s.rumyant...@intel.com
* config/i386/i386.c (x86_sched_reorder): New function.
Added new function x86_sched_reorder.
As for multiply modes, currently we
Ping?
On Sun, May 6, 2012 at 11:27 AM, Igor Zamyatin izamya...@gmail.com wrote:
Ping. Could x86 maintainer(s) look at these changes?
Thanks,
Igor
On Fri, Apr 20, 2012 at 4:04 PM, Igor Zamyatin izamya...@gmail.com wrote:
On Tue, Apr 17, 2012 at 12:27 AM, Igor Zamyatin izamya...@gmail.com
Hello!
Ping?
Please at least add and URL to the patch, it took me some time to
found the latest version [1], I'm not even sure if it is the latest
version...
I assume that you cleared all issues with middle-end and scheduler
maintainers, it is not clear from the message.
+ (1) IMUL
Ping. Could x86 maintainer(s) look at these changes?
Thanks,
Igor
On Fri, Apr 20, 2012 at 4:04 PM, Igor Zamyatin izamya...@gmail.com wrote:
On Tue, Apr 17, 2012 at 12:27 AM, Igor Zamyatin izamya...@gmail.com wrote:
On Fri, Apr 13, 2012 at 4:20 PM, Andrey Belevantsev a...@ispras.ru wrote:
On
On Tue, Apr 17, 2012 at 12:27 AM, Igor Zamyatin izamya...@gmail.com wrote:
On Fri, Apr 13, 2012 at 4:20 PM, Andrey Belevantsev a...@ispras.ru wrote:
On 13.04.2012 14:18, Igor Zamyatin wrote:
On Thu, Apr 12, 2012 at 5:01 PM, Andrey Belevantseva...@ispras.ru
wrote:
On 12.04.2012 16:38,
On Fri, Apr 13, 2012 at 4:20 PM, Andrey Belevantsev a...@ispras.ru wrote:
On 13.04.2012 14:18, Igor Zamyatin wrote:
On Thu, Apr 12, 2012 at 5:01 PM, Andrey Belevantseva...@ispras.ru
wrote:
On 12.04.2012 16:38, Richard Guenther wrote:
On Thu, Apr 12, 2012 at 2:36 PM, Igor
On 12.04.2012 18:22, Richard Guenther wrote:
2012/4/12 Andrey Belevantseva...@ispras.ru:
On 12.04.2012 17:54, Richard Guenther wrote:
2012/4/12 Andrey Belevantseva...@ispras.ru:
On 12.04.2012 16:38, Richard Guenther wrote:
On Thu, Apr 12, 2012 at 2:36 PM, Igor Zamyatinizamya...@gmail.com
On Thu, Apr 12, 2012 at 5:01 PM, Andrey Belevantsev a...@ispras.ru wrote:
On 12.04.2012 16:38, Richard Guenther wrote:
On Thu, Apr 12, 2012 at 2:36 PM, Igor Zamyatinizamya...@gmail.com
wrote:
On Thu, Apr 12, 2012 at 4:24 PM, Richard Guenther
richard.guent...@gmail.com wrote:
On Thu, Apr
On Fri, Apr 13, 2012 at 2:18 PM, Igor Zamyatin izamya...@gmail.com wrote:
On Thu, Apr 12, 2012 at 5:01 PM, Andrey Belevantsev a...@ispras.ru wrote:
On 12.04.2012 16:38, Richard Guenther wrote:
On Thu, Apr 12, 2012 at 2:36 PM, Igor Zamyatinizamya...@gmail.com
wrote:
On Thu, Apr 12, 2012 at
On 13.04.2012 14:18, Igor Zamyatin wrote:
On Thu, Apr 12, 2012 at 5:01 PM, Andrey Belevantseva...@ispras.ru wrote:
On 12.04.2012 16:38, Richard Guenther wrote:
On Thu, Apr 12, 2012 at 2:36 PM, Igor Zamyatinizamya...@gmail.com
wrote:
On Thu, Apr 12, 2012 at 4:24 PM, Richard Guenther
On Wed, Apr 11, 2012 at 5:38 PM, Andi Kleen a...@firstfloor.org wrote:
Igor Zamyatin izamya...@gmail.com writes:
Hi All!
It is known that imul placement is rather critical for Atom processors
and changes try to improve imul scheduling for Atom.
This gives +5% performance on several tests
On Wed, Apr 11, 2012 at 6:10 PM, Richard Guenther
richard.guent...@gmail.com wrote:
On Wed, Apr 11, 2012 at 3:38 PM, Andi Kleen a...@firstfloor.org wrote:
Igor Zamyatin izamya...@gmail.com writes:
Hi All!
It is known that imul placement is rather critical for Atom processors
and changes try
On Thu, Apr 12, 2012 at 12:20 PM, Igor Zamyatin izamya...@gmail.com wrote:
On Wed, Apr 11, 2012 at 6:10 PM, Richard Guenther
richard.guent...@gmail.com wrote:
On Wed, Apr 11, 2012 at 3:38 PM, Andi Kleen a...@firstfloor.org wrote:
Igor Zamyatin izamya...@gmail.com writes:
Hi All!
It is
Can atom execute two IMUL in parallel? Or what exactly is the pipeline
behavior?
As I understand from Intel's optimization reference manual, the behavior is as
follows: if the instruction immediately following IMUL has shorter latency,
execution is stalled for 4 cycles (which is IMUL's
On Thu, Apr 12, 2012 at 2:00 PM, Alexander Monakov amona...@ispras.ru wrote:
Can atom execute two IMUL in parallel? Or what exactly is the pipeline
behavior?
As I understand from Intel's optimization reference manual, the behavior is as
follows: if the instruction immediately following IMUL
On Thu, Apr 12, 2012 at 4:24 PM, Richard Guenther
richard.guent...@gmail.com wrote:
On Thu, Apr 12, 2012 at 2:00 PM, Alexander Monakov amona...@ispras.ru wrote:
Can atom execute two IMUL in parallel? Or what exactly is the pipeline
behavior?
As I understand from Intel's optimization
On Thu, Apr 12, 2012 at 2:36 PM, Igor Zamyatin izamya...@gmail.com wrote:
On Thu, Apr 12, 2012 at 4:24 PM, Richard Guenther
richard.guent...@gmail.com wrote:
On Thu, Apr 12, 2012 at 2:00 PM, Alexander Monakov amona...@ispras.ru
wrote:
Can atom execute two IMUL in parallel? Or what exactly
On 12.04.2012 16:38, Richard Guenther wrote:
On Thu, Apr 12, 2012 at 2:36 PM, Igor Zamyatinizamya...@gmail.com wrote:
On Thu, Apr 12, 2012 at 4:24 PM, Richard Guenther
richard.guent...@gmail.com wrote:
On Thu, Apr 12, 2012 at 2:00 PM, Alexander Monakovamona...@ispras.ru wrote:
Can atom
2012/4/12 Andrey Belevantsev a...@ispras.ru:
On 12.04.2012 16:38, Richard Guenther wrote:
On Thu, Apr 12, 2012 at 2:36 PM, Igor Zamyatinizamya...@gmail.com
wrote:
On Thu, Apr 12, 2012 at 4:24 PM, Richard Guenther
richard.guent...@gmail.com wrote:
On Thu, Apr 12, 2012 at 2:00 PM,
On 12.04.2012 17:54, Richard Guenther wrote:
2012/4/12 Andrey Belevantseva...@ispras.ru:
On 12.04.2012 16:38, Richard Guenther wrote:
On Thu, Apr 12, 2012 at 2:36 PM, Igor Zamyatinizamya...@gmail.com
wrote:
On Thu, Apr 12, 2012 at 4:24 PM, Richard Guenther
richard.guent...@gmail.com
2012/4/12 Andrey Belevantsev a...@ispras.ru:
On 12.04.2012 17:54, Richard Guenther wrote:
2012/4/12 Andrey Belevantseva...@ispras.ru:
On 12.04.2012 16:38, Richard Guenther wrote:
On Thu, Apr 12, 2012 at 2:36 PM, Igor Zamyatinizamya...@gmail.com
wrote:
On Thu, Apr 12, 2012 at 4:24 PM,
Hi All!
It is known that imul placement is rather critical for Atom processors
and changes try to improve imul scheduling for Atom.
This gives +5% performance on several tests from new OA 2.0 testsuite
from EEMBC.
Tested for i386 and x86-64, ok for trunk?
ChangeLog:
2012-04-10 Yuri
Igor Zamyatin izamya...@gmail.com writes:
Hi All!
It is known that imul placement is rather critical for Atom processors
and changes try to improve imul scheduling for Atom.
This gives +5% performance on several tests from new OA 2.0 testsuite
from EEMBC.
Tested for i386 and x86-64, ok
On Wed, Apr 11, 2012 at 3:38 PM, Andi Kleen a...@firstfloor.org wrote:
Igor Zamyatin izamya...@gmail.com writes:
Hi All!
It is known that imul placement is rather critical for Atom processors
and changes try to improve imul scheduling for Atom.
This gives +5% performance on several tests
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