On Apr 08 2022, Patrick O'Neill wrote:
> It looks like the file:
> gcc/config/nds32/linux.h
> interacts with the macro:
> #define HAVE_sync_compare_and_swaphi 1
>
> I'm not sure if that's the correct way to do it/if this is defined in a
> different way for targets like x86/ARM/etc.
They are norma
Hi Pan RZ,
I appreciate the help - that's a good starting point for the macros.
It looks like the file:
gcc/config/nds32/linux.h
interacts with the macro:
#define HAVE_sync_compare_and_swaphi 1
I'm not sure if that's the correct way to do it/if this is defined in a
different way for targets lik
Hi Patrick,
We are more than delighted to hear that you'd like to implement inlining
subword atomic load/store and exchange as well!
I searched for these macros in the gcc codebase, and it seems like the
internal logic that defines ATOMIC_* builtin macros can be found at
gcc/c-family/c-cpp
Hi RZ Pan,
I'll start working on the atomic store/exchange stuff. It shouldn't be
too difficult to add since it will have similar masking logic to
atomic fetch.
Also - I briefly looked and couldn't find the place where those macro's
values for RISC-V are defined in GCC. If anyone can point me in
Hi Patrick,
Glad to know that efforts have been made to add inlining subword atomic supports into gcc.
The patch looks great so far, yet as Andreas Schwab has pointed out (at
riscv-collab/riscv-gcc#337), looks like it only contains atomic fetch stuff. Just wondering
do you have further plans t
RISC-V has no support for subword atomic operations; code currently
generates libatomic library calls.
This patch changes the default behavior to inline subword atomic calls
(using the same logic as the existing library call).
Behavior can be specified using the -minline-atomics and
-mno-inline-a
