Re: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET

[Uros Bizjak]

On Mon, Sep 18, 2017 at 11:58 AM, Uros Bizjak  wrote:

>> gcc/
>>
>> * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET): New.
>> (OPTION_MASK_ISA_SHSTK_SET): Likewise.
>> (OPTION_MASK_ISA_IBT_UNSET): Likewise.
>> (OPTION_MASK_ISA_SHSTK_UNSET): Likewise.
>> (ix86_handle_option): Add -mibt, -mshstk, -mcet handling.
>> * config.gcc (extra_headers): Add cetintrin.h for x86 targets.
>> (extra_objs): Add cet.o for Linux/x86 targets.
>> (tmake_file): Add i386/t-cet for Linux/x86 targets.
>> * config/i386/cet.c: New file.
>> * config/i386/cetintrin.h: Likewise.
>> * config/i386/t-cet: Likewise.
>> * config/i386/cpuid.h (bit_SHSTK): New.
>> (bit_IBT): Likewise.
>> * config/i386/driver-i386.c (host_detect_local_cpu): Detect and
>> pass IBT and SHSTK bits.
>> * config/i386/i386-builtin-types.def
>> (VOID_FTYPE_UNSIGNED_PVOID): New.
>> (VOID_FTYPE_UINT64_PVOID): Likewise.
>> * config/i386/i386-builtin.def: Add CET intrinsics.
>> * config/i386/i386-c.c (ix86_target_macros_internal): Add
>> OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling.
>> * config/i386/i386-passes.def: Add pass_insert_endbranch pass.
>> * config/i386/i386-protos.h (make_pass_insert_endbranch): New
>> prototype.
>> * config/i386/i386.c (rest_of_insert_endbranch): New.
>> (pass_data_insert_endbranch): Likewise.
>> (pass_insert_endbranch): Likewise.
>> (make_pass_insert_endbranch): Likewise.
>> (ix86_notrack_prefixed_insn_p): Likewise.
>> (ix86_target_string): Add -mibt, -mshstk flags.
>> (ix86_option_override_internal): Add flag_instrument_control_flow
>> processing.
>> (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk.
>> (ix86_print_operand): Add 'notrack' prefix output.
>> (ix86_init_mmx_sse_builtins): Add CET intrinsics.
>> (ix86_expand_builtin): Expand CET intrinsics.
>> (x86_output_mi_thunk): Add 'endbranch' instruction.
>> * config/i386/i386.h (TARGET_IBT): New.
>> (TARGET_IBT_P): Likewise.
>> (TARGET_SHSTK): Likewise.
>> (TARGET_SHSTK_P): Likewise.
>> * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP,
>> UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP,
>> UNSPECV_WRSS, UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY.
>> (builtin_setjmp_setup): New pattern.
>> (builtin_longjmp): Likewise.
>> (rdssp): Likewise.
>> (incssp): Likewise.
>> (saveprevssp): Likewise.
>> (rstorssp): Likewise.
>> (wrss): Likewise.
>> (wruss): Likewise.
>> (setssbsy): Likewise.
>> (clrssbsy): Likewise.
>> (nop_endbr): Likewise.
>> * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch
>> options.
>> * config/i386/immintrin.h: Include .
>> * config/i386/linux-common.h
>> (file_end_indicate_exec_stack_and_cet): New prototype.
>> (TARGET_ASM_FILE_END): New.

This patch introduced following warnings during the compilation:

../../git/gcc/gcc/config/i386/i386.md:20072:1: warning: operand 0 missing mode?
../../git/gcc/gcc/config/i386/i386.md:20105:1: warning: operand 0 missing mode?

This warning suggests that operand 0 of rstorssp and clrssbsy needs
their mode defined. If the size of the memory access is not known,
then the mode should be BLKmode (not recommended), otherwise, please
specify the mode explicitly.

Looking a bit further, it looks to me that these new CET patterns
should be defined with SWI48 mode iterators that disable DImode on
32bit targets.

Please consider the attached patch that also includes a couple of
related cleanups. The patch is only lightly tested.

Uros.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 4123edf982f3..649738321673 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -36990,7 +36990,7 @@ rdseed_step:
  op1 = convert_memory_address (Pmode, op0);
  op0 = copy_addr_to_reg (op1);
}
-  emit_insn (GEN_FCN (icode) (gen_rtx_MEM (Pmode, op0)));
+  emit_insn (GEN_FCN (icode) (gen_rtx_MEM (BLKmode, op0)));
   return 0;
 
 case IX86_BUILTIN_WRSSD:
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index d48decbb7d99..74dad48c813e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -18316,8 +18316,7 @@
 
   mem = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
   3 * GET_MODE_SIZE (Pmode)));
-  reg_ssp = gen_reg_rtx (Pmode);
-  emit_insn (gen_rtx_SET (reg_ssp, const0_rtx));
+  reg_ssp = force_reg (Pmode, const0_rtx);
   emit_insn ((Pmode == SImode)
  ? gen_rdsspsi (reg_ssp, reg_ssp)
  : gen_rdsspdi (reg_ssp, reg_ssp));
@@ -18361,8 +18360,7 @@
   /* Get current shadow stack pointer.  The code below will check if
 SHSTK feature is enabled.  If it's not enabled RDSSP instruction
 is a NOP.  */
-  reg_ssp = gen_reg_rtx (Pmode);
-  emit_insn (gen_rtx_SET (reg_ssp, const0_rtx));
+  reg_ssp = force_reg (Pmode, const0_rtx);
   emit_insn ((Pmode == SImode)
 ? gen_rdsspsi (reg_ssp, reg_ssp)
 : gen_rdsspdi (reg_ssp, 

Re: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET

[Uros Bizjak]

On Thu, Oct 12, 2017 at 8:45 PM, Tsimbalist, Igor V
<igor.v.tsimbal...@intel.com> wrote:
> Uros,
>
> Attached is an updated patch. The main difference is in option name and 
> attribute name change. Other code is the same.

Trivial changes (if they fall under "trivial" rule) don't need extra
approval, but OK nevertheless.

Thanks,
Uros.

> Igor
>
>
>> -Original Message-
>> From: Tsimbalist, Igor V
>> Sent: Tuesday, September 19, 2017 5:06 PM
>> To: Uros Bizjak <ubiz...@gmail.com>; gcc-patches@gcc.gnu.org
>> Cc: Tsimbalist, Igor V <igor.v.tsimbal...@intel.com>
>> Subject: RE: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET
>>
>> Uros, thank you for the approval. Based on the approval of the first 3 
>> patches
>> (I've submitted them today), I need to adjust option and attribute names. I
>> will resubmit the patch when I fix option and attribute names.
>>
>> Thanks,
>> Igor
>>
>>
>> > -Original Message-
>> > From: Uros Bizjak [mailto:ubiz...@gmail.com]
>> > Sent: Monday, September 18, 2017 11:58 AM
>> > To: gcc-patches@gcc.gnu.org
>> > Cc: Tsimbalist, Igor V <igor.v.tsimbal...@intel.com>; Tsimbalist, Igor
>> > V <igor.v.tsimbal...@intel.com>
>> > Subject: Re: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET
>> >
>> > Hello!
>> >
>> > > gcc/
>> > >
>> > > * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET):
>> > New.
>> > > (OPTION_MASK_ISA_SHSTK_SET): Likewise.
>> > > (OPTION_MASK_ISA_IBT_UNSET): Likewise.
>> > > (OPTION_MASK_ISA_SHSTK_UNSET): Likewise.
>> > > (ix86_handle_option): Add -mibt, -mshstk, -mcet handling.
>> > > * config.gcc (extra_headers): Add cetintrin.h for x86 targets.
>> > > (extra_objs): Add cet.o for Linux/x86 targets.
>> > > (tmake_file): Add i386/t-cet for Linux/x86 targets.
>> > > * config/i386/cet.c: New file.
>> > > * config/i386/cetintrin.h: Likewise.
>> > > * config/i386/t-cet: Likewise.
>> > > * config/i386/cpuid.h (bit_SHSTK): New.
>> > > (bit_IBT): Likewise.
>> > > * config/i386/driver-i386.c (host_detect_local_cpu): Detect and pass
>> > > IBT and SHSTK bits.
>> > > * config/i386/i386-builtin-types.def
>> > > (VOID_FTYPE_UNSIGNED_PVOID): New.
>> > > (VOID_FTYPE_UINT64_PVOID): Likewise.
>> > > * config/i386/i386-builtin.def: Add CET intrinsics.
>> > > * config/i386/i386-c.c (ix86_target_macros_internal): Add
>> > > OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling.
>> > > * config/i386/i386-passes.def: Add pass_insert_endbranch pass.
>> > > * config/i386/i386-protos.h (make_pass_insert_endbranch): New
>> > > prototype.
>> > > * config/i386/i386.c (rest_of_insert_endbranch): New.
>> > > (pass_data_insert_endbranch): Likewise.
>> > > (pass_insert_endbranch): Likewise.
>> > > (make_pass_insert_endbranch): Likewise.
>> > > (ix86_notrack_prefixed_insn_p): Likewise.
>> > > (ix86_target_string): Add -mibt, -mshstk flags.
>> > > (ix86_option_override_internal): Add flag_instrument_control_flow
>> > > processing.
>> > > (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk.
>> > > (ix86_print_operand): Add 'notrack' prefix output.
>> > > (ix86_init_mmx_sse_builtins): Add CET intrinsics.
>> > > (ix86_expand_builtin): Expand CET intrinsics.
>> > > (x86_output_mi_thunk): Add 'endbranch' instruction.
>> > > * config/i386/i386.h (TARGET_IBT): New.
>> > > (TARGET_IBT_P): Likewise.
>> > > (TARGET_SHSTK): Likewise.
>> > > (TARGET_SHSTK_P): Likewise.
>> > > * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP,
>> > > UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP,
>> > UNSPECV_WRSS,
>> > > UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY.
>> > > (builtin_setjmp_setup): New pattern.
>> > > (builtin_longjmp): Likewise.
>> > > (rdssp): Likewise.
>> > > (incssp): Likewise.
>> > > (saveprevssp): Likewise.
>> > > (rstorssp): Likewise.
>> > > (wrss): Likewise.
>> > > (wruss): Likewise.
>> > > (setssbsy): Likewise.
>> > > (clrssbsy): Likewise.
>> > > (nop_endbr): Likewise.
>> > > * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch
>> > > options.
>> > > * config/i386/immintrin.h: Include .
>> > > * config/i386/linux-common.h
>> > > (file_end_indicate_exec_stack_and_cet): New prototype.
>> > > (TARGET_ASM_FILE_END): New.
>> >
>> > LGTM.
>> >
>> > OK for mainline.
>> >
>> > Thanks,
>> > Uros.

RE: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET

[Tsimbalist, Igor V]

Uros,

Attached is an updated patch. The main difference is in option name and 
attribute name change. Other code is the same.

Igor


> -Original Message-
> From: Tsimbalist, Igor V
> Sent: Tuesday, September 19, 2017 5:06 PM
> To: Uros Bizjak <ubiz...@gmail.com>; gcc-patches@gcc.gnu.org
> Cc: Tsimbalist, Igor V <igor.v.tsimbal...@intel.com>
> Subject: RE: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET
> 
> Uros, thank you for the approval. Based on the approval of the first 3 patches
> (I've submitted them today), I need to adjust option and attribute names. I
> will resubmit the patch when I fix option and attribute names.
> 
> Thanks,
> Igor
> 
> 
> > -Original Message-
> > From: Uros Bizjak [mailto:ubiz...@gmail.com]
> > Sent: Monday, September 18, 2017 11:58 AM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Tsimbalist, Igor V <igor.v.tsimbal...@intel.com>; Tsimbalist, Igor
> > V <igor.v.tsimbal...@intel.com>
> > Subject: Re: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET
> >
> > Hello!
> >
> > > gcc/
> > >
> > > * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET):
> > New.
> > > (OPTION_MASK_ISA_SHSTK_SET): Likewise.
> > > (OPTION_MASK_ISA_IBT_UNSET): Likewise.
> > > (OPTION_MASK_ISA_SHSTK_UNSET): Likewise.
> > > (ix86_handle_option): Add -mibt, -mshstk, -mcet handling.
> > > * config.gcc (extra_headers): Add cetintrin.h for x86 targets.
> > > (extra_objs): Add cet.o for Linux/x86 targets.
> > > (tmake_file): Add i386/t-cet for Linux/x86 targets.
> > > * config/i386/cet.c: New file.
> > > * config/i386/cetintrin.h: Likewise.
> > > * config/i386/t-cet: Likewise.
> > > * config/i386/cpuid.h (bit_SHSTK): New.
> > > (bit_IBT): Likewise.
> > > * config/i386/driver-i386.c (host_detect_local_cpu): Detect and pass
> > > IBT and SHSTK bits.
> > > * config/i386/i386-builtin-types.def
> > > (VOID_FTYPE_UNSIGNED_PVOID): New.
> > > (VOID_FTYPE_UINT64_PVOID): Likewise.
> > > * config/i386/i386-builtin.def: Add CET intrinsics.
> > > * config/i386/i386-c.c (ix86_target_macros_internal): Add
> > > OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling.
> > > * config/i386/i386-passes.def: Add pass_insert_endbranch pass.
> > > * config/i386/i386-protos.h (make_pass_insert_endbranch): New
> > > prototype.
> > > * config/i386/i386.c (rest_of_insert_endbranch): New.
> > > (pass_data_insert_endbranch): Likewise.
> > > (pass_insert_endbranch): Likewise.
> > > (make_pass_insert_endbranch): Likewise.
> > > (ix86_notrack_prefixed_insn_p): Likewise.
> > > (ix86_target_string): Add -mibt, -mshstk flags.
> > > (ix86_option_override_internal): Add flag_instrument_control_flow
> > > processing.
> > > (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk.
> > > (ix86_print_operand): Add 'notrack' prefix output.
> > > (ix86_init_mmx_sse_builtins): Add CET intrinsics.
> > > (ix86_expand_builtin): Expand CET intrinsics.
> > > (x86_output_mi_thunk): Add 'endbranch' instruction.
> > > * config/i386/i386.h (TARGET_IBT): New.
> > > (TARGET_IBT_P): Likewise.
> > > (TARGET_SHSTK): Likewise.
> > > (TARGET_SHSTK_P): Likewise.
> > > * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP,
> > > UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP,
> > UNSPECV_WRSS,
> > > UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY.
> > > (builtin_setjmp_setup): New pattern.
> > > (builtin_longjmp): Likewise.
> > > (rdssp): Likewise.
> > > (incssp): Likewise.
> > > (saveprevssp): Likewise.
> > > (rstorssp): Likewise.
> > > (wrss): Likewise.
> > > (wruss): Likewise.
> > > (setssbsy): Likewise.
> > > (clrssbsy): Likewise.
> > > (nop_endbr): Likewise.
> > > * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch
> > > options.
> > > * config/i386/immintrin.h: Include .
> > > * config/i386/linux-common.h
> > > (file_end_indicate_exec_stack_and_cet): New prototype.
> > > (TARGET_ASM_FILE_END): New.
> >
> > LGTM.
> >
> > OK for mainline.
> >
> > Thanks,
> > Uros.


0004-Update-x86-backend-to-enable-Intel-CET.PATCH
Description: 0004-Update-x86-backend-to-enable-Intel-CET.PATCH

RE: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET

[Tsimbalist, Igor V]

Uros, thank you for the approval. Based on the approval of the first 3 patches 
(I've submitted them today), I need to adjust option and attribute names. I 
will resubmit the patch when I fix option and attribute names.

Thanks,
Igor


> -Original Message-
> From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Monday, September 18, 2017 11:58 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Tsimbalist, Igor V <igor.v.tsimbal...@intel.com>; Tsimbalist, Igor V
> <igor.v.tsimbal...@intel.com>
> Subject: Re: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET
> 
> Hello!
> 
> > gcc/
> >
> > * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET):
> New.
> > (OPTION_MASK_ISA_SHSTK_SET): Likewise.
> > (OPTION_MASK_ISA_IBT_UNSET): Likewise.
> > (OPTION_MASK_ISA_SHSTK_UNSET): Likewise.
> > (ix86_handle_option): Add -mibt, -mshstk, -mcet handling.
> > * config.gcc (extra_headers): Add cetintrin.h for x86 targets.
> > (extra_objs): Add cet.o for Linux/x86 targets.
> > (tmake_file): Add i386/t-cet for Linux/x86 targets.
> > * config/i386/cet.c: New file.
> > * config/i386/cetintrin.h: Likewise.
> > * config/i386/t-cet: Likewise.
> > * config/i386/cpuid.h (bit_SHSTK): New.
> > (bit_IBT): Likewise.
> > * config/i386/driver-i386.c (host_detect_local_cpu): Detect and pass
> > IBT and SHSTK bits.
> > * config/i386/i386-builtin-types.def
> > (VOID_FTYPE_UNSIGNED_PVOID): New.
> > (VOID_FTYPE_UINT64_PVOID): Likewise.
> > * config/i386/i386-builtin.def: Add CET intrinsics.
> > * config/i386/i386-c.c (ix86_target_macros_internal): Add
> > OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling.
> > * config/i386/i386-passes.def: Add pass_insert_endbranch pass.
> > * config/i386/i386-protos.h (make_pass_insert_endbranch): New
> > prototype.
> > * config/i386/i386.c (rest_of_insert_endbranch): New.
> > (pass_data_insert_endbranch): Likewise.
> > (pass_insert_endbranch): Likewise.
> > (make_pass_insert_endbranch): Likewise.
> > (ix86_notrack_prefixed_insn_p): Likewise.
> > (ix86_target_string): Add -mibt, -mshstk flags.
> > (ix86_option_override_internal): Add flag_instrument_control_flow
> > processing.
> > (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk.
> > (ix86_print_operand): Add 'notrack' prefix output.
> > (ix86_init_mmx_sse_builtins): Add CET intrinsics.
> > (ix86_expand_builtin): Expand CET intrinsics.
> > (x86_output_mi_thunk): Add 'endbranch' instruction.
> > * config/i386/i386.h (TARGET_IBT): New.
> > (TARGET_IBT_P): Likewise.
> > (TARGET_SHSTK): Likewise.
> > (TARGET_SHSTK_P): Likewise.
> > * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP,
> > UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP,
> UNSPECV_WRSS,
> > UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY.
> > (builtin_setjmp_setup): New pattern.
> > (builtin_longjmp): Likewise.
> > (rdssp): Likewise.
> > (incssp): Likewise.
> > (saveprevssp): Likewise.
> > (rstorssp): Likewise.
> > (wrss): Likewise.
> > (wruss): Likewise.
> > (setssbsy): Likewise.
> > (clrssbsy): Likewise.
> > (nop_endbr): Likewise.
> > * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch
> > options.
> > * config/i386/immintrin.h: Include .
> > * config/i386/linux-common.h
> > (file_end_indicate_exec_stack_and_cet): New prototype.
> > (TARGET_ASM_FILE_END): New.
> 
> LGTM.
> 
> OK for mainline.
> 
> Thanks,
> Uros.

Re: 0004-Part-4.-Update-x86-backend-to-enable-Intel-CET

[Uros Bizjak]

Hello!

> gcc/
>
> * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET): New.
> (OPTION_MASK_ISA_SHSTK_SET): Likewise.
> (OPTION_MASK_ISA_IBT_UNSET): Likewise.
> (OPTION_MASK_ISA_SHSTK_UNSET): Likewise.
> (ix86_handle_option): Add -mibt, -mshstk, -mcet handling.
> * config.gcc (extra_headers): Add cetintrin.h for x86 targets.
> (extra_objs): Add cet.o for Linux/x86 targets.
> (tmake_file): Add i386/t-cet for Linux/x86 targets.
> * config/i386/cet.c: New file.
> * config/i386/cetintrin.h: Likewise.
> * config/i386/t-cet: Likewise.
> * config/i386/cpuid.h (bit_SHSTK): New.
> (bit_IBT): Likewise.
> * config/i386/driver-i386.c (host_detect_local_cpu): Detect and
> pass IBT and SHSTK bits.
> * config/i386/i386-builtin-types.def
> (VOID_FTYPE_UNSIGNED_PVOID): New.
> (VOID_FTYPE_UINT64_PVOID): Likewise.
> * config/i386/i386-builtin.def: Add CET intrinsics.
> * config/i386/i386-c.c (ix86_target_macros_internal): Add
> OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling.
> * config/i386/i386-passes.def: Add pass_insert_endbranch pass.
> * config/i386/i386-protos.h (make_pass_insert_endbranch): New
> prototype.
> * config/i386/i386.c (rest_of_insert_endbranch): New.
> (pass_data_insert_endbranch): Likewise.
> (pass_insert_endbranch): Likewise.
> (make_pass_insert_endbranch): Likewise.
> (ix86_notrack_prefixed_insn_p): Likewise.
> (ix86_target_string): Add -mibt, -mshstk flags.
> (ix86_option_override_internal): Add flag_instrument_control_flow
> processing.
> (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk.
> (ix86_print_operand): Add 'notrack' prefix output.
> (ix86_init_mmx_sse_builtins): Add CET intrinsics.
> (ix86_expand_builtin): Expand CET intrinsics.
> (x86_output_mi_thunk): Add 'endbranch' instruction.
> * config/i386/i386.h (TARGET_IBT): New.
> (TARGET_IBT_P): Likewise.
> (TARGET_SHSTK): Likewise.
> (TARGET_SHSTK_P): Likewise.
> * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP,
> UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP,
> UNSPECV_WRSS, UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY.
> (builtin_setjmp_setup): New pattern.
> (builtin_longjmp): Likewise.
> (rdssp): Likewise.
> (incssp): Likewise.
> (saveprevssp): Likewise.
> (rstorssp): Likewise.
> (wrss): Likewise.
> (wruss): Likewise.
> (setssbsy): Likewise.
> (clrssbsy): Likewise.
> (nop_endbr): Likewise.
> * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch
> options.
> * config/i386/immintrin.h: Include .
> * config/i386/linux-common.h
> (file_end_indicate_exec_stack_and_cet): New prototype.
> (TARGET_ASM_FILE_END): New.

LGTM.

OK for mainline.

Thanks,
Uros.