On 3/5/18 8:55 AM, Segher Boessenkool wrote:
> On Sat, Mar 03, 2018 at 10:55:28PM -0600, Peter Bergner wrote:
>> The simple fix here is to just verify the memory_operand is not an altivec
>> mem operand before calling rs6000_emit_le_vsx_move.
>>
>> This passed bootstrap and regtesting on powerpc64l
Hi Peter,
On Sat, Mar 03, 2018 at 10:55:28PM -0600, Peter Bergner wrote:
> In PR84264, we hit an assert in rs6000_emit_le_vsx_store causing an ICE
> in LRA. We get there, because LRA called the movv4si expander to generate
> a spill and the mov pattern calls rs6000_emit_le_vsx_move which in turn
On 3/4/18 4:00 AM, Jakub Jelinek wrote:
> On Sat, Mar 03, 2018 at 10:55:28PM -0600, Peter Bergner wrote:
>> gcc/
>> PR target/84264
>> * config/rs6000/vector.md:
>
> The ChangeLog entry needs fixing.
>
> Otherwise I'll defer to powerpc maintainers.
Hmm, too sloopy on my part! Forgot t
On Sat, Mar 03, 2018 at 10:55:28PM -0600, Peter Bergner wrote:
> In PR84264, we hit an assert in rs6000_emit_le_vsx_store causing an ICE
> in LRA. We get there, because LRA called the movv4si expander to generate
> a spill and the mov pattern calls rs6000_emit_le_vsx_move which in turn
> calls rs6
