Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
Hi, Adhemerval I cornered Honza during his visit to IBM Research to help me understand my concerns with the function. The code for *hold does: + tree fenv_var = create_tmp_var (double_type_node, NULL); + + tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs); + + tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var); The code for *clear does: + tree fenv_clear = create_tmp_var (double_type_node, NULL); + + tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs); + + tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var); Note that *clear creates fenv_clear, but uses fenv_var that was created earlier for *hold (probably should have been fenv_hold) or something to distinguish it. The code for *update does: + tree old_fenv = create_tmp_var (double_type_node, NULL); + tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs); + + tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, update_mffs); But it never actually uses old_fenv that it obtained from the call to call_mffs(). The current implementation is trying to follow the punning and conversions in the C code, but, according to Honza, it does not need to. It should not need the temporary variable nor the MODIFY_EXPR. The implementation of *update shows that the temporary really is not necessary because it (accidentally) is not referenced and not used. The code for *hold and *clear should be converted to the style of *update, without the temporary. The later instruction selection and register allocation in GCC should handle the conversion between double_type and uint64_type through the VIEW_CONVERT_EXPR without an explicit temporary. The call to mffs can be inserted directly into the rest of the tree being built (creating a large and ugly tree). Then the final COMPOUND_EXPR is not needed in any of the cases, as it already is omitted in the *update case. The accidental omission of a reference to old_fenv is what allowed it to be omitted from the *update case, which prompted my original question. Thanks, David
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
On Thu, 4 Sep 2014, Adhemerval Zanella wrote: While at it, may I propose another change on top of this? I've noticed the test case is rather slow, it certainly takes much more time than the average one, I've seen elapsed times of well over a minute on reasonably fast hardware and occasionally a timeout midway through even though the test case was otherwise progressing just fine. I think lock contention or unrelated system activity such as hardware interrupts (think a busy network!) may contribute to it for systems using LL/SC loops for atomicity. So I think the default timeout that's used for really quick tests should be extended a bit. I propose a factor of 2, just not to make it too excessive, at least for the beginning (maybe it'll have to be higher eventually). Do you mind if I incorporate this change on my patchset? I missed your e-mail previously, sorry. Surely I don't! Thanks. Maciej
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
On Wed, 3 Sep 2014, Uros Bizjak wrote: So I think the default timeout that's used for really quick tests should be extended a bit. I propose a factor of 2, just not to make it too excessive, at least for the beginning (maybe it'll have to be higher eventually). Or you can just lower the iteration count as I have to do for alpha. Thanks for the tip. Hmm, frankly I think setting the timeout factor has a greater chance to be maintenance free (no need to add further targets as they get discovered) and I think a bit more flexible too. E.g. someone may (and often will, if they care about their test run times) override the global board timeout to say 5 from the default of 300 seconds in their board description file for their super-fast test system and the timeout factor will still do its work here. Whereas with the default timeout applying here the lowest timeout setting that works here will be the global lower limit, also for tests that are inherently faster than this one (i.e. don't loop over thousands of iterations or in fact have no loop at all and just execute in a fall-through manner) even on systems where lock contention is not an issue. If you think that extending the timeout for everyone is too big a hammer here, then perhaps we could conditionalise it on target_has_contentious_atomics or suchlike and list the right targets there, but frankly I think it would be a bit of an overkill (and my observation above about looped vs non-looped tests still applies). Thoughts? Maciej
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
On 03-09-2014 11:01, Maciej W. Rozycki wrote:
On Tue, 2 Sep 2014, Adhemerval Zanella wrote:
Ping.
On 19-08-2014 13:54, Adhemerval Zanella wrote:
Ping.
On 06-08-2014 17:21, Adhemerval Zanella wrote:
On 01-08-2014 12:31, Joseph S. Myers wrote:
On Thu, 31 Jul 2014, David Edelsohn wrote:
Thanks for implementing the FENV support. The patch generally looks
good to me.
My one concern is a detail in the implementation of update. I do not
have enough experience with GENERIC to verify the details and it seems
like it is missing building an outer COMPOUND_EXPR containing
update_mffs and the CALL_EXPR for update mtfsf.
I suppose what's actually odd there is that you have
+ tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv,
call_mffs);
+
+ tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node,
update_mffs);
so you build a MODIFY_EXPR in void_type_node but then convert it with a
VIEW_CONVERT_EXPR. If you'd built the MODIFY_EXPR in double_type_node
then the VIEW_CONVERT_EXPR would be meaningful (the value of an
assignment
a = b being the new value of a), but reinterpreting a void value doesn't
make sense. Or you could probably just use call_mffs directly in the
VIEW_CONVERT_EXPR without explicitly creating the old_fenv variable.
Thanks for the review Josephm. I have changed to avoid the void
reinterpretation
and use call_mffs directly. I have also removed the the mask generation
in 'clear'
from your previous message, it is now reusing the mas used in
feholdexcept. The
testcase patch is the same as before.
Checked on both linux-powerpc64/powerpc64le and no regressions found.
--
2014-08-06 Adhemerval Zanella azane...@linux.vnet.ibm.com
gcc:
* config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): New
function.
gcc/testsuite:
* gcc.dg/atomic/c11-atomic-exec-5.c
(test_main_long_double_add_overflow): Define and run only for
LDBL_MANT_DIG != 106.
(test_main_complex_long_double_add_overflow): Likewise.
(test_main_long_double_sub_overflow): Likewise.
(test_main_complex_long_double_sub_overflow): Likewise.
FWIW I pushed it through regression testing across my usual set of
powerpc-linux-gnu multilibs with the results (for c11-atomic-exec-5.c) as
follows:
-mcpu=603ePASS
-mcpu=603e -msoft-float UNSUPPORTED
-mcpu=8540 -mfloat-gprs=single -mspe=yes -mabi=speUNSUPPORTED
-mcpu=8548 -mfloat-gprs=double -mspe=yes -mabi=speUNSUPPORTED
-mcpu=7400 -maltivec -mabi=altivecPASS
-mcpu=e6500 -maltivec -mabi=altivec PASS
-mcpu=e5500 -m64 PASS
-mcpu=e6500 -m64 -maltivec -mabi=altivec PASS
Thanks for testing it, I'll to add these permutations on my own testbench.
(floating-point environment is of course unsupported for soft-float
targets and for the SPE FPU another change is required to implement
floating-point environment handling to complement one proposed here).
No regressions otherwise.
While at it, may I propose another change on top of this?
I've noticed the test case is rather slow, it certainly takes much more
time than the average one, I've seen elapsed times of well over a minute
on reasonably fast hardware and occasionally a timeout midway through even
though the test case was otherwise progressing just fine. I think lock
contention or unrelated system activity such as hardware interrupts (think
a busy network!) may contribute to it for systems using LL/SC loops for
atomicity.
So I think the default timeout that's used for really quick tests should
be extended a bit. I propose a factor of 2, just not to make it too
excessive, at least for the beginning (maybe it'll have to be higher
eventually).
Do you mind if I incorporate this change on my patchset?
OK?
2014-09-03 Maciej W. Rozycki ma...@codesourcery.com
gcc/testsuite/
* gcc.dg/atomic/c11-atomic-exec-5.c (dg-timeout-factor): New
setting.
Maciej
gcc-test-c11-atomic-exec-5-timeout-factor.diff
Index: gcc-fsf-trunk-quilt/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
===
--- gcc-fsf-trunk-quilt.orig/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
2014-09-02 17:34:06.718927043 +0100
+++ gcc-fsf-trunk-quilt/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
2014-09-03 14:51:12.958927233 +0100
@@ -9,6 +9,7 @@
/* { dg-additional-options -D_XOPEN_SOURCE=600 { target
*-*-solaris2.1[0-9]* } } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-require-effective-target pthread } */
+/* { dg-timeout-factor 2 } */
#include fenv.h
#include float.h
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
On Tue, 2 Sep 2014, Adhemerval Zanella wrote:
Ping.
On 19-08-2014 13:54, Adhemerval Zanella wrote:
Ping.
On 06-08-2014 17:21, Adhemerval Zanella wrote:
On 01-08-2014 12:31, Joseph S. Myers wrote:
On Thu, 31 Jul 2014, David Edelsohn wrote:
Thanks for implementing the FENV support. The patch generally looks
good to me.
My one concern is a detail in the implementation of update. I do not
have enough experience with GENERIC to verify the details and it seems
like it is missing building an outer COMPOUND_EXPR containing
update_mffs and the CALL_EXPR for update mtfsf.
I suppose what's actually odd there is that you have
+ tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv,
call_mffs);
+
+ tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node,
update_mffs);
so you build a MODIFY_EXPR in void_type_node but then convert it with a
VIEW_CONVERT_EXPR. If you'd built the MODIFY_EXPR in double_type_node
then the VIEW_CONVERT_EXPR would be meaningful (the value of an
assignment
a = b being the new value of a), but reinterpreting a void value doesn't
make sense. Or you could probably just use call_mffs directly in the
VIEW_CONVERT_EXPR without explicitly creating the old_fenv variable.
Thanks for the review Josephm. I have changed to avoid the void
reinterpretation
and use call_mffs directly. I have also removed the the mask generation
in 'clear'
from your previous message, it is now reusing the mas used in
feholdexcept. The
testcase patch is the same as before.
Checked on both linux-powerpc64/powerpc64le and no regressions found.
--
2014-08-06 Adhemerval Zanella azane...@linux.vnet.ibm.com
gcc:
* config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): New
function.
gcc/testsuite:
* gcc.dg/atomic/c11-atomic-exec-5.c
(test_main_long_double_add_overflow): Define and run only for
LDBL_MANT_DIG != 106.
(test_main_complex_long_double_add_overflow): Likewise.
(test_main_long_double_sub_overflow): Likewise.
(test_main_complex_long_double_sub_overflow): Likewise.
FWIW I pushed it through regression testing across my usual set of
powerpc-linux-gnu multilibs with the results (for c11-atomic-exec-5.c) as
follows:
-mcpu=603e PASS
-mcpu=603e -msoft-float UNSUPPORTED
-mcpu=8540 -mfloat-gprs=single -mspe=yes -mabi=spe UNSUPPORTED
-mcpu=8548 -mfloat-gprs=double -mspe=yes -mabi=spe UNSUPPORTED
-mcpu=7400 -maltivec -mabi=altivec PASS
-mcpu=e6500 -maltivec -mabi=altivec PASS
-mcpu=e5500 -m64PASS
-mcpu=e6500 -m64 -maltivec -mabi=altivecPASS
(floating-point environment is of course unsupported for soft-float
targets and for the SPE FPU another change is required to implement
floating-point environment handling to complement one proposed here).
No regressions otherwise.
While at it, may I propose another change on top of this?
I've noticed the test case is rather slow, it certainly takes much more
time than the average one, I've seen elapsed times of well over a minute
on reasonably fast hardware and occasionally a timeout midway through even
though the test case was otherwise progressing just fine. I think lock
contention or unrelated system activity such as hardware interrupts (think
a busy network!) may contribute to it for systems using LL/SC loops for
atomicity.
So I think the default timeout that's used for really quick tests should
be extended a bit. I propose a factor of 2, just not to make it too
excessive, at least for the beginning (maybe it'll have to be higher
eventually).
OK?
2014-09-03 Maciej W. Rozycki ma...@codesourcery.com
gcc/testsuite/
* gcc.dg/atomic/c11-atomic-exec-5.c (dg-timeout-factor): New
setting.
Maciej
gcc-test-c11-atomic-exec-5-timeout-factor.diff
Index: gcc-fsf-trunk-quilt/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
===
--- gcc-fsf-trunk-quilt.orig/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
2014-09-02 17:34:06.718927043 +0100
+++ gcc-fsf-trunk-quilt/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
2014-09-03 14:51:12.958927233 +0100
@@ -9,6 +9,7 @@
/* { dg-additional-options -D_XOPEN_SOURCE=600 { target *-*-solaris2.1[0-9]*
} } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-require-effective-target pthread } */
+/* { dg-timeout-factor 2 } */
#include fenv.h
#include float.h
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
Hello! While at it, may I propose another change on top of this? I've noticed the test case is rather slow, it certainly takes much more time than the average one, I've seen elapsed times of well over a minute on reasonably fast hardware and occasionally a timeout midway through even though the test case was otherwise progressing just fine. I think lock contention or unrelated system activity such as hardware interrupts (think a busy network!) may contribute to it for systems using LL/SC loops for atomicity. So I think the default timeout that's used for really quick tests should be extended a bit. I propose a factor of 2, just not to make it too excessive, at least for the beginning (maybe it'll have to be higher eventually). Or you can just lower the iteration count as I have to do for alpha. Uros.
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
On Wed, 3 Sep 2014, Maciej W. Rozycki wrote: (floating-point environment is of course unsupported for soft-float targets and for the SPE FPU another change is required to implement floating-point environment handling to complement one proposed here). Support for SPE will depend on the C library just as soft-float support will, because of the need to have trapping on exceptions other than inexact enabled in the processor at all times with the kernel then using the prctl settings to determine whether that trap is for emulation or to produce SIGFPE. (The relevant support is in glibc 2.19 for soft-float and e500, in the form of __atomic_feholdexcept, __atomic_feclearexcept and __atomic_feupdateenv functions. I intend to implement the GCC side - conditional on being configured for glibc 2.19 or later on the target, as specified with --with-glibc-version or detected by configure's examination of target headers - once the hard-float support is in GCC. I believe the support in question will be identical for soft-float and e500, since it will be calling libc functions instead of manipulating processor state.) -- Joseph S. Myers jos...@codesourcery.com
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
Ping.
On 19-08-2014 13:54, Adhemerval Zanella wrote:
Ping.
On 06-08-2014 17:21, Adhemerval Zanella wrote:
On 01-08-2014 12:31, Joseph S. Myers wrote:
On Thu, 31 Jul 2014, David Edelsohn wrote:
Thanks for implementing the FENV support. The patch generally looks
good to me.
My one concern is a detail in the implementation of update. I do not
have enough experience with GENERIC to verify the details and it seems
like it is missing building an outer COMPOUND_EXPR containing
update_mffs and the CALL_EXPR for update mtfsf.
I suppose what's actually odd there is that you have
+ tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv,
call_mffs);
+
+ tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, update_mffs);
so you build a MODIFY_EXPR in void_type_node but then convert it with a
VIEW_CONVERT_EXPR. If you'd built the MODIFY_EXPR in double_type_node
then the VIEW_CONVERT_EXPR would be meaningful (the value of an assignment
a = b being the new value of a), but reinterpreting a void value doesn't
make sense. Or you could probably just use call_mffs directly in the
VIEW_CONVERT_EXPR without explicitly creating the old_fenv variable.
Thanks for the review Josephm. I have changed to avoid the void
reinterpretation
and use call_mffs directly. I have also removed the the mask generation in
'clear'
from your previous message, it is now reusing the mas used in feholdexcept.
The
testcase patch is the same as before.
Checked on both linux-powerpc64/powerpc64le and no regressions found.
--
2014-08-06 Adhemerval Zanella azane...@linux.vnet.ibm.com
gcc:
* config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): New
function.
gcc/testsuite:
* gcc.dg/atomic/c11-atomic-exec-5.c
(test_main_long_double_add_overflow): Define and run only for
LDBL_MANT_DIG != 106.
(test_main_complex_long_double_add_overflow): Likewise.
(test_main_long_double_sub_overflow): Likewise.
(test_main_complex_long_double_sub_overflow): Likewise.
---
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d088ff6..7d66eb1 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1631,6 +1631,9 @@ static const struct attribute_spec
rs6000_attribute_table[] =
#undef TARGET_CAN_USE_DOLOOP_P
#define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
+
+#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
+#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
/* Processor table. */
@@ -7,6 +33340,80 @@ emit_fusion_gpr_load (rtx *operands)
return ;
}
+/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
+
+static void
+rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
+{
+ if (!TARGET_HARD_FLOAT || !TARGET_FPRS)
+return;
+
+ tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
+ tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
+ tree call_mffs = build_call_expr (mffs, 0);
+
+ /* Generates the equivalent of feholdexcept (fenv_var)
+
+ *fenv_var = __builtin_mffs ();
+ double fenv_hold;
+ *(uint64_t*)fenv_hold = *(uint64_t*)fenv_var 0x0007LL;
+ __builtin_mtfsf (0xff, fenv_hold); */
+
+ /* Mask to clear everything except for the rounding modes and non-IEEE
+ arithmetic flag. */
+ const unsigned HOST_WIDE_INT hold_exception_mask =
+HOST_WIDE_INT_UC (0x0007);
+
+ tree fenv_var = create_tmp_var (double_type_node, NULL);
+
+ tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var,
call_mffs);
+
+ tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
+ tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
+build_int_cst (uint64_type_node, hold_exception_mask));
+
+ tree fenv_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
fenv_llu_and);
+
+ tree hold_mtfsf = build_call_expr (mtfsf, 2,
+build_int_cst (unsigned_type_node, 0xff), fenv_mtfsf);
+
+ *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
+
+ /* Reload the value of fenv_hold to clear the exceptions. */
+
+ *clear = build_call_expr (mtfsf, 2,
+build_int_cst (unsigned_type_node, 0xff), fenv_mtfsf);
+
+ /* Generates the equivalent of feupdateenv (fenv_var)
+
+ double old_fenv = __builtin_mffs ();
+ double fenv_update;
+ *(uint64_t*)fenv_update = (*(uint64_t*)old 0x1f00LL) |
+(*(uint64_t*)fenv_var 0x1ff80fff);
+ __builtin_mtfsf (0xff, fenv_update); */
+
+ const unsigned HOST_WIDE_INT update_exception_mask =
+HOST_WIDE_INT_UC (0x1f00);
+ const unsigned HOST_WIDE_INT new_exception_mask =
+HOST_WIDE_INT_UC (0x1ff80fff);
+
+ tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, call_mffs);
+ tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
+old_llu,
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
Ping.
On 06-08-2014 17:21, Adhemerval Zanella wrote:
On 01-08-2014 12:31, Joseph S. Myers wrote:
On Thu, 31 Jul 2014, David Edelsohn wrote:
Thanks for implementing the FENV support. The patch generally looks
good to me.
My one concern is a detail in the implementation of update. I do not
have enough experience with GENERIC to verify the details and it seems
like it is missing building an outer COMPOUND_EXPR containing
update_mffs and the CALL_EXPR for update mtfsf.
I suppose what's actually odd there is that you have
+ tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv,
call_mffs);
+
+ tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, update_mffs);
so you build a MODIFY_EXPR in void_type_node but then convert it with a
VIEW_CONVERT_EXPR. If you'd built the MODIFY_EXPR in double_type_node
then the VIEW_CONVERT_EXPR would be meaningful (the value of an assignment
a = b being the new value of a), but reinterpreting a void value doesn't
make sense. Or you could probably just use call_mffs directly in the
VIEW_CONVERT_EXPR without explicitly creating the old_fenv variable.
Thanks for the review Josephm. I have changed to avoid the void
reinterpretation
and use call_mffs directly. I have also removed the the mask generation in
'clear'
from your previous message, it is now reusing the mas used in feholdexcept.
The
testcase patch is the same as before.
Checked on both linux-powerpc64/powerpc64le and no regressions found.
--
2014-08-06 Adhemerval Zanella azane...@linux.vnet.ibm.com
gcc:
* config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): New
function.
gcc/testsuite:
* gcc.dg/atomic/c11-atomic-exec-5.c
(test_main_long_double_add_overflow): Define and run only for
LDBL_MANT_DIG != 106.
(test_main_complex_long_double_add_overflow): Likewise.
(test_main_long_double_sub_overflow): Likewise.
(test_main_complex_long_double_sub_overflow): Likewise.
---
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d088ff6..7d66eb1 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1631,6 +1631,9 @@ static const struct attribute_spec
rs6000_attribute_table[] =
#undef TARGET_CAN_USE_DOLOOP_P
#define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
+
+#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
+#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
/* Processor table. */
@@ -7,6 +33340,80 @@ emit_fusion_gpr_load (rtx *operands)
return ;
}
+/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
+
+static void
+rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
+{
+ if (!TARGET_HARD_FLOAT || !TARGET_FPRS)
+return;
+
+ tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
+ tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
+ tree call_mffs = build_call_expr (mffs, 0);
+
+ /* Generates the equivalent of feholdexcept (fenv_var)
+
+ *fenv_var = __builtin_mffs ();
+ double fenv_hold;
+ *(uint64_t*)fenv_hold = *(uint64_t*)fenv_var 0x0007LL;
+ __builtin_mtfsf (0xff, fenv_hold); */
+
+ /* Mask to clear everything except for the rounding modes and non-IEEE
+ arithmetic flag. */
+ const unsigned HOST_WIDE_INT hold_exception_mask =
+HOST_WIDE_INT_UC (0x0007);
+
+ tree fenv_var = create_tmp_var (double_type_node, NULL);
+
+ tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
+
+ tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
+ tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
+build_int_cst (uint64_type_node, hold_exception_mask));
+
+ tree fenv_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
fenv_llu_and);
+
+ tree hold_mtfsf = build_call_expr (mtfsf, 2,
+build_int_cst (unsigned_type_node, 0xff), fenv_mtfsf);
+
+ *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
+
+ /* Reload the value of fenv_hold to clear the exceptions. */
+
+ *clear = build_call_expr (mtfsf, 2,
+build_int_cst (unsigned_type_node, 0xff), fenv_mtfsf);
+
+ /* Generates the equivalent of feupdateenv (fenv_var)
+
+ double old_fenv = __builtin_mffs ();
+ double fenv_update;
+ *(uint64_t*)fenv_update = (*(uint64_t*)old 0x1f00LL) |
+(*(uint64_t*)fenv_var 0x1ff80fff);
+ __builtin_mtfsf (0xff, fenv_update); */
+
+ const unsigned HOST_WIDE_INT update_exception_mask =
+HOST_WIDE_INT_UC (0x1f00);
+ const unsigned HOST_WIDE_INT new_exception_mask =
+HOST_WIDE_INT_UC (0x1ff80fff);
+
+ tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, call_mffs);
+ tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
+old_llu, build_int_cst (uint64_type_node, update_exception_mask));
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
On 01-08-2014 12:31, Joseph S. Myers wrote:
On Thu, 31 Jul 2014, David Edelsohn wrote:
Thanks for implementing the FENV support. The patch generally looks
good to me.
My one concern is a detail in the implementation of update. I do not
have enough experience with GENERIC to verify the details and it seems
like it is missing building an outer COMPOUND_EXPR containing
update_mffs and the CALL_EXPR for update mtfsf.
I suppose what's actually odd there is that you have
+ tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv,
call_mffs);
+
+ tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, update_mffs);
so you build a MODIFY_EXPR in void_type_node but then convert it with a
VIEW_CONVERT_EXPR. If you'd built the MODIFY_EXPR in double_type_node
then the VIEW_CONVERT_EXPR would be meaningful (the value of an assignment
a = b being the new value of a), but reinterpreting a void value doesn't
make sense. Or you could probably just use call_mffs directly in the
VIEW_CONVERT_EXPR without explicitly creating the old_fenv variable.
Thanks for the review Josephm. I have changed to avoid the void
reinterpretation
and use call_mffs directly. I have also removed the the mask generation in
'clear'
from your previous message, it is now reusing the mas used in feholdexcept.
The
testcase patch is the same as before.
Checked on both linux-powerpc64/powerpc64le and no regressions found.
--
2014-08-06 Adhemerval Zanella azane...@linux.vnet.ibm.com
gcc:
* config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): New
function.
gcc/testsuite:
* gcc.dg/atomic/c11-atomic-exec-5.c
(test_main_long_double_add_overflow): Define and run only for
LDBL_MANT_DIG != 106.
(test_main_complex_long_double_add_overflow): Likewise.
(test_main_long_double_sub_overflow): Likewise.
(test_main_complex_long_double_sub_overflow): Likewise.
---
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d088ff6..7d66eb1 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1631,6 +1631,9 @@ static const struct attribute_spec
rs6000_attribute_table[] =
#undef TARGET_CAN_USE_DOLOOP_P
#define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
+
+#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
+#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
/* Processor table. */
@@ -7,6 +33340,80 @@ emit_fusion_gpr_load (rtx *operands)
return ;
}
+/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
+
+static void
+rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
+{
+ if (!TARGET_HARD_FLOAT || !TARGET_FPRS)
+return;
+
+ tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
+ tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
+ tree call_mffs = build_call_expr (mffs, 0);
+
+ /* Generates the equivalent of feholdexcept (fenv_var)
+
+ *fenv_var = __builtin_mffs ();
+ double fenv_hold;
+ *(uint64_t*)fenv_hold = *(uint64_t*)fenv_var 0x0007LL;
+ __builtin_mtfsf (0xff, fenv_hold); */
+
+ /* Mask to clear everything except for the rounding modes and non-IEEE
+ arithmetic flag. */
+ const unsigned HOST_WIDE_INT hold_exception_mask =
+HOST_WIDE_INT_UC (0x0007);
+
+ tree fenv_var = create_tmp_var (double_type_node, NULL);
+
+ tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
+
+ tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
+ tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
+build_int_cst (uint64_type_node, hold_exception_mask));
+
+ tree fenv_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node, fenv_llu_and);
+
+ tree hold_mtfsf = build_call_expr (mtfsf, 2,
+build_int_cst (unsigned_type_node, 0xff), fenv_mtfsf);
+
+ *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
+
+ /* Reload the value of fenv_hold to clear the exceptions. */
+
+ *clear = build_call_expr (mtfsf, 2,
+build_int_cst (unsigned_type_node, 0xff), fenv_mtfsf);
+
+ /* Generates the equivalent of feupdateenv (fenv_var)
+
+ double old_fenv = __builtin_mffs ();
+ double fenv_update;
+ *(uint64_t*)fenv_update = (*(uint64_t*)old 0x1f00LL) |
+(*(uint64_t*)fenv_var 0x1ff80fff);
+ __builtin_mtfsf (0xff, fenv_update); */
+
+ const unsigned HOST_WIDE_INT update_exception_mask =
+HOST_WIDE_INT_UC (0x1f00);
+ const unsigned HOST_WIDE_INT new_exception_mask =
+HOST_WIDE_INT_UC (0x1ff80fff);
+
+ tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, call_mffs);
+ tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
+old_llu, build_int_cst (uint64_type_node, update_exception_mask));
+
+ tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
+build_int_cst (uint64_type_node, new_exception_mask));
+
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
On Thu, 31 Jul 2014, David Edelsohn wrote: Thanks for implementing the FENV support. The patch generally looks good to me. My one concern is a detail in the implementation of update. I do not have enough experience with GENERIC to verify the details and it seems like it is missing building an outer COMPOUND_EXPR containing update_mffs and the CALL_EXPR for update mtfsf. I suppose what's actually odd there is that you have + tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs); + + tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, update_mffs); so you build a MODIFY_EXPR in void_type_node but then convert it with a VIEW_CONVERT_EXPR. If you'd built the MODIFY_EXPR in double_type_node then the VIEW_CONVERT_EXPR would be meaningful (the value of an assignment a = b being the new value of a), but reinterpreting a void value doesn't make sense. Or you could probably just use call_mffs directly in the VIEW_CONVERT_EXPR without explicitly creating the old_fenv variable. -- Joseph S. Myers jos...@codesourcery.com
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
Thanks for implementing the FENV support. The patch generally looks good to me. My one concern is a detail in the implementation of update. I do not have enough experience with GENERIC to verify the details and it seems like it is missing building an outer COMPOUND_EXPR containing update_mffs and the CALL_EXPR for update mtfsf. I would like someone to double check. Thanks, David
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
On Thu, 3 Jul 2014, Adhemerval Zanella wrote: + /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT): + + double fenv_clear = __builtin_mffs (); + *(uint64_t)fenv_clear = 0xLL; + __builtin_mtfsf (0xff, fenv_clear); */ + + /* Mask to clear everything except for the rounding modes and non-IEEE + arithmetic flag. */ + const unsigned HOST_WIDE_INT clear_exception_mask = +HOST_WIDE_INT_UC (0x); This mask is different from the one before, and it looks like it's clearing the rounding mode bits. You probably don't need to do this masking here. In general, for the feclearexcept operation it's sufficient to reuse the same status/control register settings as you used in the feholdexcept operation - nothing (visible at C level) should have changed since that call except for the exception flags, and anyway when the feclearexcept operation is executed, the logical idea is to make things as if the floating-point operation preceding the failed compare-and-exchange never happened, so reusing the register setting makes logical sense in that way as well. (On x86, that reuse is what's done for SSE floating point; for 387 we use fnclex in both operations, and never explicitly compute a control word setting with exceptions cleared and masked.) Other than that I don't see any issues with the changes (this is not an approval of the patch, however). The testsuite changes are OK. -- Joseph S. Myers jos...@codesourcery.com
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
Ping.
On 03-07-2014 18:08, Adhemerval Zanella wrote:
This patch implements the TARGET_ATOMIC_ASSIGN_EXPAND_FENV for
powerpc-fpu. I have to adjust current c11-atomic-exec-5 testcase
because for IBM long double 0 += LDBL_MAX might generate
overflow/underflow in internal __gcc_qadd calculations.
The c11-atomic-exec-5 now passes for linux/powerpc, checked on
powerpc32-linux-fpu, powerpc64-linux, and powerpc64le-linux.
--
2014-07-03 Adhemerval Zanella azane...@linux.vnet.ibm.com
gcc:
* config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): New
function.
gcc/testsuite:
* gcc.dg/atomic/c11-atomic-exec-5.c
(test_main_long_double_add_overflow): Define and run only for
LDBL_MANT_DIG != 106.
(test_main_complex_long_double_add_overflow): Likewise.
(test_main_long_double_sub_overflow): Likewise.
(test_main_complex_long_double_sub_overflow): Likewise.
---
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index bf67e72..75a2a45 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1621,6 +1621,9 @@ static const struct attribute_spec
rs6000_attribute_table[] =
#undef TARGET_CAN_USE_DOLOOP_P
#define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
+
+#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
+#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
/* Processor table. */
@@ -32991,6 +32994,105 @@ emit_fusion_gpr_load (rtx *operands)
return ;
}
+/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
+
+static void
+rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
+{
+ if (!TARGET_HARD_FLOAT || !TARGET_FPRS)
+return;
+
+ tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
+ tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
+ tree call_mffs = build_call_expr (mffs, 0);
+
+ /* Generates the equivalent of feholdexcept (fenv_var)
+
+ *fenv_var = __builtin_mffs ();
+ double fenv_hold;
+ *(uint64_t*)fenv_hold = *(uint64_t*)fenv_var 0x0007LL;
+ __builtin_mtfsf (0xff, fenv_hold); */
+
+ /* Mask to clear everything except for the rounding modes and non-IEEE
+ arithmetic flag. */
+ const unsigned HOST_WIDE_INT hold_exception_mask =
+HOST_WIDE_INT_C (0x0007);
+
+ tree fenv_var = create_tmp_var (double_type_node, NULL);
+
+ tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
+
+ tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
+ tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
+build_int_cst (uint64_type_node, hold_exception_mask));
+
+ tree fenv_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
fenv_llu_and);
+
+ tree hold_mtfsf = build_call_expr (mtfsf, 2,
+build_int_cst (unsigned_type_node, 0xff), fenv_mtfsf);
+
+ *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
+
+ /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
+
+ double fenv_clear = __builtin_mffs ();
+ *(uint64_t)fenv_clear = 0xLL;
+ __builtin_mtfsf (0xff, fenv_clear); */
+
+ /* Mask to clear everything except for the rounding modes and non-IEEE
+ arithmetic flag. */
+ const unsigned HOST_WIDE_INT clear_exception_mask =
+HOST_WIDE_INT_UC (0x);
+
+ tree fenv_clear = create_tmp_var (double_type_node, NULL);
+
+ tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear,
call_mffs);
+
+ tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node,
fenv_var);
+ tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
+fenv_clean_llu, build_int_cst (uint64_type_node, clear_exception_mask));
+
+ tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
+fenv_clear_llu_and);
+
+ tree clear_mtfsf = build_call_expr (mtfsf, 2,
+build_int_cst (unsigned_type_node, 0xff), fenv_clear_mtfsf);
+
+ *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
+
+ /* Generates the equivalent of feupdateenv (fenv_var)
+
+ double old_fenv = __builtin_mffs ();
+ double fenv_update;
+ *(uint64_t*)fenv_update = (*(uint64_t*)old 0x1f00LL) |
+(*(uint64_t*)fenv_var 0x1ff80fff);
+ __builtin_mtfsf (0xff, fenv_update); */
+
+ const unsigned HOST_WIDE_INT update_exception_mask =
+HOST_WIDE_INT_UC (0x1f00);
+ const unsigned HOST_WIDE_INT new_exception_mask =
+HOST_WIDE_INT_UC (0x1ff80fff);
+
+ tree old_fenv = create_tmp_var (double_type_node, NULL);
+ tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv,
call_mffs);
+
+ tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, update_mffs);
+ tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
+old_llu, build_int_cst (uint64_type_node,
Re: [PATCH] PowerPC: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV
Adhemerval, This looks very good. Thanks for helping with the FENV implementation. I will discuss this with some GIMPLE experts during Cauldron. I want to check that the GIMPLE is correct before approving this. Thanks, David
