On Thu, Dec 01, 2016 at 05:26:16PM +0100, Dominik Vogt wrote: > The following patch series adds some patterns for enhanced use of > the r[ixo]sbg instructions on S/390. > > - 0001-* fixes some test regressions with the existing risbg > patterns that are broken because of recent trunkt changes. > > - 0002-* adds new patterns for the r[xo]sbg instructions and an > SI mode variant of "extzv". > > For details, please chech the commit comments of the patches. All > patches have been bootstrapped on s390x biarch and regression > tested on s390x biarch and s390.
Risbg patch. Ciao Dominik ^_^ ^_^ -- Dominik Vogt IBM Germany
gcc/ChangeLog-fix-risbg-tests * config/s390/s390.md ("*trunc_sidi_and_subreg_ze<clobbercc_or_nocc>") ("*extzvdi_top"): New patterns. gcc/testsuite/ChangeLog-fix-risbg-tests * gcc.target/s390/risbg-ll-1.c (f43, f44): Adapt regexps. * gcc.target/s390/risbg-ll-2.c (f9): Ditto.
>From 59c63c47602d0f32948758b8ce9f36d55b8f8f39 Mon Sep 17 00:00:00 2001 From: Dominik Vogt <v...@linux.vnet.ibm.com> Date: Fri, 25 Nov 2016 10:33:03 +0100 Subject: [PATCH 1/2] S/390: Fix risbg pattern tests. With r242812 combine generates zero_extract instead of lshiftrt in some case The test cases are updated to reflect this, but the pattern "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" is not used anymore. Add new pattern "*trunc_sidi_and_subreg_ze<clobbercc_or_nocc>" to take over the one's work. Add a variant "*extzv<mod>_top" that deals with zero_extracts that can be expressed as a simple right shift, which has the advantage of not clobbering the condition code. --- gcc/config/s390/s390.md | 33 ++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/s390/risbg-ll-1.c | 8 ++++---- gcc/testsuite/gcc.target/s390/risbg-ll-2.c | 2 +- 3 files changed, 38 insertions(+), 5 deletions(-) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index aaf8427..43b9371 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -3755,6 +3755,24 @@ } }) +; Special case where zero_extract can be written as a right-shift. +(define_insn_and_split "*extzvdi_top" + [(set (match_operand:DI 0 "register_operand" "=d") + (zero_extract:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand 2 "const_int_operand" "") ; size + (const_int 0))) ; start + ] + "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), 0, 64)" + "#" + "" + [(set (match_dup 0) + (lshiftrt:DI (match_dup 1) (match_dup 2)))] +{ + operands[2] = GEN_INT (64 - INTVAL (operands[2])); +}) + +; In all other cases try risbg. (define_insn "*extzv<mode><clobbercc_or_nocc>" [(set (match_operand:GPR 0 "register_operand" "=d") (zero_extract:GPR @@ -4045,6 +4063,21 @@ [(set_attr "op_type" "RIE") (set_attr "z10prop" "z10_super_E1")]) +(define_insn "*trunc_sidi_and_subreg_ze<clobbercc_or_nocc>" + [(set (match_operand:SI 0 "register_operand" "=d") + (and:SI + (subreg:SI (zero_extract:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand 2 "const_int_operand" "") ; size + (match_operand 3 "const_int_operand" "")) ; pos + 4) + (match_operand:SI 4 "contiguous_bitmask_nowrap_operand" "")))] + "<z10_or_zEC12_cond> + && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)" + "<risbg_n>\t%0,%1,%t4,128+%f4,%2+%3" + [(set_attr "op_type" "RIE") + (set_attr "z10prop" "z10_super_E1")]) + ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) ; -> z = y >> d; z = risbg; diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-1.c b/gcc/testsuite/gcc.target/s390/risbg-ll-1.c index 30350d0..17a9000 100644 --- a/gcc/testsuite/gcc.target/s390/risbg-ll-1.c +++ b/gcc/testsuite/gcc.target/s390/risbg-ll-1.c @@ -478,8 +478,8 @@ i64 f42 (t42 v_x) // Check that we get the case where a 64-bit shift is used by a 32-bit and. i32 f43 (i64 v_x) { - /* { dg-final { scan-assembler "f43:\n\trisbg\t%r2,%r2,32,128\\\+61,64-12" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f43:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\trisbg\t%r2,%r3,32,128\\\+61,64-12" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f43:\n\trisbg\t%r2,%r2,32,128\\\+61,32\\\+20" { target { lp64 } } } } */ + /* { dg-final { scan-assembler "f43:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\trisbg\t%r2,%r3,32,128\\\+61,32\\\+20" { target { ! lp64 } } } } */ i64 v_shr3 = ((ui64)v_x) >> 12; i32 v_shr3_tr = (ui32)v_shr3; i32 v_conv = v_shr3_tr & -4; @@ -489,8 +489,8 @@ i32 f43 (i64 v_x) // Check that we don't get the case where the 32-bit and mask is not contiguous i32 f44 (i64 v_x) { - /* { dg-final { scan-assembler "f44:\n\tsrlg\t%r2,%r2,12" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f44:\n\tsrlg\t%r2,%r3,12\n\tnilf\t%r2,10" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f44:\n\(\t.*\n\)*\tngr\t" { target { lp64 } } } } */ + /* { dg-final { scan-assembler "f44:\n\(\t.*\n\)*\tnilf\t" { target { ! lp64 } } } } */ i64 v_shr4 = ((ui64)v_x) >> 12; i32 v_conv = (ui32)v_shr4; i32 v_and = v_conv & 10; diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c index 6588dc7..3628192 100644 --- a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c +++ b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c @@ -100,7 +100,7 @@ i64 f8 (i64 v_a, i64 v_b) // ands with complement masks. i32 f9 (i64 v_x, i32 v_y) { - /* { dg-final { scan-assembler "f9:\n\trisbg\t%r3,%r2,48,63,64-48" { target { lp64 } }} } */ + /* { dg-final { scan-assembler "f9:\n\trisbg\t%r3,%r2,64-16,63,16\\\+0" { target { lp64 } }} } */ /* { dg-final { scan-assembler "f9:\n\trisbg\t%r4,%r2,32\\+16,63,64-16" { target { ! lp64 } }} } */ i64 v_shr6 = ((ui64)v_x) >> 48; i32 v_conv = (ui32)v_shr6; -- 2.3.0