Re: Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp
Hi Kito & Jeff A new series for zcmp(https://patchwork.sourceware.org/project/gcc/list/?series=23929) to: 1. solve the 2 issues Kito catched 2. rebase The new series would be a replacement of the following: https://patchwork.sourceware.org/project/gcc/list/?series=21577 https://patchwork.sourceware.org/project/gcc/patch/[email protected]/ The rest of zcmp patches will be send out after the new series accepted to avoid rebase again an again. BR, Fei On 2023-08-20 18:53 Fei Gao wrote: > > >Hi Kito > >This issue is due to zcmp and shrink-wrap-separate conflict, >which has been addressed by an under-review patch. >[PATCH 0/2] resolve confilct between RISC-V zcmp and shrink-wrap-separate >https://patchwork.sourceware.org/project/gcc/list/?series=21577 >https://www.mail-archive.com/[email protected]/msg311487.html > >I'm making [PATCH 1/4][V5][RISC-V] support cm.push cm.pop cm.popret in zcmp >for the 1st issue you catched. >Please let me know if you want me to merge >https://www.mail-archive.com/[email protected]/msg311486.html >into [PATCH 1/4][V5][RISC-V]. > >BR, >Fei >On 2023-08-16 16:38 Kito Cheng wrote: >> >>Another fail case for CFI: >> >>$ riscv64-unknown-elf-gcc _mulhc3.i >>-march=rv64imafd_zicsr_zifencei_zca_zcmp -mabi=lp64d -g -O2 -o >>_mulhc3.s >> >>typedef float a __attribute__((mode(HF))); >>b, c; >>f() { >> a a, d, e = a + d; >> if (g() && e) >> c = b; >>} >> >> >>0x10e508a maybe_record_trace_start >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2584 >>0x10e58fb scan_trace >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2784 >>0x10e5fab create_cfi_notes >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2938 >>0x10e6ee4 execute_dwarf2_frame >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:3309 >>0x10e7c5a execute >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:3797 >> >>On Wed, Aug 16, 2023 at 4:33 PM Kito Cheng wrote: >>> >>> Hi Fei: >>> >>> Tried to use Jiawei's patch to test this patch and found some issue: >>> >>> >>> > @@ -5430,13 +5632,15 @@ riscv_expand_prologue (void) >>> > /* Save the registers. */ >>> > if ((frame->mask | frame->fmask) != 0) >>> > { >>> > - HOST_WIDE_INT step1 = riscv_first_stack_step (frame, >>> > remaining_size); >>> > - >>> > - insn = gen_add3_insn (stack_pointer_rtx, >>> > - stack_pointer_rtx, >>> > - GEN_INT (-step1)); >>> > - RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; >>> > - remaining_size -= step1; >>> > + if (known_gt (remaining_size, frame->frame_pointer_offset)) >>> > + { >>> > + HOST_WIDE_INT step1 = riscv_first_stack_step (frame, >>> > remaining_size); >>> > + remaining_size -= step1; >>> > + insn = gen_add3_insn (stack_pointer_rtx, >>> > + stack_pointer_rtx, >>> > + GEN_INT (-step1)); >>> > + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; >>> > + } >>> > riscv_for_each_saved_reg (remaining_size, riscv_save_reg, false, >>> >false); >>> > } >>> > >>> >>> I hit some issue here during building libgcc, I use >>> riscv-gnu-toolchain with --with-arch=rv64gzca_zcmp >>> >>> And the error message is: >>> >>> In file included from >>> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind-dw2.c:1471: >>> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc: In >>> function '_Unwind_Backtrace': >>> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc:330:1: >>> internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176 >>> 330 | } >>> | ^ >>> 0x83753a gen_reg_rtx(machine_mode) >>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/emit-rtl.cc:1176 >>> 0xf5566f maybe_legitimize_operand >>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8047 >>> 0xf5566f maybe_legitimize_operands(insn_code, unsigned int, unsigned >>> int, expand_operand*) >>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8191 >>> 0xf511d9 maybe_gen_insn(insn_code, unsigned int, expand_operand*) >>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8210 >>> 0xf58539 expand_binop_directly >>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1452 >>> 0xf5 expand_binop(machine_mode, optab_tag, rtx_def*, rtx_def*, >>> rtx_def*, int, optab_methods) >>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1539 >>> 0xcbfdd0 force_operand(rtx_def*, rtx_def*) >>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:8231 >>> 0xc8fca1 force_reg(machine_mode, rtx_def*) >>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/explow.cc:687 >>> 0x144b8cd riscv_force_temporary >>> >>>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1531 >>> 0x144b8cd riscv_force_address >>> >>>../../../../riscv-gnu-toolc
Re: Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp
Hi Kito This issue is due to zcmp and shrink-wrap-separate conflict, which has been addressed by an under-review patch. [PATCH 0/2] resolve confilct between RISC-V zcmp and shrink-wrap-separate https://patchwork.sourceware.org/project/gcc/list/?series=21577 https://www.mail-archive.com/[email protected]/msg311487.html I'm making [PATCH 1/4][V5][RISC-V] support cm.push cm.pop cm.popret in zcmp for the 1st issue you catched. Please let me know if you want me to merge https://www.mail-archive.com/[email protected]/msg311486.html into [PATCH 1/4][V5][RISC-V]. BR, Fei On 2023-08-16 16:38 Kito Cheng wrote: > >Another fail case for CFI: > >$ riscv64-unknown-elf-gcc _mulhc3.i >-march=rv64imafd_zicsr_zifencei_zca_zcmp -mabi=lp64d -g -O2 -o >_mulhc3.s > >typedef float a __attribute__((mode(HF))); >b, c; >f() { > a a, d, e = a + d; > if (g() && e) > c = b; >} > > >0x10e508a maybe_record_trace_start > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2584 >0x10e58fb scan_trace > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2784 >0x10e5fab create_cfi_notes > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2938 >0x10e6ee4 execute_dwarf2_frame > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:3309 >0x10e7c5a execute > ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:3797 > >On Wed, Aug 16, 2023 at 4:33 PM Kito Cheng wrote: >> >> Hi Fei: >> >> Tried to use Jiawei's patch to test this patch and found some issue: >> >> >> > @@ -5430,13 +5632,15 @@ riscv_expand_prologue (void) >> > /* Save the registers. */ >> > if ((frame->mask | frame->fmask) != 0) >> > { >> > - HOST_WIDE_INT step1 = riscv_first_stack_step (frame, >> > remaining_size); >> > - >> > - insn = gen_add3_insn (stack_pointer_rtx, >> > - stack_pointer_rtx, >> > - GEN_INT (-step1)); >> > - RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; >> > - remaining_size -= step1; >> > + if (known_gt (remaining_size, frame->frame_pointer_offset)) >> > + { >> > + HOST_WIDE_INT step1 = riscv_first_stack_step (frame, >> > remaining_size); >> > + remaining_size -= step1; >> > + insn = gen_add3_insn (stack_pointer_rtx, >> > + stack_pointer_rtx, >> > + GEN_INT (-step1)); >> > + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; >> > + } >> > riscv_for_each_saved_reg (remaining_size, riscv_save_reg, false, >> >false); >> > } >> > >> >> I hit some issue here during building libgcc, I use >> riscv-gnu-toolchain with --with-arch=rv64gzca_zcmp >> >> And the error message is: >> >> In file included from >> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind-dw2.c:1471: >> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc: In >> function '_Unwind_Backtrace': >> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc:330:1: >> internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176 >> 330 | } >> | ^ >> 0x83753a gen_reg_rtx(machine_mode) >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/emit-rtl.cc:1176 >> 0xf5566f maybe_legitimize_operand >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8047 >> 0xf5566f maybe_legitimize_operands(insn_code, unsigned int, unsigned >> int, expand_operand*) >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8191 >> 0xf511d9 maybe_gen_insn(insn_code, unsigned int, expand_operand*) >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8210 >> 0xf58539 expand_binop_directly >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1452 >> 0xf5 expand_binop(machine_mode, optab_tag, rtx_def*, rtx_def*, >> rtx_def*, int, optab_methods) >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1539 >> 0xcbfdd0 force_operand(rtx_def*, rtx_def*) >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:8231 >> 0xc8fca1 force_reg(machine_mode, rtx_def*) >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/explow.cc:687 >> 0x144b8cd riscv_force_temporary >> >>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1531 >> 0x144b8cd riscv_force_address >> >>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1528 >> 0x144b8cd riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*) >> >>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:2387 >> 0x1af063e gen_movdf(rtx_def*, rtx_def*) >> >>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.md:2107 >> 0xcba503 rtx_insn* insn_gen_fn::operator()> rtx_def*>(rtx_def*, rtx_def*) const >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/recog.h:411 >> 0xcba503 emit_move_insn_1(rtx_def*, rtx_def*) >> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:4164 >> 0x143d6c4 riscv_emit_move(rtx_def*, rtx_def*) >
Re: Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp
Hi Kito
Root cause has been identified.
Here's the frame layout fo the TC, please use courier font :)
+---+
| |
| GPR save area 112 B |
| |
+---+
| |<-- fs0 is beyond sp based 12-bit
range
| FPR save area 96 B |
| |
+---+
| |
| local variables |<-- stack_pointer_rtx after
riscv_first_stack_step
| |
+---+
During stack frame allocation:
1. cm.push reserves 160 bytes, 112 for ra and sregs with 128-bit alignment as
per ABI, and additional 48 bytes for first 6 fprs.
2. riscv_first_stack_step reserves 2032 bytes for the rest 6 fprs and local
variables.
3. riscv_for_each_saved_reg tries to save fs0 which is beyond sp based 12-bit
range,
thus breaking gcc_assert (can_create_pseudo_p ()) in gen_reg_rtx when doing
force reg as it's already after reload complete.
I tried with a solution like saving first 6 fprs immediately after cm.push. It
seems working:)
I will fix epilogue correspondingly as well.
Thanks again for your test.
BR,
Fei
On 2023-08-16 16:33 Kito Cheng wrote:
>
>Hi Fei:
>
>Tried to use Jiawei's patch to test this patch and found some issue:
>
>
>> @@ -5430,13 +5632,15 @@ riscv_expand_prologue (void)
>> /* Save the registers. */
>> if ((frame->mask | frame->fmask) != 0)
>> {
>> - HOST_WIDE_INT step1 = riscv_first_stack_step (frame, remaining_size);
>> -
>> - insn = gen_add3_insn (stack_pointer_rtx,
>> - stack_pointer_rtx,
>> - GEN_INT (-step1));
>> - RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
>> - remaining_size -= step1;
>> + if (known_gt (remaining_size, frame->frame_pointer_offset))
>> + {
>> + HOST_WIDE_INT step1 = riscv_first_stack_step (frame,
>> remaining_size);
>> + remaining_size -= step1;
>> + insn = gen_add3_insn (stack_pointer_rtx,
>> + stack_pointer_rtx,
>> + GEN_INT (-step1));
>> + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
>> + }
>> riscv_for_each_saved_reg (remaining_size, riscv_save_reg, false,
>>false);
>> }
>>
>
>I hit some issue here during building libgcc, I use
>riscv-gnu-toolchain with --with-arch=rv64gzca_zcmp
>
>And the error message is:
>
>In file included from
>../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind-dw2.c:1471:
>../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc: In
>function '_Unwind_Backtrace':
>../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc:330:1:
>internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176
> 330 | }
> | ^
>0x83753a gen_reg_rtx(machine_mode)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/emit-rtl.cc:1176
>0xf5566f maybe_legitimize_operand
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8047
>0xf5566f maybe_legitimize_operands(insn_code, unsigned int, unsigned
>int, expand_operand*)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8191
>0xf511d9 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8210
>0xf58539 expand_binop_directly
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1452
>0xf5 expand_binop(machine_mode, optab_tag, rtx_def*, rtx_def*,
>rtx_def*, int, optab_methods)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1539
>0xcbfdd0 force_operand(rtx_def*, rtx_def*)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:8231
>0xc8fca1 force_reg(machine_mode, rtx_def*)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/explow.cc:687
>0x144b8cd riscv_force_temporary
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1531
>0x144b8cd riscv_force_address
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1528
>0x144b8cd riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:2387
>0x1af063e gen_movdf(rtx_def*, rtx_def*)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.md:2107
>0xcba503 rtx_insn* insn_gen_fn::operator()rtx_def*>(rtx_def*, rtx_def*) const
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/recog.h:411
>0xcba503 emit_move_insn_1(rtx_def*, rtx_def*)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:4164
>0x143d6c4 riscv_emit_move(rtx_def*, rtx_def*)
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1486
>0x143d6c4 riscv_save_reg
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/ris
Re: Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp
Hi Kito
Thanks for reporting these 2 issues.
Let me check and feedback you soon.
BR
Fei
On 2023-08-16 16:38 Kito Cheng wrote:
>
>Another fail case for CFI:
>
>$ riscv64-unknown-elf-gcc _mulhc3.i
>-march=rv64imafd_zicsr_zifencei_zca_zcmp -mabi=lp64d -g -O2 -o
>_mulhc3.s
>
>typedef float a __attribute__((mode(HF)));
>b, c;
>f() {
> a a, d, e = a + d;
> if (g() && e)
> c = b;
>}
>
>
>0x10e508a maybe_record_trace_start
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2584
>0x10e58fb scan_trace
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2784
>0x10e5fab create_cfi_notes
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2938
>0x10e6ee4 execute_dwarf2_frame
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:3309
>0x10e7c5a execute
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:3797
>
>On Wed, Aug 16, 2023 at 4:33 PM Kito Cheng wrote:
>>
>> Hi Fei:
>>
>> Tried to use Jiawei's patch to test this patch and found some issue:
>>
>>
>> > @@ -5430,13 +5632,15 @@ riscv_expand_prologue (void)
>> > /* Save the registers. */
>> > if ((frame->mask | frame->fmask) != 0)
>> > {
>> > - HOST_WIDE_INT step1 = riscv_first_stack_step (frame,
>> > remaining_size);
>> > -
>> > - insn = gen_add3_insn (stack_pointer_rtx,
>> > - stack_pointer_rtx,
>> > - GEN_INT (-step1));
>> > - RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
>> > - remaining_size -= step1;
>> > + if (known_gt (remaining_size, frame->frame_pointer_offset))
>> > + {
>> > + HOST_WIDE_INT step1 = riscv_first_stack_step (frame,
>> > remaining_size);
>> > + remaining_size -= step1;
>> > + insn = gen_add3_insn (stack_pointer_rtx,
>> > + stack_pointer_rtx,
>> > + GEN_INT (-step1));
>> > + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
>> > + }
>> > riscv_for_each_saved_reg (remaining_size, riscv_save_reg, false,
>> >false);
>> > }
>> >
>>
>> I hit some issue here during building libgcc, I use
>> riscv-gnu-toolchain with --with-arch=rv64gzca_zcmp
>>
>> And the error message is:
>>
>> In file included from
>> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind-dw2.c:1471:
>> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc: In
>> function '_Unwind_Backtrace':
>> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc:330:1:
>> internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176
>> 330 | }
>> | ^
>> 0x83753a gen_reg_rtx(machine_mode)
>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/emit-rtl.cc:1176
>> 0xf5566f maybe_legitimize_operand
>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8047
>> 0xf5566f maybe_legitimize_operands(insn_code, unsigned int, unsigned
>> int, expand_operand*)
>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8191
>> 0xf511d9 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8210
>> 0xf58539 expand_binop_directly
>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1452
>> 0xf5 expand_binop(machine_mode, optab_tag, rtx_def*, rtx_def*,
>> rtx_def*, int, optab_methods)
>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1539
>> 0xcbfdd0 force_operand(rtx_def*, rtx_def*)
>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:8231
>> 0xc8fca1 force_reg(machine_mode, rtx_def*)
>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/explow.cc:687
>> 0x144b8cd riscv_force_temporary
>>
>>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1531
>> 0x144b8cd riscv_force_address
>>
>>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1528
>> 0x144b8cd riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)
>>
>>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:2387
>> 0x1af063e gen_movdf(rtx_def*, rtx_def*)
>>
>>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.md:2107
>> 0xcba503 rtx_insn* insn_gen_fn::operator()> rtx_def*>(rtx_def*, rtx_def*) const
>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/recog.h:411
>> 0xcba503 emit_move_insn_1(rtx_def*, rtx_def*)
>> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:4164
>> 0x143d6c4 riscv_emit_move(rtx_def*, rtx_def*)
>>
>>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1486
>> 0x143d6c4 riscv_save_reg
>>
>>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:5715
>> 0x143e2b9 riscv_for_each_saved_reg
>>
>>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:5904
>> 0x14480d0 riscv_expand_prologue()
>>
>>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:6156
>> 0x1af57fb gen_prologue()
>>
>>../../../.
Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp
Another fail case for CFI:
$ riscv64-unknown-elf-gcc _mulhc3.i
-march=rv64imafd_zicsr_zifencei_zca_zcmp -mabi=lp64d -g -O2 -o
_mulhc3.s
typedef float a __attribute__((mode(HF)));
b, c;
f() {
a a, d, e = a + d;
if (g() && e)
c = b;
}
0x10e508a maybe_record_trace_start
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2584
0x10e58fb scan_trace
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2784
0x10e5fab create_cfi_notes
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:2938
0x10e6ee4 execute_dwarf2_frame
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:3309
0x10e7c5a execute
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/dwarf2cfi.cc:3797
On Wed, Aug 16, 2023 at 4:33 PM Kito Cheng wrote:
>
> Hi Fei:
>
> Tried to use Jiawei's patch to test this patch and found some issue:
>
>
> > @@ -5430,13 +5632,15 @@ riscv_expand_prologue (void)
> >/* Save the registers. */
> >if ((frame->mask | frame->fmask) != 0)
> > {
> > - HOST_WIDE_INT step1 = riscv_first_stack_step (frame, remaining_size);
> > -
> > - insn = gen_add3_insn (stack_pointer_rtx,
> > - stack_pointer_rtx,
> > - GEN_INT (-step1));
> > - RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
> > - remaining_size -= step1;
> > + if (known_gt (remaining_size, frame->frame_pointer_offset))
> > +{
> > + HOST_WIDE_INT step1 = riscv_first_stack_step (frame,
> > remaining_size);
> > + remaining_size -= step1;
> > + insn = gen_add3_insn (stack_pointer_rtx,
> > +stack_pointer_rtx,
> > +GEN_INT (-step1));
> > + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
> > +}
> >riscv_for_each_saved_reg (remaining_size, riscv_save_reg, false,
> > false);
> > }
> >
>
> I hit some issue here during building libgcc, I use
> riscv-gnu-toolchain with --with-arch=rv64gzca_zcmp
>
> And the error message is:
>
> In file included from
> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind-dw2.c:1471:
> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc: In
> function '_Unwind_Backtrace':
> ../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc:330:1:
> internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176
> 330 | }
> | ^
> 0x83753a gen_reg_rtx(machine_mode)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/emit-rtl.cc:1176
> 0xf5566f maybe_legitimize_operand
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8047
> 0xf5566f maybe_legitimize_operands(insn_code, unsigned int, unsigned
> int, expand_operand*)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8191
> 0xf511d9 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8210
> 0xf58539 expand_binop_directly
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1452
> 0xf5 expand_binop(machine_mode, optab_tag, rtx_def*, rtx_def*,
> rtx_def*, int, optab_methods)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1539
> 0xcbfdd0 force_operand(rtx_def*, rtx_def*)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:8231
> 0xc8fca1 force_reg(machine_mode, rtx_def*)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/explow.cc:687
> 0x144b8cd riscv_force_temporary
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1531
> 0x144b8cd riscv_force_address
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1528
> 0x144b8cd riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:2387
> 0x1af063e gen_movdf(rtx_def*, rtx_def*)
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.md:2107
> 0xcba503 rtx_insn* insn_gen_fn::operator() rtx_def*>(rtx_def*, rtx_def*) const
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/recog.h:411
> 0xcba503 emit_move_insn_1(rtx_def*, rtx_def*)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:4164
> 0x143d6c4 riscv_emit_move(rtx_def*, rtx_def*)
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1486
> 0x143d6c4 riscv_save_reg
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:5715
> 0x143e2b9 riscv_for_each_saved_reg
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:5904
> 0x14480d0 riscv_expand_prologue()
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:6156
> 0x1af57fb gen_prologue()
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.md:2816
> 0x143c746 target_gen_prologue
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.md:3302
>
>
> Reduced case:
>
> $ riscv64-unknown-elf-gcc -march=rv64imafd_zicsr_
Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp
Hi Fei:
Tried to use Jiawei's patch to test this patch and found some issue:
> @@ -5430,13 +5632,15 @@ riscv_expand_prologue (void)
>/* Save the registers. */
>if ((frame->mask | frame->fmask) != 0)
> {
> - HOST_WIDE_INT step1 = riscv_first_stack_step (frame, remaining_size);
> -
> - insn = gen_add3_insn (stack_pointer_rtx,
> - stack_pointer_rtx,
> - GEN_INT (-step1));
> - RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
> - remaining_size -= step1;
> + if (known_gt (remaining_size, frame->frame_pointer_offset))
> +{
> + HOST_WIDE_INT step1 = riscv_first_stack_step (frame,
> remaining_size);
> + remaining_size -= step1;
> + insn = gen_add3_insn (stack_pointer_rtx,
> +stack_pointer_rtx,
> +GEN_INT (-step1));
> + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
> +}
>riscv_for_each_saved_reg (remaining_size, riscv_save_reg, false,
> false);
> }
>
I hit some issue here during building libgcc, I use
riscv-gnu-toolchain with --with-arch=rv64gzca_zcmp
And the error message is:
In file included from
../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind-dw2.c:1471:
../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc: In
function '_Unwind_Backtrace':
../../../../../riscv-gnu-toolchain-trunk/gcc/libgcc/unwind.inc:330:1:
internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1176
330 | }
| ^
0x83753a gen_reg_rtx(machine_mode)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/emit-rtl.cc:1176
0xf5566f maybe_legitimize_operand
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8047
0xf5566f maybe_legitimize_operands(insn_code, unsigned int, unsigned
int, expand_operand*)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8191
0xf511d9 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:8210
0xf58539 expand_binop_directly
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1452
0xf5 expand_binop(machine_mode, optab_tag, rtx_def*, rtx_def*,
rtx_def*, int, optab_methods)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs.cc:1539
0xcbfdd0 force_operand(rtx_def*, rtx_def*)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:8231
0xc8fca1 force_reg(machine_mode, rtx_def*)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/explow.cc:687
0x144b8cd riscv_force_temporary
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1531
0x144b8cd riscv_force_address
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1528
0x144b8cd riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:2387
0x1af063e gen_movdf(rtx_def*, rtx_def*)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.md:2107
0xcba503 rtx_insn* insn_gen_fn::operator()(rtx_def*, rtx_def*) const
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/recog.h:411
0xcba503 emit_move_insn_1(rtx_def*, rtx_def*)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/expr.cc:4164
0x143d6c4 riscv_emit_move(rtx_def*, rtx_def*)
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:1486
0x143d6c4 riscv_save_reg
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:5715
0x143e2b9 riscv_for_each_saved_reg
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:5904
0x14480d0 riscv_expand_prologue()
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.cc:6156
0x1af57fb gen_prologue()
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.md:2816
0x143c746 target_gen_prologue
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/config/riscv/riscv.md:3302
Reduced case:
$ riscv64-unknown-elf-gcc -march=rv64imafd_zicsr_zifencei_zca_zcmp
-mabi=lp64d unwind-dw2.i -Os
typedef struct {
struct {
struct {
struct {
long a
}
} a[129]
}
} b;
struct c {
void *a[129]
} d() {
struct c a;
__builtin_unwind_init();
b e;
f(a, &e);
}
Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp
Seems there are some indent format problems in the patch, could you fix them :) ``` patch:509: indent with spaces. x_save_size = riscv_stack_align (num_multi_push * UNITS_PER_WORD); error: patch failed: gcc/config/riscv/riscv.cc:5652 error: gcc/config/riscv/riscv.cc: patch does not apply ``` > -原始邮件- > 发件人: "Fei Gao" > 发送时间: 2023-06-07 13:52:12 (星期三) > 收件人: [email protected] > 抄送: [email protected], [email protected], [email protected], [email protected], [email protected], "Fei Gao" > 主题: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp > > Zcmp can share the same logic as save-restore in stack allocation: pre-allocation > by cm.push, step 1 and step 2. > > please be noted cm.push pushes ra, s0-s11 in reverse order than what save-restore does. > So adaption has been done in .cfi directives in my patch. > > Signed-off-by: Fei Gao > > gcc/ChangeLog: > > * config/riscv/iterators.md > slot0_offset: slot 0 offset in stack GPRs area in bytes > slot1_offset: slot 1 offset in stack GPRs area in bytes > slot2_offset: likewise > slot3_offset: likewise > slot4_offset: likewise > slot5_offset: likewise > slot6_offset: likewise > slot7_offset: likewise > slot8_offset: likewise > slot9_offset: likewise > slot10_offset: likewise > slot11_offset: likewise > slot12_offset: likewise > * config/riscv/predicates.md > (stack_push_up_to_ra_operand): predicates of stack adjust pushing ra > (stack_push_up_to_s0_operand): predicates of stack adjust pushing ra, s0 > (stack_push_up_to_s1_operand): likewise > (stack_push_up_to_s2_operand): likewise > (stack_push_up_to_s3_operand): likewise > (stack_push_up_to_s4_operand): likewise > (stack_push_up_to_s5_operand): likewise > (stack_push_up_to_s6_operand): likewise > (stack_push_up_to_s7_operand): likewise > (stack_push_up_to_s8_operand): likewise > (stack_push_up_to_s9_operand): likewise > (stack_push_up_to_s11_operand): likewise > (stack_pop_up_to_ra_operand): predicates of stack adjust poping ra > (stack_pop_up_to_s0_operand): predicates of stack adjust poping ra, s0 > (stack_pop_up_to_s1_operand): likewise > (stack_pop_up_to_s2_operand): likewise > (stack_pop_up_to_s3_operand): likewise > (stack_pop_up_to_s4_operand): likewise > (stack_pop_up_to_s5_operand): likewise > (stack_pop_up_to_s6_operand): likewise > (stack_pop_up_to_s7_operand): likewise > (stack_pop_up_to_s8_operand): likewise > (stack_pop_up_to_s9_operand): likewise > (stack_pop_up_to_s11_operand): likewise > * config/riscv/riscv-protos.h > (riscv_zcmp_valid_stack_adj_bytes_p):declaration > * config/riscv/riscv.cc (struct riscv_frame_info): comment change > (riscv_avoid_multi_push): helper function of riscv_use_multi_push > (riscv_use_multi_push): true if multi push is used > (riscv_multi_push_sregs_count): num of sregs in multi-push > (riscv_multi_push_regs_count): num of regs in multi-push > (riscv_16bytes_align): align to 16 bytes > (riscv_stack_align): moved to a better place > (riscv_save_libcall_count): no functional change > (riscv_compute_frame_info): add zcmp frame info > (riscv_adjust_multi_push_cfi_prologue): adjust cfi for cm.push > (riscv_gen_multi_push_pop_insn): gen function for multi push and pop > (riscv_expand_prologue): allocate stack by cm.push > (riscv_adjust_multi_pop_cfi_epilogue): adjust cfi for cm.pop[ret] > (riscv_expand_epilogue): allocate stack by cm.pop[ret] > (zcmp_base_adj): calculate stack adjustment base size > (zcmp_additional_adj): calculate stack adjustment additional size > (riscv_zcmp_valid_stack_adj_bytes_p): check if stack adjustment valid > * config/riscv/riscv.h (RETURN_ADDR_MASK): mask of ra > (S0_MASK): likewise > (S1_MASK): likewise > (S2_MASK): likewise > (S3_MASK): likewise > (S4_MASK): likewise > (S5_MASK): likewise > (S6_MASK): likewise > (S7_MASK): likewise > (S8_MASK): likewise > (S9_MASK): likewise > (S10_MASK): likewise > (S11_MASK): likewise > (MULTI_PUSH_GPR_MASK): GPR_MASK that cm.push can cover at most > (ZCMP_MAX_SPIMM): max spimm value > (ZCMP_SP_INC_STEP): zcmp sp increment step > (ZCMP_INVALID_S0S10_SREGS_COUNTS): num of s0-s10 > (ZCMP_S0S11_SREGS_COUNTS): num of s0-s11 > (ZCMP_MAX_GRP_SLOTS): max slots of pushing and poping in zcmp > * config/riscv/riscv.md: include zc.md > * config/riscv/zc.md: New file. machine description for zcmp > > gcc/testsuite/ChangeLog
